Patent Application
20070290981
The liquid crystal display panel 43 injects liquid crystal molecules between two glass substrates. M number of data lines S1 to Sm/2 and n number of gate lines G0 to Gn, which are formed on a lower glass substrate of the liquid crystal display panel, cross each other.
Odd-numbered data lines S1, S3, . . . , Sn−1 and even numbered data lines S1 to Sm which are adjacent to each other in the liquid crystal display panel 43 are electrically connected in each of the upper and lower ends to form a closed-loop of a shape which encompasses one pixel row.
The upper end of the odd-numbered data lines S1, S3, . . . Sn−1 and the even numbered data lines S1 to Sm which form the closed-loop is electrically connected to an output channel C1 to Cm/2 of the data drive circuit. One data line closed-loop is connected to one data output channel.
The gate lines G0 to Gn are patterned in a zigzag shape. The odd-numbered gate lines G1, G3, . . . , Gn−1 overlap the pixel electrodes 1B, 1D disposed in an even-numbered pixel row and are connected to gate electrodes of the TFT's disposed in the odd-numbered pixel row. The even-numbered gate lines G0, G2, G4, . . . , Gn overlap the pixel electrodes 1A, 1C disposed in an odd-numbered pixel row and are connected to gate electrodes of the TFT's disposed in the even-numbered pixel row.
The TFT's are connected to the crossing part of the data lines S1 to Sm and the gate lines G0 to Gn. The TFT's are disposed on the left side of the data lines S1 to Sm. The TFT's supply the data voltage from the data line S1 to Sm to the pixel electrode 1 in response to the scan signal from the gate drive circuit 42. A gate electrode of the TFT is connected to the gate line G0 to Gn and a drain electrode is connected to the data line S1 to Sm. A source electrode of the TFT is connected to the pixel electrode 1 of the liquid crystal cell Clc. A common voltage Vcom is supplied to a common electrode 2 that faces the pixel electrode 1.
A storage capacitor Cst is formed in each liquid crystal cell of the liquid crystal display panel 43. The storage capacitor Cst is formed by the pixel electrode and the gate line G0 to Gn that overlap each other with a dielectric therebetween. The storage capacitor Cst maintains a voltage of the liquid crystal cell Clc. In the pixels disposed in the first line of the utmost top end, no scan pulse is supplied to the storage capacitor Cst that is formed between the pixel electrode of the first line and the gate line G0 of the utmost top end to which the common voltage Vcom is supplied. In the pixels arranged in the same row, the storage capacitor Cst of the odd-numbered pixel is formed by the overlapping of the pixel electrode of the odd-numbered pixel and (n−1)th (where n is a positive integer of not less than 0) gate line with a dielectric layer therebetween. The storage capacitor Cst of the even-numbered pixel is formed by the overlapping of the pixel electrode of the even-numbered pixel and nth gate line with a dielectric layer therebetween. For example, the odd-numbered pixels and the even-numbered pixels arranged in the same row are overlapped with the gate lines which are different from each other.
A black matrix, a color filter and a common electrode (not shown) are formed on the upper glass substrate of the liquid crystal display panel 43. Alternatively, the common electrode is formed on the upper glass substrate in a vertical electric field drive method such as a TN (twisted nematic) mode and a VA (vertical alignment) mode, and is formed on the lower glass substrate together with the pixel electrode 1 in a horizontal electric field drive method such as an IPS (in plane switching) mode and a FFS (fringe field switching) mode.
A polarizer where the optical axes are at right angles to each other is stuck onto the upper glass substrate and the lower glass substrate of the liquid crystal display panel 43. An alignment film that sets a pre-tilt angle of liquid crystal is formed on the inner surface being in contact with the liquid crystal.
The data drive circuit 41 is composed of a plurality of data drive IC's of which each includes a shift register, a latch, a digital-analog converter and an output buffer. The data drive circuit 41 latches the digital video data under control of the timing controller 44 and converts the digital video data into a positive/negative analog gamma compensation voltage to be outputted through the data output channels C1 to Cm/2 as the positive/negative data voltage. The data output channels C1 to Cm/2 are connected to the data lines S1 to Sm in a ratio of 1:2. For example, one data output channel is connected to two data lines which are connected to the closed-loop. The data voltages are synchronized with the scan signals to be outputted for each unit of approximately ½ horizontal period to be supplied to the two data lines D1 to Dm that are connected to the closed-loop.
The gate drive circuit 42 is composed of a plurality of gate drive IC's that includes a shift register. A level shifter converts an output signal from the shift register into a signal of a suitable swing width that drives the liquid crystal cell. An output buffer is connected between the level shifter and the gate line G1 to Gn. The gate drive circuit 42 sequentially outputs the scan pulse for approximately ½ horizontal period.
The timing controller 44 receives a vertical/horizontal synchronization signal and a clock signal and generates a gate control signal GDC that controls the gate drive circuit 42 and a data control signal DDC that controls the data drive circuit 42. The gate control signal GCD includes, for example, a gate start pulse GSP, a gate shift clock signal GSC that drives the shift register, a gate output signal GOE. For example, the gate start pulse GSP and the gate shift clock signal GSP are generated to have a pulse width of an approximately ½ horizontal period so that a pulse width of the scan pulse is an approximately ½ horizontal period. The data control signal DDC includes, for example, a source start pulse GSP, a source shift clock SSC, a source output signal SOE, a polarity signal POL. For example, the source output signal SOE and the polarity signal POL are generated for each ½ horizontal period so that the positive/negative data voltage are outputted for an approximately ½ horizontal period.
Together with a timing control of the drive circuits 41 and 42, the timing controller 44 also acts to sample and re-align the digital video data RGB to supply to the data drive circuit 41.
In one embodiment, the liquid crystal display device has a low load, for example a low electrical resistance, because the number of TFT's connected to the data lines S1 to Sn is low and the width of the data line is broadened by a closed-loop structure. Accordingly, the liquid crystal display device of the present invention can delay the voltage drop and delay of the data voltage by reducing the load of the data lines, for example, RC load.
Referring to
During the first scan period of the approximately ½ horizontal period when the first scan pulse is supplied to the first gate line G1, the data voltage of the first line is supplied to the data lines S1 to Sn. In one embodiment, at this moment, only the TFT's disposed in the odd-numbered pixel row of the first line are turned on by the first scan pulse, thus the data voltage is charged in the pixel electrodes 1A, 1C of the odd-numbered pixel row.
In one embodiment, during the second scan period of the approximately ½ horizontal period when the second scan pulse is supplied to the second gate line G1, the data voltage of the second line is supplied to the data lines S1 to Sn. At this moment, only the TFT's disposed in the even-numbered pixel row of the first line are turned on by the second scan pulse. Accordingly, the data voltage is charged in the pixel electrodes 1B, 1D of the even-numbered pixel row. In one embodiment, while the even-numbered pixel row of the first line is selected, the TFT disposed in the odd-numbered pixel row of the first line is turned off by a gate low voltage, for example, a common voltage Vcom. Accordingly, in one embodiment, while the even-numbered pixel row of the first line is selected, the liquid crystal cells Clc are disposed in the odd-numbered pixel row maintain the data voltage supplied for the first scan period by the storage capacitor Cst that is formed between the 0th gate line G0 and the pixel electrode 1A. The 0th gate line G0 is only overlapped with the pixel electrodes 1A of the odd-numbered pixel row in the utmost top row and is not connected to the TFT's. The storage capacitor Cst can also be formed even in the even-numbered pixels of the utmost top row by the 0th gate line G0. Alternatively, the pixel electrode is formed by the overlapping of the first gate line G1 and the pixel electrode 1B in the even-numbered pixels in the utmost top row.
The scan pulse alternates between a gate high voltage VGH of not less than a threshold voltage of the TFT and a gate low voltage VGL of less than the threshold voltage of the TFT. In this embodiment, the gate low voltage VGL should be generated to be the same voltage as the common voltage Vcom supplied to the common electrode 2 so that the data voltage is fixedly kept in the liquid crystal cell Clc.
In one embodiment, the data line S1 to Sm is opened because of the pattern defect generated in the fabrication process, as in
The foregoing embodiment has been explained centering on the fact that one output channel of the data drive circuit 41 is connected by two data lines, but one output channel of the data drive circuit 41 can be connected to not less than two data lines. For example, it is possible that the data voltage is time-divided for each ⅓ horizontal period and the three data voltages that are sequentially generated from one output channel of the data drive circuit 41 are supplied to the three data lines in a time division manner. In this embodiment, the channel number of the data drive circuit 41 is reduced to ⅓ in comparison with the related art.
In one embodiment, the liquid crystal display device and the driving method thereof connect the data lines, which are more than an integer multiple of the number of output channels, to the output channel of the data drive IC and forms the closed-loop by shorting the data lines in the upper and lower ends, thereby making it possible to reduce the load by lowering the electrical resistance of the data line. In one embodiment, the data voltage is supplied to all the pixel arrays in the normal manner even though a part of the data lines connected to the closed-loop is broken.
Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2006-0054825 | Jun 2006 | KR | national |
