Patent Application
20150332651
The present invention relates to a liquid-crystal display device and a method for driving the same.
On a display unit of an active matrix-type liquid-crystal display device, a plurality of pixel formation portions are formed in a matrix. In each of the pixel formation portions, there are provided: a thin film transistor (hereinafter, referred to as a “TFT”) that operates as a switching element; and a pixel capacitance connected to a data signal line through the TFT. By switching on/off this TFT, a data signal for displaying an image is written as a data voltage into the pixel capacitance in the pixel formation portion. This data voltage is applied to a liquid crystal layer of the pixel formation portion, and changes an orientation direction of liquid crystal molecules to a direction corresponding to a voltage value of the data signal. As described above, the liquid-crystal display device controls a transmittance of the liquid crystal layer of each pixel formation portion, and thereby displays an image on the display unit.
In a case where the liquid-crystal display device as described above is used in a portable electronic instrument or the like, a reduction of power consumption thereof has been heretofore required. Accordingly, there is proposed a method for driving a display device, in which a pause period (also referred to as a “non-refresh period”) of turning all of gate lines as scanning signal lines of the liquid-crystal display device to a non-scanning state to pause refreshing of a display image after a scanning period (also referred to as a “refresh period”) of performing the refreshing by scanning the gate lines (for example, refer to Unexamined Japanese Patent Publication No. 2001-312253). In this pause period, for example, controlling signals and the like can be prevented from being given to a gate driver as a scanning signal line drive circuit and/or a source driver as a data signal line drive circuit. In such a way, operations of the gate driver and/or the source driver can be paused, and accordingly, the power consumption can be reduced. As in such a driving method described in Unexamined Japanese Patent Publication No. 2001-312253, the drive performed by providing the pause period after the refresh period is referred to, for example, as “pause drive”. Note that this pause drive is also referred to as “low frequency drive” or “intermittent drive”. The pause drive as described above is suitable for still image display.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2001-312253
[Patent Document 2] Japanese Patent Application Laid-Open No. 2011-85680
In the liquid-crystal display device as descried above, if a power supply is turned off when the image is displayed on the display unit, the TFT in each pixel formation portion also turns to an OFF state. The data voltage held in the pixel capacitance in the pixel formation portion at this time is held also thereafter in a state of maintaining a value thereof. That is to say, after the power supply is turned off, a stored charge equivalent to the data voltage remains in the pixel capacitance. Therefore, an off-leak current (current flowing through the TFT in the OFF state) of the TFT is relatively large as in a case where a channel layer of the TFT in the pixel formation portion is composed of amorphous silicon (a-Si) or the like, the data voltage held in the pixel capacitance is discharged through the TFT to the data signal line in a short time after the power supply is turned off. However, in a case where the off-leak current of the TFT is small (for example, a case of a TFT using an oxide semiconductor such as indium gallium zinc oxide for the channel layer), a direct current voltage is applied thereto continuously, whereby there occurs such a problem (hereinafter, referred to as a “problem such as generation of flicker”) that an afterimage formed by burn-in of liquid crystal is generated when the power supply is thereafter turned on, and that a flicker caused by deviation of an optimum common voltage is generated.
In order to address the above problem, there has been heretofore known a configuration in which voltages individually applied to a gate terminal, source terminal and common electrode of the TFT are controlled when the power supply of the liquid-crystal display device is turned off, whereby a voltage (stored charge in the pixel capacitance) held in the pixel capacitance in the pixel formation portion is discharged (hereinafter, this configuration is referred to as an “off-sequence configuration”) (for example, refer to Unexamined Japanese Patent Publication No. 2011-85680).
However, the inventors of this application have found out that, in the liquid-crystal display device that performs the above-described pause drive, even in a case of adopting the off-sequence configuration for discharge in order to solve the problem such as the generation of the flicker, which is caused by the stored charge in the pixel capacitance after the power supply is turned off, the inventors have found out that the problem such as the generation of the flicker is not solved.
In this connection, it is an object of the present invention to provide a liquid-crystal display device, in which the problem such as the generation of the flicker does not occur even in the case of performing the pause drive, and to provide a method for driving the liquid-crystal display device.
A first aspect of the present invention is directed to a liquid-crystal display device that displays an image represented by input image data, by applying a voltage corresponding to the input image data, to a liquid crystal layer in a display unit, the liquid-crystal display device comprising:
a drive unit configured to apply the voltage to the liquid crystal layer, the voltage corresponding to the input image data; and
a display control unit configured to control the drive unit upon receiving an OFF signal instructing OFF of a power supply of the liquid-crystal display device, so that a polarity bias of the voltage applied to the liquid crystal layer is reduced from a time when the OFF signal is inputted until the power supply is turned off.
According to a second aspect of the present invention, in the first aspect of the invention,
the display unit includes a plurality of pixel formation portions composed so as to hold the voltage to be applied to the liquid crystal layer, as a data voltage, and
the display control unit includes:
a bias movement determination unit configured to determine whether the polarity bias is in an increasing direction or in a decreasing direction at a point of time when the OFF signal is inputted; and
a balance control unit configured to control the drive unit in a case where the bias movement determination unit determines that the polarity bias is in the increasing direction, so that the polarity bias is reduced after performing polarity reverse refreshment of writing a data voltage into the plurality of pixel formation portions, the data voltage reversing the polarity of the applied voltage to the liquid crystal layer, and configured to control the drive unit in a case where the bias movement determination unit determines that the polarity bias is in the decreasing direction, so that the polarity bias is reduced without performing the polarity reverse refreshment.
According to a third aspect of the present invention, in the second aspect of the invention,
the display control unit further includes a polarity bias calculation unit configured to obtain a degree of the polarity bias of the voltage applied to the liquid crystal layer, and
the polarity bias calculation unit obtains a difference between a first number of frames and a second number of frames as a polarity bias count value indicating the degree of the polarity bias, the first number of frames being the number of frame periods while a data voltage with a same polarity as a polarity of a data voltage written into the pixel formation portions immediately after a point of time when the power supply of the liquid-crystal display device is turned on is held in the pixel formation portions, the second number of frames being the number of frame periods while a data voltage with a different polarity from the polarity of the data voltage written into the pixel formation portions immediately after the power supply is turned on is held in the pixel formation portions, and
the bias movement determination unit determines whether the polarity bias is in the increasing direction or the decreasing direction based on comparison between the polarity bias count value at the point of time when the OFF signal is inputted and the polarity bias count value in a frame period before the point of time when the OFF signal is inputted.
According to a fourth aspect of the present invention, in the second aspect of the invention, the bias movement determination unit determines whether or not the polarity bias is in the increasing direction or the decreasing direction in response to whether the number of times of polarity reverse of the data voltage held in the pixel formation portions from the point of time when the power supply is turned on until the point of time when the OFF signal is inputted is an odd number or an even number.
According to a fifth aspect of the present invention, in the second aspect of the invention,
before the point of time when the OFF signal is inputted, the balance control unit controls the drive unit so that the data voltage reversing the polarity of the applied voltage to the liquid crystal layer is written during a refresh period of writing the data voltage into the pixel formation portions, and
the bias movement determination unit determines whether the polarity bias is in the increasing direction or the decreasing direction in response to whether a total number of frame periods included in the refresh period from the point of time when the power supply is turned on until the point of time when the OFF signal is inputted is an odd number or an even number.
According to a sixth aspect of the present invention, in anyone of the third to fifth aspects of the invention,
the display control unit further includes a REF/NREF determination unit configured to determine, with regard to each frame period, whether the frame period is a refresh period of writing the data voltage into the plurality of pixel formation portions or a pause period of pausing the write of the data voltage into the plurality of pixel formation portions, and
the balance control unit:
controls, before the point of time when the OFF signal is inputted, the drive unit so that the refresh period of writing the data voltage into the plurality of pixel formation portions and the pause period of pausing the write of the data voltage into the plurality of pixel formation portions appears alternately based on a result of the determination by the REF/NREF determination unit, and
after the point of time when the OFF signal is inputted,
in a case where the bias movement determination unit determines that the polarity bias is in the increasing direction, controls the drive unit so that the pause period for reducing the polarity bias is inserted in response to the degree of the polarity bias at the point of time when the OFF signal is inputted after the polarity reverse refreshment is performed, and
in a case where the bias movement determination unit determines that the polarity bias is in the decreasing direction, controls the drive unit so that the pause period for reducing the polarity bias is inserted in response to the degree of the polarity bias at the point of time when the OFF signal is inputted without performing the polarity reverse refreshment.
According to a seventh aspect of the present invention, in the first aspect of the invention,
the display control unit includes:
a polarity bias calculation unit configured to obtain a polarity bias of the voltage applied to the liquid crystal layer; and
a balance control unit configured to, upon receiving the OFF signal, start a zero determination operation of continuously determining whether or not the polarity bias is substantially “0”, maintain an operation of the drive unit without turning off the power supply while it is determined that the polarity bias is not “0” in the zero determination operation, and permit OFF of the power supply when the polarity bias is “0” in the zero determination operation.
According to an eighth aspect of the present invention, in the seventh aspect of the invention,
wherein the display unit includes a plurality of pixel formation portions composed so as to hold a voltage to be applied to the liquid crystal layer, as a data voltage,
the display control unit further includes a REF/NREF determination unit configured to determine, with regard to each frame period, whether the frame period is a refresh period of writing the data voltage into the plurality of pixel formation portions or a pause period of pausing the write of the data voltage into the plurality of pixel formation portions, and
the balance control unit:
controls, before a point of time when the OFF signal is inputted, the drive unit so that the refresh period of writing the data voltage into the plurality of pixel formation portions and the pause period of pausing the write of the data voltage into the plurality of pixel formation portions appears alternately based on a result of the determination by the REF/NREF determination unit, and
after the point of time when the OFF signal is inputted, continues an operation of the drive unit, the drive unit being performed before the point of time when the Off signal is inputted, while it is determined that the polarity bias is not “0” by the zero determination operation.
According to a ninth aspect of the present invention, in the sixth or eighth aspect of the invention, the REF/NREF determination unit detects presence of an image change by comparing image data for a previous frame period and image data for a subsequent frame with each other, and determines whether the subsequent frame period is the refresh period or the pause period in response to the presence of the image change.
According to a tenth aspect of the present invention, in the sixth or eighth aspect of the invention, the REF/NREF determination unit detects presence of an image change by comparing a result of predetermined arithmetic operation processing using image data for a previous frame period and a result of the arithmetic operation processing using image data for a subsequent frame with each other, and determines whether the subsequent frame period is the refresh period or the pause period in response to the presence of the image change.
According to an eleventh aspect of the present invention, in the sixth or eighth aspect of the invention, the REF/NREF determination unit determines, with regard to each frame period, whether the frame period is the refresh period or the pause period by input information given from an outside.
According to a twelfth aspect of the present invention, in the sixth or eighth aspect of the invention, in a period while the input image data is not given from an outside, the REF/NREF determination unit determines, with regard to each frame period, whether the frame period is the refresh period or the pause period so that the refresh period appears every predetermined time.
According to a thirteenth aspect of the present invention, in the second aspect of the invention,
the liquid-crystal display device further including:
data signal lines and scanning signal lines configured to be connected to the pixel formation portions and the drive unit,
wherein each of the pixel formation portions includes:
a pixel capacitance configured to hold the data voltage; and
a switching element having a control terminal connected to the scanning signal line, a first conduction terminal connected to the data signal line, and a second conduction terminal connected to the pixel capacitance,
wherein the switching element includes a thin film transistor having a channel layer formed of an oxide semiconductor.
According to a fourteenth aspect of the present invention, in the thirteenth aspect of the invention, the oxide semiconductor contains indium, gallium, zinc and oxygen.
A fifteenth aspect of the present invention is directed to a method for driving a liquid-crystal display device that displays, on a display unit, an image represented by input image data, by applying a voltage corresponding to the input image data, to a liquid crystal layer in the display unit, the method including:
a driving step of applying the voltage to the liquid crystal layer, the voltage corresponding to the input image data; and
a polarity bias compensation step of, when an OFF signal instructing OFF of a power supply of the liquid-crystal display device is inputted, controlling voltage application to the liquid crystal layer so that a polarity bias of the voltage applied to the liquid crystal layer until a point of time when the OFF signal is inputted can be reduced from a time when the OFF signal is inputted until the power supply is turned off.
In accordance with the first aspect of the present invention, when the OFF signal instructing OFF of the power supply is inputted, the drive unit is controlled so that the polarity bias of the voltage applied to the liquid crystal layer until the point of time when the OFF signal is inputted can be reduced. In such a way, at the point of time when the power supply is turned off, the polarity bias of the applied voltage to the liquid crystal layer is reduced, whereby the charge storage owing to the uneven distribution of the impurity ions in the liquid crystal layer is resolved or suppressed. As a result, the generation of the flicker, and the like, which are thereafter caused when the power supply is turned to operate the liquid-crystal display device, can be suppressed.
In accordance with the second aspect of the present invention, at the point of time when the OFF signal instructing OFF of the power supply is inputted, in the case where it is determined that the polarity bias of the applied voltage to the liquid crystal layer is in the increasing direction, the drive unit is controlled so that the polarity bias can be reduced after the polarity reverse refreshment is performed, and meanwhile, in the case where it is determined that the polarity bias is in the decreasing direction, the drive unit is controlled so that the polarity bias can be reduced without performing the polarity reverse refreshment. In such a way, irrespective of the moving direction of the polarity bias at the time when the OFF signal is inputted, the polarity bias can be reduced (canceled) in a short time by the voltage application to the liquid crystal layer after the point of time when the OFF signal is inputted.
In accordance with the third aspect of the present invention, based on the comparison between the polarity bias count value at the point of time when the OFF signal is inputted and the polarity bias count value in the frame period before the point of time when the OFF signal is inputted, it is determined whether the polarity bias of the applied voltage to the liquid crystal layer is in the increasing direction or the decreasing direction, and the drive unit is controlled based on the result of this determination in a similar way to the second aspect of the present invention. In such a way, similar effects to those of the second aspect of the present invention are obtained.
In accordance with the fourth aspect of the present invention, it is determined whether the polarity bias of the applied voltage to the liquid crystal layer is in the increasing direction or the decreasing direction in response to whether the number of times of the polarity reverse of the data voltage held in the pixel formation portions from the point of time when the power supply is turned on until the point of time when the OFF signal instructing OFF of the power supply is inputted is an odd number or an even number. In such a way, the determination of the moving direction of the polarity bias of the applied voltage to the liquid crystal layer can be performed with ease.
In accordance with the fifth aspect of the present invention, it is determined whether the polarity bias of the applied voltage to the liquid crystal layer is in the increasing direction or the decreasing direction in response to whether the total number of the frame periods included in the refresh period from the point of time when the power supply is turned on until the point of time when the OFF signal instructing OFF of the power supply is inputted is an odd number or an even number. In such a way, in the configuration in which the data voltage, which reverses the polarity of the applied voltage to the liquid crystal layer, is written during the refresh period, the determination of the moving direction of the polarity bias of the applied voltage to the liquid crystal layer can be performed with more ease.
In accordance with the sixth aspect of the present invention, in the liquid-crystal display device in which the pause drive is performed, when the OFF signal instructing OFF of the power supply is inputted to the liquid-crystal display device, after the point of time when the OFF signal is inputted, in the case where it is determined that the polarity bias of the applied voltage to the liquid crystal layer is in the increasing direction, the pause period for reducing the polarity bias is inserted after the polarity reverse refreshment is performed, and meanwhile, in the case where it is determined that the polarity bias is in the decreasing direction, the pause period is inserted without performing the polarity reverse refreshment. In the pause drive, the period while the polarity of the applied voltage to the liquid crystal layer is maintained to be the same is long, and accordingly, such a problem as the generation of the flicker, which is caused by the bias of the polarity, is prone to occur; however, in accordance with the sixth aspect of the present invention, also in the liquid-crystal display device that performs the pause period, such a polarity bias is canceled in a short time by the above-described operation performed after the point of time when the OFF signal is inputted, and the problem such as the generation of the flicker can be suppressed.
In accordance with the seventh aspect of the present invention, when the OFF signal instructing OFF of the power supply is inputted, the zero determination operation of continuously determining whether or not the polarity bias of the applied voltage to the liquid crystal layer is substantially “0” is started, and by this zero determination operation, the polarity bias can be reduced before the power supply is turned off without determining the moving direction of the polarity bias.
In accordance with the eighth aspect of the present invention, similar effects to those of the seventh aspect of the present invention are exerted in the liquid-crystal display device in which the pause drive is performed.
In accordance with the ninth aspect of the present invention, a slight change of the image is also detected, and based on a result of this detection, it can be determined whether the subsequent frame period is set to be the refresh period or the pause period.
In accordance with the tenth aspect of the present invention, without providing a memory with a large capacity, the presence of the image change is detected, and based on a result of this detection, it can be determined whether the subsequent frame period is set to be the refresh period or the pause period.
In accordance with the eleventh aspect of the present invention, without providing a memory and the like, it can be determined with ease whether each frame period is set to be the refresh period or the pause period.
In accordance with the twelfth aspect of the present invention, the refresh period is inserted every predetermined time also during the period while the input image data is not given from the outside. In such a way, quality of the image display is maintained, and the refreshment of reversing the polarity of the applied voltage to the liquid crystal layer is performed every predetermined time, whereby the charge storage owing to the uneven distribution of the impurity ions in the liquid crystal layer is suppressed, and a deterioration of the liquid crystal can be prevented.
In accordance with the thirteenth aspect of the present invention, the thin film transistor in which the channel layer is formed of the oxide semiconductor is used as the switching element of each pixel formation portion in the active matrix-type liquid-crystal display device. In such a way, the off-leak current of the thin film transistor is reduced to a large extent, and the voltage written into the pixel capacitance of each pixel formation portion is held for a longer period. Moreover, the polarity bias of the applied voltage to the liquid crystal layer can be canceled by the control for the drive unit after the point of time when the OFF signal instructing OFF of the power supply is inputted. Hence, in the case of performing the pause drive, the power consumption for the image display can be reduced to a large extent while the generation of the flicker, and the like are suppressed.
In accordance with the fourteenth aspect of the present invention, indium gallium zinc oxide is used as the oxide semiconductor that forms the channel layer of the thin film transistor included in each pixel formation portion, whereby similar effects to those of the thirteenth aspect of the present invention can be obtained.
Effects of other aspects of the present invention are obvious from the above-described first to fourteenth aspects of the present invention and from the following description of the embodiments, and accordingly, a description thereof is omitted.
A description is made below of embodiments of the present invention while focusing a liquid-crystal display device that performs pause drive; however, the present invention is also applicable to a liquid-crystal display device that does not perform the pause drive. Moreover, in the following description of the liquid-crystal display device that performs the pause drive, a frame period for writing a voltage of a data signal, which represents an image to be displayed, as a data voltage into a pixel formation portion is referred to as a “refresh frame period”, and a frame period while the write of the data voltage is paused is referred to as a “pause frame period”. Note that it is defined that “one frame period” is a period for refreshing one screen (that is, rewriting or writing the data voltage), and that a length of the “one frame period” is a length (16.67 ms) of one frame period in a general display device in which a refresh rate is 60 Hz; however, the present invention is not limited to this.
Before making the description of the embodiments of the present invention, a description is made of a basic study made by the inventors of this application in order to solve the problem described above.
The liquid-crystal display device applies a voltage to the liquid crystal layer to control a transmittance of the liquid crystal layer, thereby displaying an image. However, if a direct current component is contained in the applied voltage to the liquid crystal layer, then charge storage owing to uneven distribution of impurity ions in the liquid crystal layer (hereinafter, the charge storage is simply referred to as a “charge bias”) occurs, and as a result, a display defect such as a flicker and an afterimage is generated. Therefore, in general, alternating current drive is performed in the liquid-crystal display device. That is to say, the liquid-crystal display device is configured so that a temporal average value (or integrated value) of the applied voltage to the liquid crystal layer can be substantially “0” in such a manner that the polarities of the applied voltage to the liquid crystal layer are reversed every predetermined period (typically, every frame period) (refer to the voltage polarities A and B shown in
However, depending on timing when the power supply of the liquid-crystal display device is turned off, the temporal average value of the applied voltage to the liquid crystal layer does not become “0”, and the charge bias occurs in some case. For example, in the liquid-crystal display device in which the reverse cycle is 1 frame, when the power supply is turned off at a point of time when an odd number of frame periods elapse after the power supply is turned on, then the temporal integrated value of the applied voltage to the liquid crystal layer does not become “0”, and an operation of the liquid-crystal display device is stopped in a state where the charge bias occurs. However, the charge bias at this time is no more than a bias caused by application of the voltage of one polarity between the positive and negative polarities during one frame period (16.67 ms), and accordingly, has not been recognized as a cause of the display defect such as the generation of the flicker.
In contrast, in the liquid-crystal display device that performs the pause drive as shown in
A problem such as the generation of the flicker is caused by the charge storage owing to the uneven distribution of the impurity ions in the liquid crystal layer, and it is conceived that the charge storage as described above occurs by the polarity bias of the applied voltage to the liquid crystal layer (hereinafter, this polarity bias is also simply referred to as “polarity bias”). The problem such as the generation of the flicker, which is caused by the charge storage owing to the uneven distribution of the impurity ions, cannot be solved even in a case of executing the conventional off-sequence for discharging the stored charge in the pixel capacitance.
A description is made below of embodiments of the present invention, which is made based on the basic study described above in order to solve the problem such as the generation of the flicker, which is caused by the polarity bias.
In the display unit 500, there are formed: a plurality of data signal lines SL; a plurality of scanning signal lines GL; and a plurality of pixel formation portions 10 arranged in a matrix so as to correspond to the plurality of data signal lines SL and the plurality of scanning signal lines GL. In
In this embodiment, as the TFT 11, for example, a TFT including a channel layer composed of an oxide semiconductor is used. More specifically, the channel layer of the TFT 11 is formed of In—Ga—Zn—O (indium gallium zinc oxide) containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O). Hereinafter, the TFT including the channel layer composed of In—Ga—Zn—O is referred to as an “In—Ga—Zn—O TFT”. An off-leak current of the In—Ga—Zn—O TFT is far small in comparison with a silicon-based TFT using amorphous silicon and the like for the channel layer. Therefore, the voltage written into the pixel capacitance Cp can be held for a longer period. Note that a similar effect is obtained even in a case of using, as the channel layer, an oxide semiconductor containing, for example, at least one of indium, gallium, zinc, copper (Cu), silicon (Si), tin (Sn), aluminum (Al), calcium (Ca), germanium (Ge) and lead (Pb) as an oxide semiconductor other than In—Ga—Zn—O. Moreover, such use of the oxide semiconductor as the channel layer of the TFT 11 is merely an example, and the silicon-based semiconductor may be used in place of this.
Typically, the display control unit 200 is realized as an IC (Integrated Circuit). The display control unit 200 receives data DAT, which includes input image data representing an image to be displayed, from the host 90, and in response to this, generates and outputs a source driver control signal Ssc, a gate driver control signal Sgc, a common voltage signal and the like. The source driver control signal Ssc is given to the source driver 310, the gate driver control signal is given to the gate driver 320, and the common voltage signal is given to the common electrode 13 in the display unit 500. Moreover, to the display control unit 200, an OFF signal Soff instructing OFF of the power supply of the liquid-crystal display device 100 is also inputted from the host 90, and this OFF signal Soff is also given to the source driver 310 and the gate driver 320 through the display control unit 200.
In response to the source driver control signal Ssc, the source driver 310 generates and outputs a data signal, which is to be given to each data signal line SL. For example, the source driver control signal Ssc includes: a digital video signal, which indicates the image to be displayed; a source start pulse signal; a source clock signal; a latch strobe signal; a polarity switch control signal; and the like. In response to the source driver control signal Ssc as described above, the source driver 310 operates a shift register, a sampling latch circuit and the like (not shown) in an inside thereof, converts a digital signal, which is obtained based on the digital video signal, into an analog signal by a DA conversion circuit (not shown), and thereby generates the above-described data signal.
In response to the gate driver control signal Sgc, the gate driver 320 repeats application of an active scanning signal to each scanning signal line GL in a predetermined cycle. For example, the gate driver control signal Sgc includes: a gate clock signal; and a gate start pulse signal. In response to the gate clock signal and the gate start pulse signal, the gate driver 320 generates a shift register and the like (not shown) in an inside thereof, and thereby generates the above-described scanning signal.
On a back surface side of the display unit 500, a backlight unit (not shown) is provided, whereby backlight light is applied onto a back surface of the display unit 500. The backlight unit may be a unit controlled by the display control unit 200, or may be a unit controlled by other methods. Note that, in a case where the liquid crystal panel is of a reflection type, it is not necessary to provide the backlight unit.
In such a manner as described above, the data signal is applied to each data signal line SL, the scanning signal is applied to each scanning signal line GL, whereby the image indicated by the input image data included in the data DAT transmitted from the host 90 is displayed on the display unit 500 in the liquid crystal panel.
As shown in
Based on the data DAT received from the host 90, the REF/NREF determination circuit 21 determines whether or not each frame period is a refresh period (REF period) or a pause period (NREF period), generates a REF/NREF signal indicating a result of the determination, and gives the generated REF/NREF signal to the polarity bias calculation circuit 23. Moreover, this REF/NREF signal is also given to the bias movement determination circuit 24 and the balance control circuit 25 through the polarity bias calculation circuit 23. With regard to such a determination as to whether each frame period is the refresh period or the pause period, for example, in a case where the image represented by the input image data included in the data DAT received from the host 90 is changed from an image to be displayed during a previous frame period, then it can be determined that such a next frame is the refresh period. Moreover, if a period while the image represented by the input image data (hereinafter, this image is referred to as an “input image”) is not changed or a period while the input image data is not received from the host 90 continues, the REF/NREF signal is generated so that the refresh frame period can be inserted every predetermined period. For example, in a case where the pause period continues for 59 frame periods, the REF/NREF signal is generated so that the next frame period can be the refresh period, that is, that the refresh period can be inserted at least once a second.
Methods for determining whether each frame period should be set to be the refresh period or the pause period are listed below. In this embodiment, any of a plurality of methods which will be described below can be used, or alternatively, a plurality of methods selected from the plurality of methods which will be described below may be used in combination with one another.
(1) Based on the input image data included in the data DAT received from the host 90, each of the frames is compared with a previous frame, and it is thereby determined whether or not the image is changed, and in response to a result of the determination, it is determined whether a next frame is the refresh period or the pause period.
(2) Predetermined arithmetic operation processing is performed for each frame by using the input image data included in the data DAT received from the host 90, a result of such an arithmetic operation for each frame is compared with a result of an arithmetic operation for the previous frame, it is determined whether the image is changed, and in response to a result of the determination, it is determined whether the next frame is the refresh period or the pause period. As the predetermined arithmetic operation, there are conceived: calculation of a sum total of pixel values in 1 frame; calculation of a checksum therein; and the like.
(3) With regard to each frame period, a dedicated signal indicating whether the frame period is the refresh period or the pause period is received from the host 90.
(4) With regard to each frame period, the host 90 writes the data, which indicates whether the frame period is the refresh period or the pause period, into a specific register provided in the display control unit 200.
(5) In a case where data of the input image is included in the data DAT received from the host 90, it is next determined that the frame period is the refresh period, and in a case where the data of the input image is not included in the data DAT, it is next determined that the frame period is the pause period.
(6) With regard to each frame period, it is determined whether the frame period is the refresh period or the pause period so that such refreshment can be performed periodically (every predetermined time) in the case where the data of the input image is not included in the data DAT received from the host 90.
With regard to cases of using the methods of (1) and (2) among the above-described methods of (1) to (6), configurations thereof will be described later.
The polarity bias calculation circuit 23 includes a register 23c for storing a value, which indicates a degree of the polarity bias at the present point of time. Hereinafter, this register is referred to as a “polarity bias counter 23c”, and a value of this polarity bias counter 23c is denoted by reference symbol “Nb”. In an initial state, the polarity bias calculation circuit 23 sets this polarity bias count value Nb at “0”, increments the value Nb by “1” (increases the value Nb by “1”) at a point of ending time of a first refresh frame period after the power supply is turned on, and thereafter, increments the value Nb by “1” every time when 1 pause frame period is ended until a next refresh frame period appears. That is to say, the polarity bias count value Nb is subjected to a counting-up operation every frame period. Note that, in this embodiment, it is assumed that there is no polarity bias at the point of time when the power supply is turned on.
In this embodiment, during the refresh frame period, (the balance control circuit 25 of) the display control unit 200 reverses the polarity of the data voltage, which is held in (the pixel capacitance Cp of) each pixel formation portion 10, without fail. Hence, the polarity bias calculation circuit 23 decrements the value Nb by “1” (decreases the value Nb by “1”) at a point of time when the next refresh frame period is ended, and thereafter, decrements the value Nb by “1” every time when one pause frame period is ended until the next refresh frame period appears. That is to say, the polarity bias count value Nb is subjected to a counting-down operation every frame period. Subsequently, every time when the refresh frame period appears, the polarity bias calculation circuit 23 performs alternate switching between the counting-up operation and the counting-down operation (hereinafter, this switching is referred to as “switching of a counting direction”) for the polarity bias count value Nb. As a result, in a case where the refreshment is performed an odd number of times from the point of time when the power supply is turned on until the present point of time, at the present point of time and after, the polarity bias count value Nb is incremented by “1” every time when one frame period is ended, and in a case where the refreshment is performed an even number of times from the point of time when the power supply is turned on until the present point of time, the polarity bias count value Nb is decremented by “1” every time when one frame period is ended.
As described above, in the polarity bias counter 23c, as the polarity bias count value Nb indicating the degree of the polarity bias of the applied voltage to the liquid crystal layer, such a difference as follows is held, the difference being between a first number of frames, which is the number of the frame periods while the data voltage with the same polarity as the polarity of the data voltage written into the pixel formation portion 10 immediately after the power supply of the liquid-crystal display device 100 is turned on is held in the pixel formation portion, and a second number of frames, which is the number of the frame periods while the data voltage with a different polarity from the polarity of the data voltage written into the pixel formation portion 10 immediately after the power supply of the liquid-crystal display device 100 is turned on is held in the pixel formation portion. This polarity bias count value Nb is outputted as a signal from the polarity bias calculation circuit 23, is given to the bias movement determination circuit 24, and is also given to the balance control circuit 25 through the bias movement determination circuit 24.
Based on the polarity bias count value Nb given from the polarity bias calculation circuit 23, the bias movement determination circuit 24 determines whether the polarity bias of the applied voltage to the liquid crystal layer is in an increasing direction or a decreasing direction, that is, determines a moving direction of the polarity bias. As a method for determining the moving direction of the polarity bias, for example, one of the following methods of (A1) and (A2) can be used, or these two methods of (A1) and (A2) may be used in combination with each other.
(A1) A polarity bias count value Nb (hereinafter, referred to as an “immediately previous refreshing polarity bias count value Nbp”) at a point of time when the immediately previous refresh frame period is started is held in advance in an immediately previous refreshing polarity bias counter 24c that is a register provided in the bias movement determination circuit 24. Then, the polarity bias count value Nb at the present point of time, which is given from the polarity bias calculation circuit 23, is compared with the immediately previous refreshing polarity bias count value Nbp, and in response to a result of the comparison, it is determined whether the polarity bias is in the increasing direction or the decreasing direction.
(A2) Such polarity bias count values Nb at points of time when a plurality of immediately previous frame periods are ended are stored in advance in the bias movement determination circuit 24, and an average value Nba of these polarity bias count values Nb is obtained. The polarity bias count value Nb at the present point of time, which is given from the polarity bias calculation circuit 23, is compared with the average value Nba, and in response to a result of the comparison, it is determined whether the polarity bias is in the increasing direction or the decreasing direction. Note that, in place of the above-described average value Nba, another value (for example, a median value), which can be regarded to represent the polarity bias count values Nb at the respective points of time when the above-described plurality of immediately previous frame periods are ended, may be used.
The following description is made on the assumption that the above-described (A1) is used as the method for determining the moving direction of the polarity bias in this embodiment. The determination result in the bias movement determination circuit 24 is given as a bias moving direction signal to the balance control circuit 25.
After the power supply is turned on, the balance control circuit 25 controls the source driver 310 and the gate driver 320 based on the data DAT received from the host 90 and on the above-described REF/NREF signal until receiving the OFF signal Soff, which instructs OFF of the power supply, from the host 90 (until the OFF signal Soff becomes active). In such a way, the display unit 500 is driven by the source driver 310 and the gate driver 320 so that the image represented by the input image data included in the data DAT can be displayed on the display unit 500. As already mentioned, the pause drive system is adopted in this embodiment. Therefore, in this drive, based on the above-described REF/NREF signal, the refreshment, which rewrites the data voltage held in each pixel formation portion 10 based on the input image data so that the polarity of the data voltage can be reversed, is performed during the refresh frame period, and the refreshment is paused by turning all of the scanning signal lines GL to a non-selected state during the pause frame period. For example, in a case where forced refreshment that is based on new input image data received from the host 90 during the pause period is not performed, the refreshment is performed every predetermined period (hereinafter, this refreshment is referred to as “periodical refreshment”), and the drive as shown in
Upon having received the OFF signal Soff, which instructs OFF of the power supply, from the host 90, the balance control circuit 25 controls the drive unit 300, which is composed of the source driver 310 and the gate driver 320, so that the above-described polarity bias count value Nb at a power supply OFF instructing point of time, which is a point of time when the OFF signal Soff is inputted, can be sequentially decreased and become “0” after the power supply OFF instructing point of time. In such a way, the balance control circuit 25 controls the application of the voltage to the liquid crystal layer. Specifically, the balance control circuit 25 executes the following (Step B1 to (Step B3).
(Step B1): First, based on the above-described bias moving direction signal, it is determined whether the polarity bias is in the increasing direction or in the decreasing direction. As a result, in a case where it is determined that the polarity bias is in the increasing direction, the drive unit 300 is controlled so that the refreshment that reverses the polarity of the data voltage held in each pixel formation portion 10 can be performed, whereby one refresh frame period is inserted. The polarity bias count value Nb received from the polarity bias calculation circuit 23 is decremented by 1, and thereafter, the processing proceeds to Step B2. Meanwhile, in a case where it is determined that the polarity bias is in the decreasing direction, the processing proceeds to Step B2 without performing the refreshment.
(Step B2): Such an operation of “controlling the drive unit 300 so that the pause frame period can be inserted sequentially, and decrementing the above-described polarity bias count value Nb by “1” every time when one pause frame period is ended” is repeated until the above-described polarity bias count value Nb can become “0”, and the processing proceeds to Step B3 when the above-described polarity bias count value Nb becomes “0”.
(Step B3): The drive unit 300 is controlled so that the “off-sequence for discharge” can be executed.
After the off-sequence for discharge in Step B3 described above is ended, the power supply of the liquid-crystal display device 100 according to this embodiment is turned off. By such OFF of the power supply, the polarity bias count value Nb in the polarity bias calculation circuit 23 is initialized to “0”, and the immediately previous refreshing polarity bias count value Nbp in the bias movement determination circuit 24 is also initialized to “0”. Note that the “off-sequence for discharge” in Step B3 described above is a sequence for discharging charges stored in the pixel capacitance Cp in each pixel formation portion 10, and a specific configuration thereof is not particularly limited; however, an off-sequence similar to the conventional off-sequence for discharge may be used.
In this first operation example, in a similar way to the example shown in
At the power supply OFF instructing point of time ta, the above-described polarity bias count value Nb is larger than the immediately previous refreshing polarity bias count value Nbp (polarity bias count value Nb at the point of time t=2). Therefore, it is determined that the polarity bias is in the increasing direction. As a result, as shown in
Thereafter, the insertion of the pause frame period is repeated, and as shown by a solid line in
The off-sequence for discharge is started at the point of time when the polarity bias is canceled as described above (that is, the point of time when the insertion of the pause frame period is discontinued) (refer to Steps B2 and B3). When this off-sequence is ended, the power supply of the liquid-crystal display device 100 is turned off.
At this power supply OFF instructing point of time tb, the above-described polarity bias count value Nb is larger than the immediately previous refreshing polarity bias count value Nbp (polarity bias count value Nb at the point of time t=1). Therefore, it is determined that the polarity bias is in the decreasing direction. As a result, if the OFF signal Soff instructing OFF of the power supply is inputted at the point of time tb, the insertion of the pause frame period is repeated with the refresh frame period being not inserted, and as shown by a solid line in
When the polarity bias is resolved as described above, the off-sequence for discharge is started (refer to Steps B2 and B3). When this off-sequence is ended, the power supply of the liquid-crystal display device 100 is turned off.
A description is made below of third to fifth operation examples in this embodiment with reference to
Here, such a starting point of time of the refresh frame period, which is immediately before this power supply OFF instructing point of time t1, is a starting point of time t1b of the frame period while the forced refreshment is performed, and a polarity bias count value Nb at this point of time t1b is held as the immediately previous refreshing polarity bias count value Nbp in the immediately previous refreshing polarity bias counter 24c in the bias movement determination circuit 24. As shown in
Thereafter, the insertion of the pause frame period is repeated, and the polarity bias count value Nb is decremented by “1” every time when one pause frame period is ended (refer to Step B2). As a result of such an operation, the insertion of the pause frame period is discontinued at the point of time when the polarity bias count value Nb becomes “0”. At this discontinuation point of time, the polarity bias at the power supply OFF instructing point of time t1 is canceled by the polarity bias generated after this point of time t1, and a temporal integrated value of the data voltage held in each pixel formation portion 10 from the point of time t=0 when the power supply is turned on until the discontinuation point of time, that is, a temporal integrated value of the applied voltage to the liquid crystal layer becomes substantially “0”.
When the polarity bias is canceled as described above, the off-sequence for discharge is thereafter started (refer to Steps B2 and B3). When this off-sequence is ended, the power supply of the liquid-crystal display device 100 is turned off.
As shown in
When the polarity bias is canceled as described above, then in a similar way to the third operation example, the power supply of the liquid-crystal display device 100 is turned off after being subjected to the off-sequence for discharge (refer to Steps B2, B3).
As shown in
When the polarity bias is canceled as described above, then in a similar way to the third and fourth operation examples, the power supply of the liquid-crystal display device 100 is turned off after being subjected to the off-sequence for discharge (refer to Steps B2, B3).
In accordance with the above-described first embodiment, when the OFF signal Soff instructing OFF of the power supply is inputted, the moving direction of the polarity bias at the point of time when the OFF signal Soff is inputted (that is, the power supply OFF instructing point of time) is determined. As a result of this determination, in the case where the polarity bias is in the increasing direction, the polarity (polarity of the data voltage held in each pixel formation portion 10) of the applied voltage to the liquid crystal layer is reversed by the insertion of the refresh frame period, and the insertion of the pause frame period is thereafter started, and in the case where the polarity bias is in the decreasing direction, the insertion of the pause frame period is started without the refresh frame period being inserted. Then, in each of the above-described cases, the polarity bias count value Nb is decremented by “1” every time when the pause frame period is inserted, and the insertion of the pause frame period is discontinued at the point of time when the polarity bias count value Nb becomes “0”. At this discontinuation point of time, the polarity bias at the power supply OFF instructing point of time is canceled by the above-described operation (control of the drive unit 300) after this power supply OFF instructing point of time, and the temporal integrated value of the applied voltage to the liquid crystal layer from the point of time t=0 when the power supply is turned on until the discontinuation point of time becomes substantially “0”.
In such a manner as described above, the polarity bias of the applied voltage to the liquid crystal layer is resolved, whereby the charge storage owing to the uneven distribution of the impurity ions in the liquid crystal layer is resolved. Moreover, the off-sequence for discharge is executed after the discontinuation point of time (point of time when the polarity bias count value Nb becomes “0”) of the insertion of the pause frame period, and the power supply is thereafter turned off. Therefore, the stored charge in the pixel capacitance Cp of each pixel formation portion 10 is also discharged. Hence, at the point of time when the power supply is turned off, either of the stored charge owing to the uneven distribution of the impurity ions and the stored charge in the pixel capacitance is not present. Therefore, also in the liquid-crystal display device that performs the pause drive for the purpose of largely reducing the power consumption, and so on as in this embodiment, a problem such as the generation of the flicker does not occur when the power supply is thereafter turned on to turn the liquid-crystal display device to the operation state.
Note that, in the above-described configuration, the insertion of the pause frame period is discontinued at the point of time when the polarity bias count value Nb becomes “0”; however, at a point of time when the above-described polarity bias count value Nb becomes a value sufficiently approximate to “0” (that is, a value in which the already-mentioned charge bias is ignorable), it may be determined that the above-described polarity bias count value Nb is substantially “0”, and the insertion of the pause frame period may be discontinued. Moreover, in place of the configuration in which the pause frame period is inserted until the polarity bias count value Nb becomes “0”, the insertion of the pause frame period may be discontinued at a point of time when the polarity bias count value Nb becomes such a value approximate to “0”, which corresponds to substantial resolution of the polarity bias of the applied voltage to the liquid crystal layer from a viewpoint that the polarity bias just needs to be substantially resolved. Furthermore, from a viewpoint that the polarity bias of the applied voltage to the liquid crystal layer just needs to be capable of being decreased so as to contribute to the solution of the problem such as the generation of the flicker, the insertion of the pause frame period may be discontinued at a point of time when the polarity bias count value Nb becomes such a value approximate to “0”, which corresponds to such reduction of the polarity bias of the applied voltage to the liquid crystal layer.
In the above-described first embodiment, the drive unit 300 is controlled so that the polarity (polarity of the applied voltage to the liquid crystal layer) of the data voltage held in each pixel formation portion 10 can be reversed every time when the refresh frame period is inserted. However, such a configuration is also conceivable, in which the drive unit 300 is controlled so that a refresh frame period while the polarity of the data voltage held in each pixel formation portion 10 is not reversed can be included. In this case, in place of the configuration of switching the counting direction of the polarity bias count value Nb every time when the refresh frame period appears, the polarity bias calculation circuit 23 just needs to have a configuration of switching the counting direction of the polarity bias count value Nb only when there appears the refresh frame period while the polarity of the data voltage held in each pixel formation portion 10 is reversed. If such a configuration is adopted, in a similar way to the above-described first embodiment, the polarity bias of the applied voltage to the liquid crystal layer is resolved by the above-described control for the drive unit 300 after the power supply OFF instructing point of time, and accordingly, similar effects to those of the above-described first embodiment are obtained.
Note that, in the above-described first embodiment, the In—Ga—Zn—O TFT is used as the switching element in each pixel formation portion 10, and accordingly, the off-leak current is extremely small. However, in a case of using a silicon-based TFT other than the In—Ga—Zn—O TFT as the switching element, an off-leak current of the switching element is large, and accordingly, it is also possible to omit the above-described off-sequence for discharge.
In the above-described first embodiment, by the bias movement determination circuit 24, the moving direction of the polarity bias is determined at the power supply OFF instructing point of time based on the comparison between the polarity bias count value Nb and the immediately previous refreshing polarity bias count value Nbp. However, if this embodiment is premised on such a configuration, in which the polarity of the data voltage held in each pixel formation portion is reversed without fail when the refreshment is performed irrespective of whether the refreshment is the periodical refreshment or the forced refreshment, the moving direction of the polarity bias can be determined based on whether the number of times of the refreshment performed until the power supply OFF instructing point of time is an odd number or an even number. An embodiment in which attention is paid to this point is described below as a second embodiment of the present invention.
As shown in
Based on the data DAT received from the host 90, the REF/NREF determination circuit 21 determines whether each frame period is a refresh period or a pause period, generates a REF/NREF signal indicating a result of the determination, and gives the generated REF/NREF signal to the RFE odd number/even number determination circuit 22 and the polarity bias calculation circuit 23. Moreover, this REF/NREF signal is also given to the balance control circuit 25 through the polarity bias calculation circuit 23. This REF/NREF determination circuit 21 can be realized by a similar configuration to that of the REF/NREF determination circuit 21 in the first embodiment, and accordingly, a detailed description thereof is omitted.
Based on the above-described REF/NREF signal, the RFE odd number/even number determination circuit 22 determines whether the number of times of the refreshment from the point of time when the power supply is turned on until the present point of time (that is, the number of the refresh frame periods included in the period) is an odd number or an even number, generates an odd number/even number signal indicating a result of the determination, and gives this to the balance control circuit 25. For the purpose of determining whether such a refreshment number of times as described above is an odd number or an even number, an odd number/even number bit register 22b that is a 1-bit register is included in the RFE odd number/even number determination circuit 22. An odd number/even number bit value Bo/e that is a value of this odd number/even number bit register 22b is initialized to “0” at the point of time when the power supply is turned on, is changed to “1” at the starting point of time of the first refresh frame period immediately after such initialization, and subsequently, is alternately changed to “1” and “0” every time when the refresh frame period appears. This odd number/even number bit value Bo/e is outputted as a signal from the RFE odd number/even number determination circuit 22, and is given to the balance control circuit 25. In this embodiment, this odd number/even number bit value Bo/e indicates the moving direction of the polarity bias, and accordingly, it can be said that a polarity bias movement determination unit is realized by the REF odd number/even number determination circuit 22.
The polarity bias calculation circuit 23 includes a polarity bias counter 23c as a register for storing a value indicating a degree of the polarity bias at the present point of time, and is realized by a similar configuration to that of the polarity bias calculation circuit 23 in the first embodiment. A polarity bias count value Nb set in this immediately previous refreshing polarity bias counter 24c is outputted as a signal from the polarity bias calculation circuit 23, and is given to the balance control circuit 25.
After the power supply is turned on, the balance control circuit 25 operates in a similar way to the balance control circuit 25 in the first embodiment until receiving the OFF signal Soff, which instructs OFF of the power supply, from the host 90. That is to say, the balance control circuit 25 controls the drive unit 300 so that the pause drive as shown in
Upon receiving the OFF signal Soff instructing OFF of the power supply from the host 90, the balance control circuit 25 controls the drive unit 300 so that the above-described polarity bias count value Nb at the power supply OFF instructing point of time can be sequentially decreased after that point of time and can become “0”. Specifically, except for the following point, the balance control circuit 25 operates in a similar way to the balance control circuit 25 in the first embodiment (refer to (Step B1) to (Step B3), which are already mentioned).
The balance control circuit 25 in this embodiment determines whether the polarity bias is in the increasing direction or the decreasing direction based on the above-described odd number/even number bit value Bo/e, and is different from the balance control circuit 25 in the first embodiment in this point.
Also by this embodiment configured as described above, the drive unit 300 is controlled in a similar way to the first embodiment after the power supply OFF instructing point of time, the polarity bias at the power supply OFF instructing point of time is canceled by the control of the drive unit 300 after the power supply OFF instructing point of time, and the temporal integrated value of the applied voltage to the liquid crystal layer becomes substantially “0”. Hence, also by this embodiment, similar effects to those of the first embodiment are obtained.
Note that, in the above-described configuration, the insertion of the pause frame period is discontinued at the point of time when the polarity bias count value Nb becomes “0”; however, at the point of time when the above-described polarity bias count value Nb becomes a value sufficiently approximate to “0” (that is, a value in which the already-mentioned charge bias is ignorable), it may be determined that the above-described polarity bias count value Nb is substantially “0”, and the insertion of the pause frame period may be discontinued. Moreover, in place of the configuration in which the pause frame period is inserted until the polarity bias count value Nb becomes “0”, the insertion of the pause frame period may be discontinued at the point of time when the polarity bias count value Nb becomes such a value approximate to “0”, which corresponds to substantial resolution of the polarity bias of the applied voltage to the liquid crystal layer from a viewpoint that the polarity bias just needs to be substantially resolved. Furthermore, from a viewpoint that the polarity bias of the applied voltage to the liquid crystal layer just needs to be capable of being decreased so as to contribute to the solution of the problem such as the generation of the flicker, the insertion of the pause frame period may be discontinued at a point of time when the polarity bias count value Nb becomes such a value approximate to “0”, which corresponds to such reduction of the polarity bias of the applied voltage to the liquid crystal layer.
Next, a description is made of variants of the second embodiment with reference to
In the above-described configuration example, the image data of the preceding frame is stored in the memory 26 of the display control unit 200; however, in place of this, a result of a predetermined arithmetic operation for the image data of the preceding frame may be stored in the memory 26. In this case, the REF/NREF determination circuit 21 compares a result of the predetermined arithmetic operation for the image data of the subsequent frame with the result of the predetermined arithmetic operation for the preceding frame, which is stored in the memory 26, with each other. As a result, if both results of the predetermined arithmetic operations coincide with each other, the subsequent frame period is determined to be the pause period, and if both results of the predetermined arithmetic operations do not coincide with each other, the subsequent frame period is determined to be the refresh period. A determination result obtained as described above is outputted as the REF/NREF signal. Other configurations in the display control unit 200 and configurations other than the display control unit 200 are similar to those of the second embodiment shown in
In the above-described first and second embodiments, the moving direction of the polarity bias at the power supply OFF instructing point of time is determined, and based on the result of this determination, in the case where the polarity bias is in the increasing direction, the polarity of the data voltage in each pixel formation portion 10 is reversed (hence, the polarity of the applied voltage to the liquid crystal layer is reversed) by the insertion of the refresh frame period. In such a way, the polarity bias at the power supply OFF instructing point of time can be resolved (canceled) in a short time (refer to
As shown in
Based on the data DAT received from the host 90, the REF/NREF determination circuit 21 determines whether each frame period is the refresh period or the pause period, generates a REF/NREF signal indicating a result of the determination, and gives the generated REF/NREF signal to the polarity bias calculation circuit 23. Moreover, this REF/NREF is also given to the balance control circuit 25 through the polarity bias calculation circuit 23. This REF/NREF determination circuit 21 can be realized by a similar configuration to that of the REF/NREF determination circuit 21 in the first embodiment, and accordingly, a detailed description thereof is omitted.
Also in this embodiment, the REF/NREF determination circuit 21 and the polarity bias calculation circuit 23 operate in a similar way to the first embodiment; however, the polarity bias count value Nb obtained in the polarity bias calculation circuit 23 is given to the balance control circuit 25.
Before the point of time when the OFF signal Soff instructing OFF of the power supply is inputted (that is, the power supply OFF instructing point of time), this balance control circuit 25 operates in a similar way to the balance control circuit 25 in the first embodiment; however, after the power supply OFF instructing point of time, operates in a different manner from that of the balance control circuit 25 in the first embodiment.
That is to say, upon receiving the OFF signal Soff instructing OFF of the power supply, the balance control circuit 25 in this embodiment starts an operation of “determining whether or not the polarity bias count value Nb is “0” every time of receiving the polarity bias count value Nb from the polarity bias calculation circuit 23 (hereinafter, this operation is referred to as a “zero determination operation”)”. In this zero determination operation, during a period while it is determined that the polarity bias count value Nb from the polarity bias calculation circuit 23 is not “0”, the balance control circuit 25 controls the drive unit 300 in a similar way to the case before the power supply OFF instructing point of time based on the data DAT coming from the host 90. Meanwhile, in this zero determination operation, when it is determined that the polarity bias count value Nb coming from the polarity bias calculation circuit 23 is “0”, the balance control circuit 25 stops the control for the drive unit 300, which is based on the data DAT from the host 90, and executes an off-sequence similar to the off-sequence for discharge, which is used in the first embodiment and the like. When this off-sequence is ended, the power supply of the liquid-crystal display device 100 is turned off. Note that, in the above-described zero determination operation, it is determined whether or not the above-described polarity bias count value Nb is “0”; however, at the point of time when the above-described polarity count value Nb becomes a value sufficiently approximate to “0” (that is, a value in which the already-mentioned charge bias is ignorable), it may be determined that the above-described polarity bias count value Nb is substantially “0”, and the off-sequence for discharge may be started.
As shown in
In this first operation example, the polarity bias count value Nb coming from the polarity bias calculation circuit 23 is linearly decreased as shown by a solid line in
When the polarity bias is resolved as described above, the off-sequence for discharge is started. When this off-sequence is ended, the power supply of the liquid-crystal display device 100 is turned off.
As shown in
In this second operation example, the polarity bias count value Nb coming from the polarity bias calculation circuit 23 is linearly increased as shown by a solid line in
When the polarity bias is resolved as described above, the off-sequence for discharge is started. When this off-sequence is ended, the power supply of the liquid-crystal display device 100 is turned off.
The above-described first and second operation examples are premised on the pause drive that does not include the forced refreshment. However, even in the pause drive including the forced refreshment, there comes the point of time when the polarity bias count value Nb coming from the polarity bias calculation circuit 23 becomes “0” in the above-described zero determination operation started after the power supply OFF instructing point of time. Hence, this embodiment may have a configuration of performing the pause drive including the forced refreshment.
As described above, in this embodiment, when the OFF signal Soff instructing OFF of the power supply is inputted, the above-described zero determination operation is started, and based on the zero determination operation, the operation of the drive unit 300 is maintained with the power supply being not turned off until the polarity bias is resolved (while the polarity bias count value Nb is not “0”, and when the polarity bias is resolved (when the polarity bias count value Nb becomes “0”), OFF of the power supply is permitted. Hence, in accordance with this embodiment, in a similar way to the first and second embodiments, also in the liquid-crystal display device that performs the pause drive for the purpose of reducing the power consumption, and so on, a problem such as the generation of the flicker does not occur when the power supply is thereafter turned on to turn the liquid-crystal display device to the operation state. Moreover, in accordance with this embodiment, the configuration for determining the moving direction of the polarity bias is not required, and accordingly, the problem can be resolved by a simpler configuration than in the first and second embodiments.
Note that, in place of the configuration of permitting OFF of the power supply (starting the off-sequence for discharge) at the point of time when the polarity bias count value Nb becomes “0”, OFF of the power supply may be permitted at the point of time when the polarity bias count value Nb becomes such a value approximate to “0”, which corresponds to substantial resolution of the polarity bias of the applied voltage to the liquid crystal layer from a viewpoint that the polarity bias just needs to be substantially resolved. Furthermore, from a viewpoint that the polarity bias of the applied voltage to the liquid crystal layer just needs to be capable of being decreased so as to contribute to the solution of the problem such as the generation of the flicker, OFF of the power supply may be permitted at a point of time when the polarity bias count value Nb becomes such a value approximate to “0”, which corresponds to such reduction of the applied voltage to the liquid crystal layer.
The embodiments and the variants thereof in the present invention, which are described above, are premised on that the pause drive is performed; however, the present invention is not limited to this, and is also applicable to a liquid-crystal display device that performs usual drive in which the pause period does not appear. Even in such a liquid-crystal display device according to a usual drive method, the present invention is particularly effective in such a case of writing the data voltage into the pixel formation portions for a plurality of the frame periods without reversing the voltage. Moreover, in the embodiments and the variants thereof in the present invention, which are described above, the polarity bias count value Nb is used, whereby the degree of the polarity bias of the applied voltage to the liquid crystal layer is expressed by using one frame period as a unit; however, the unit indicating the degree of the polarity bias may be changed to another one. For example, the degree of the polarity bias may be expressed by a time measured by a timer, and in this case, a balance of the polarity of the applied voltage to the liquid crystal layer is managed by the timer. Furthermore, in the embodiments and the variants thereof in the present invention, which are described above, all of the display control unit 200 is realized by hardware; however, a part or all of the configurations in the display control unit 200 may be realized by software.
The present invention is utilized for the liquid-crystal display devices using the TFT, which has the channel layer composed of the oxide semiconductor, as the switching element of the pixel formation portion, and among them, is utilized particularly for the liquid-crystal display device that performs the pause drive.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012-288969 | Dec 2012 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2013/084219 | 12/20/2013 | WO | 00 |
