Patent Application
20240404486
This application claims the benefit of priority to Japanese Patent Application Number 2023-089886 filed on May 31, 2023. The entire contents of the above-identified application are hereby incorporated by reference.
The following disclosure relates to a liquid crystal display device capable of switching an operation mode between a normal mode and a low power consumption mode, and a method of driving the same.
Liquid crystal display devices are used in various electronic devices such as television receivers, in-vehicle displays such as car navigation devices, notebook computers, and portable terminals such as smartphones and tablet terminals. For such liquid crystal display devices, there has been an increasing demand for lower power consumption. General liquid crystal display devices of the related art are driven at a drive frequency (frame frequency) of 60 Hz. However, the higher the drive frequency becomes, the larger the power consumption becomes, and thus techniques for reducing a drive frequency are actively being developed in order to reduce power consumption. As such a technique, there is known a technique referred to as “pause driving” in which a pause period during which a writing operation of a video signal to a liquid crystal capacitance is stopped is provided. In a liquid crystal display device adopting pause driving, writing of a video signal is performed only in one frame period among a plurality of continuous frame periods, and writing of the video signal is not performed in the remaining periods.
In the liquid crystal display device adopting pause driving, for example, an operation mode is switched between a normal mode in which a drive frequency is set to 60 Hz and a low frequency mode in which a drive frequency is set to 1 Hz. In this regard, for example, switching from the normal mode to the low frequency mode is performed when there is no change in a display image throughout a predetermined period, and switching from the low frequency mode to the normal mode is performed when a user performs some operation or when data is transmitted from the outside. A thin film transistor in which a channel layer is formed of an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) as main components (hereinafter referred to as an “IGZO-TFT”) has an extremely small off-state current, and thus, in a liquid crystal display device adopting pause driving, an IGZO-TFT is typically used as a pixel transistor.
In relation to the disclosure, JP 2002-182619 A discloses that power consumption is reduced by stopping AC driving of a common electrode (counter electrode) and bringing a source driver into a high impedance state in a pause period (a period during which update of a display image is paused).
In a liquid crystal display device using an IGZO-TFT, power consumption is reduced as compared with a liquid crystal display device of the related art by adopting the above-described pause driving. For example, in a liquid crystal display device used in a notebook computer, a portable terminal, or the like, pause driving is widely adopted. Incidentally, in recent years, there has been an increasing demand for reflective or slightly transmissive large-sized liquid crystal display devices for signage applications, and such large-sized liquid crystal display devices require an external power source even when the above-described pause driving is adopted. For this reason, an installation location is limited. Consequently, a further reduction in power consumption is required such that power consumption can be covered by, for example, a solar cell. Furthermore, even when a reduction in power consumption is achieved, it is not preferable that display quality be degraded as compared with the related art.
According to the technique disclosed in JP 2002-182619 A, a current flowing through an amplifier in the source driver becomes small. However, for example, in a level shifter IC that outputs a gate control signal for controlling the operation of a power source IC or a gate driver (scanning signal line drive circuit), power is consumed even in a pause period. Thus, it is not possible to expect the effect of significantly reducing power consumption as compared with the related art.
Consequently, an object of the following disclosure is to realize a liquid crystal display device capable of significantly reducing power consumption as compared with the related art without degrading display quality.
(1) A liquid crystal display device according to some embodiments of the disclosure is a liquid crystal display device capable of switching an operation mode between a normal mode and a low power consumption mode, the liquid crystal display device including:
(2) The liquid crystal display device according to some embodiments of the disclosure includes the configuration of (1), in which, during the pause period, the plurality of video signal lines are maintained in a high impedance state, and a power source of the video signal line drive circuit is maintained in an OFF state.
(3) The liquid crystal display device according to some embodiments of the disclosure includes the configuration of (2), in which the power source circuit further generates a second power source voltage to be supplied to the video signal line drive circuit, and the power source circuit pauses generation of the second power source voltage during the pause period.
(4) The liquid crystal display device according to some embodiments of the disclosure includes the configuration of (1), in which the scanning signal line drive circuit is monolithically formed on a substrate, and a potential of a scanning control signal for controlling an operation of the scanning signal line drive circuit is maintained at 0 V during the pause period.
(5) The liquid crystal display device according to some embodiments of the disclosure includes, in addition to the configuration of (4), a level shifter circuit configured to generate the scanning control signal, in which a power source of the level shifter circuit is maintained in an OFF state during the pause period.
(6) The liquid crystal display device according to some embodiments of the disclosure includes the configuration of (5), in which the power source circuit further generates a third power source voltage to be supplied to the level shifter circuit, and the power source circuit pauses generation of the third power source voltage during the pause period.
(7) The liquid crystal display device according to some embodiments of the disclosure includes the configuration of (1), in which the scanning signal line drive circuit is provided in a form of an integrated circuit chip, and a potential of a scanning control signal for controlling an operation of the scanning signal line drive circuit is maintained at 0 V during the pause period.
(8) The liquid crystal display device according to some embodiments of the disclosure includes, in addition to the configuration of (7), a timing control circuit configured to generate the scanning control signal, in which a power source of the timing control circuit is maintained in an OFF state during the pause period.
(9) The liquid crystal display device according to some embodiments of the disclosure includes the configuration of (7), in which the power source circuit further generates a third power source voltage to be supplied to the scanning signal line drive circuit, and the power source circuit pauses generation of the third power source voltage during the pause period.
(10) The liquid crystal display device according to some embodiments of the disclosure includes the configuration of (1), in which, during the first transition period, the power source circuit changes the potential of the first power source voltage from the potential of the first level to the potential of the second level, and then the scanning signal line drive circuit changes the potentials of the plurality of scanning signal lines from the potential of the predetermined off level to 0 V.
(11) The liquid crystal display device according to some embodiments of the disclosure includes the configuration of (1), in which, during the second transition period, the scanning signal line drive circuit changes the potentials of the plurality of scanning signal lines from 0 V to the potential of the predetermined off level, and then the power source circuit changes the potential of the first power source voltage from the potential of the second level to the potential of the first level.
(12) The liquid crystal display device according to some embodiments of the disclosure includes the configuration of (1), in which the pixel transistor is a thin film transistor in which a channel layer is formed of an oxide semiconductor, the oxide semiconductor being indium gallium zinc oxide containing indium (In), gallium (Ga), zinc (Zn), and oxygen (0) as main components.
(13) The liquid crystal display device according to some embodiments of the disclosure includes the configuration of (1), in which the pixel transistor is a thin film transistor having a dual-gate structure in which two transistors are connected in series.
(14) The liquid crystal display device according to some embodiments of the disclosure includes the configuration (1), in which the pixel transistor is a thin film transistor having a double-gate structure including a top gate and a back gate as the control terminal.
(15) The liquid crystal display device according to some embodiments of the disclosure includes any one of the configurations of (1) to (14), in which a variation range of the potential of the first power source voltage from the potential of the first level to the potential of the second level in the first transition period is equal to a variation range of the potentials of the plurality of scanning signal lines from the potential of the predetermined off level to 0 V in the first transition period.
(16) A driving method according to some embodiments of the disclosure is a method of driving a liquid crystal display device capable of switching an operation mode between a normal mode and a low power consumption mode,
In the liquid crystal display device according to some embodiments of the disclosure, in a period during which an operation mode is set to be a low power consumption mode, it is not necessary to supply a video signal to a video signal line drive circuit, and it is also not necessary to supply a power source voltage to a scanning signal line drive circuit and a video signal line drive circuit. Thus, in a period during which an operation mode is set to be a low power consumption mode, both an AC component and a DC component of power consumption are greatly reduced as compared with a period during which an operation mode is set to be a normal mode. As described above, power consumption is greatly reduced as compared with the related art. A power source circuit changes the potential of a first power source voltage so that a leakage current flowing through a pixel transistor is not generated during a pause period of a period during which an operation mode is set to be a low power consumption mode. Thus, even when a drive frequency is lowered, display quality is not degraded as compared with the related art. As described above, it is possible to realize a liquid crystal display device capable of significantly reducing power consumption as compared with the related art without degrading display quality.
The disclosure will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
Before describing embodiments, terms used in the present specification will be described. In a liquid crystal display device according to each of the following embodiments, the above-described pause driving is performed. In this regard, for convenience of description, pause driving of the related art is referred to as “pause driving of the related art”, and pause driving in each of the following embodiments is referred to as “ultra-low power pause driving”. In a liquid crystal display device adopting pause driving, an operation mode is switched between a normal mode and a low frequency mode as described above, and a low frequency mode in pause driving of the related art is referred to as a “low frequency mode of the related art” and a low frequency mode in ultra-low power pause driving is referred to as an “SP mode” (Super Pause Mode). A period during which a video signal is written to a liquid crystal capacitance (including a preparation period for writing) is referred to as a “rewrite period”, and a period during which a video signal is not written to the liquid crystal capacitance is referred to as a “pause period”.
Embodiments will be described below with reference to the accompanying drawings.
The system substrate 5 is provided with a power source IC (power source circuit) 51 that generates various power source voltages, a TCON 52 which is an IC generating a timing signal and the like for controlling the timing in an operation of displaying an image in the display portion 20, and a level shifter IC 53 for changing a voltage level (potential) of a timing signal generated by the TCON 52. In the present embodiment, a display control unit 10 to be described later is realized by the TCON 52 and the level shifter IC 53.
The display portion 20 is provided with pixel forming portions 200 for forming pixels so as to correspond to intersections between the plurality of gate bus lines GL and the plurality of source bus lines SL (see
Next, an operation outline of the liquid crystal display devices according to the present embodiment will be described with reference to a functional block diagram illustrated in
The display control unit 10 receives an image signal DA transmitted from a host, and outputs a digital video signal DV, a gate control signal (scanning control signal) GCTL for controlling the operation of the gate driver 30, and a source control signal SCTL for controlling the operation of the source driver 40. That is, the display control unit 10 controls the operation of the gate driver 30 and the operation of the source driver 40. The gate control signal GCTL includes a gate start pulse signal, a clear signal, and a gate clock signal, and the source control signal SCTL includes a source start pulse signal, a source clock signal, a latch strobe signal, and a polarity control signal.
The gate driver 30 repeats application of an active scanning signal to each of the gate bus lines GL in one vertical scanning period as a cycle, based on the gate control signal GCTL transmitted from the display control unit 10. However, in the pause period, the gate driver 30 pauses the operation of applying the scanning signal to the gate bus lines GL.
The source driver 40 applies a driving video signal to each of the plurality of source bus lines SL, based on the digital video signal DV and the source control signal SCTL transmitted from the display control unit 100. However, in the pause period, the source driver 40 pauses the operation of applying the driving video signal to the source bus lines SL.
As described above, the scanning signal is applied to the gate bus lines GL, and the driving video signal is applied to the source bus lines SL, whereby an image based on the image signal DA transmitted from the host is displayed in the display portion 20.
Incidentally, in the liquid crystal display device according to the present embodiment, ultra-low power pause driving is performed in which an operation mode is switched between a normal mode in which a display image is updated in each frame period at a drive frequency of 60 Hz and an SP mode in which a display image is updated only once in a plurality of frame periods at a drive frequency of 0.01 Hz. A period during which an operation mode is maintained in a normal mode is referred to as a “normal mode period”, a period during which an operation mode is set to be an SP mode is referred to as an “SP mode period”, a period during which the operation mode transitions from the normal mode to the SP mode is referred to as a “first transition period”, and a period during which the operation mode transitions from the SP mode to the normal mode is referred to as a “second transition period”. The SP mode period includes a pause period significantly longer than a pause period in the low frequency mode of the related art and a rewrite period.
The power source IC 51 includes a VGH generation unit 511, a VGL generation unit 512, a VDD generation unit 513, a VDDIO generation unit 514, an AVDD generation unit 515, a GMA generation unit 516, and a VCOM generation unit 517. The VGH generation unit 511 generates a gate high power source voltage VGH which is a high-level side power source voltage for operating the gate driver 30. The VGL generation unit 512 generates a gate low power source voltage VGL which is a low-level side power source voltage for operating the gate driver 30. The gate high power source voltage VGH and the gate low power source voltage VGL are supplied to the level shifter IC 53. The VDD generation unit 513 generates a logic power source voltage VDD used in a logic circuit in the TCON 52. The VDDIO generation unit 514 generates an input/output power source voltage VDDIO used in an input/output circuit 521 in the TCON 52. The logic power source voltage VDD and the input/output power source voltage VDDIO are supplied to the TCON 52. The AVDD generation unit 515 generates a source power source voltage AVDD which is a power source voltage for operating the source driver 40. The GMA generation unit 516 generates a gamma power source voltage GMA used to generate a gray-scale voltage in the source driver 40. The source power source voltage AVDD and the gamma power source voltage GMA are supplied to the source driver 40. The VCOM generation unit 517 generates a common electrode drive voltage VCOM. The common electrode drive voltage VCOM is applied to the common electrode 29.
In the present embodiment, a first power source voltage is realized by the common electrode drive voltage VCOM, a second power source voltage is realized by the source power source voltage AVDD and the gamma power source voltage GMA, and a third power source voltage is realized by the gate high power source voltage VGH and the gate low power source voltage VGL.
The TCON 52 includes the input/output circuit 521, a RAM 522, an oscillator 523, a timing control unit 524, and a source output interface (I/F) 525. The input/output circuit 521 receives the image signal DA transmitted from the host and writes the image signal DA to the RAM 522. The input/output circuit 521 also applies the image signal DA extracted from the RAM 522 at an appropriate timing to the timing control unit 524. The RAM 522 temporarily holds the image signal DA transmitted from the host. The oscillator 523 generates a basic clock for operating the timing control unit 524. The timing control unit 524 generates various control signals for controlling the operations of the gate driver 30 and the source driver 40 based on the image signal DA applied from the input/output circuit 521 and the basic clock generated by the oscillator 523. The source output I/F 525 outputs the image signal DA and the above-described source control signal SCTL.
The level shifter IC 53 converts voltage levels (potentials) of various control signals transmitted from the timing control unit 524 into the potential of the gate high power source voltage VGH or the gate low power source voltage VGL to output the gate control signal GCTL, a gate high-level side power source voltage GVDD, and a gate low-level side power source voltage GVSS. The gate control signal GCTL, the gate high-level side power source voltage GVDD, and the gate low-level side power source voltage GVSS are applied to the gate driver 30.
Next, the gate driver 30 in the present embodiment will be described below. Here, it is assumed that i gate bus lines GL1 to GLi and j source bus lines SL1 to SLj are arranged in the display portion 20.
As the gate control signals GCTL, a gate start pulse signal GSP, a clear signal GCLR, and gate clock signals GCK1 and GCK2 are applied to the shift register 300. The gate clock signals GCK1 and GCK2 are two-phase clock signals, and the phases of the gate clock signals GCK1 and GCK2 are shifted by 180 degrees. As power source voltages for operation, the gate high-level side power source voltage GVDD and the gate low-level side power source voltage GVSS are applied to the shift register 300.
Each unit circuit 3 includes an input terminal that receives the gate clock signal GCK1 or the gate clock signal GCK2 as an input clock signal CKA, an input terminal that receives the clear signal GCLR, an input terminal that receives a set signal S, an input terminal that receives a reset signal R, an input terminal that receives the gate high-level side power source voltage GVDD, an input terminal that receives a gate low-level side power source voltage GVSS, and an output terminal that outputs an output signal Q.
Signals applied to input terminals of the respective stages (respective unit circuits 3) of the shift register 300 are as follows. The gate clock signal GCK1 is applied as the input clock signal CKA to the unit circuits 3 in the odd-numbered stages, and the gate clock signal GCK2 is applied as the input clock signal CKA to the unit circuits 3 in the even-numbered stages. Regarding a unit circuit 3(k) at an arbitrary stage (k-th stage in this case), an output signal Q(k−1) output from a unit circuit 3(k−1) at a stage one stage before the arbitrary stage is applied as the set signal S, and an output signal Q(k+1) output from a unit circuit 3(k+1) at a stage one stage after the arbitrary stage is applied as the reset signal R. The gate start pulse signal GSP is applied as the set signal S to the unit circuit 3(1) at the first stage, and the clear signal GCLR is applied as the reset signal R to the unit circuit 3(i) at the i-th stage. The gate high-level side power source voltage GVDD, the gate low-level side power source voltage GVSS, and the clear signal GCLR are applied in common to all of the unit circuits 3(1) to 3(i).
The output signal Q is output from an output terminal (of each of the unit circuits 3) at each of the stages of the shift register 300. The output signal Q output from the arbitrary stage (k-th stage in this case) is applied to a gate bus line GLk in a k-th row as a scanning signal and is also applied to a unit circuit 3(k−1) at a stage one stage before the arbitrary stage as the reset signal R, and is applied to a unit circuit 3(k+1) at a stage one stage after the arbitrary stage as the set signal S.
In the above-described configuration, when a pulse of the gate start pulse signal GSP as the set signal S is applied to the unit circuit 3(1) at the first stage of the shift register 300, a shift pulse included in the output signal Q output from each unit circuit 3 is sequentially transferred from the unit circuit 3(1) at the first stage to the unit circuit 3(i) at the i-th stage based on the clock operations of the gate clock signals GCK1 and GCK2. Then, in response to the transfer of the shift pulses, the output signals Q output from the unit circuits 3 are sequentially set to be at a high level. Thereby, i scanning signals applied to i gate bus lines GL1 to GLi arranged in the display portion 20 are sequentially set to be at a high level (active). That is, i gate bus lines GL1 to GLi are sequentially set to be in a selected state.
Next, a connection relationship between the components in the unit circuit 3 will be described. Hereinafter, a gate terminal will be referred to as a “control terminal”, one of two terminals functioning as a drain terminal and a source terminal will be referred to as a “first conduction terminal”, and the other will be referred to as a “second conduction terminal”. A second conduction terminal of the thin film transistor M1b, a first conduction terminal of the thin film transistor M2a, a first conduction terminal of the thin film transistor M3a, a first conduction terminal of the thin film transistor M4a, a control terminal of the thin film transistor M10, one end of the capacitor Cbst, and the stabilization circuit 301 are connected to each other via a first node N1. A control terminal of the thin film transistor M4a, a control terminal of the thin film transistor M4b, a control terminal of the thin film transistor M9, and the stabilization circuit 301 are connected to each other via a second node N2.
Regarding the thin film transistor M1a, a control terminal is connected to the input terminal 31, a first conduction terminal is connected to the input terminal 35, and a second conduction terminal is connected to a first conduction terminal of the thin film transistor M1b. Regarding the thin film transistor M1b, a control terminal is connected to the input terminal 31, a first conduction terminal is connected to a second conduction terminal of the thin film transistor M1a, and a second conduction terminal is connected to the first node N1. Regarding the thin film transistor M2a, a control terminal is connected to the input terminal 34, a first conduction terminal is connected to the first node N1, and a second conduction terminal is connected to a first conduction terminal of the thin film transistor M2b. Regarding the thin film transistor M2b, a control terminal is connected to the input terminal 34, a first conduction terminal is connected to a second conduction terminal of the thin film transistor M2a, and a second conduction terminal is connected to the input terminal 36. Regarding the thin film transistor M3a, a control terminal is connected to the input terminal 32, a first conduction terminal is connected to the first node N1, and a second conduction terminal is connected to a first conduction terminal of the thin film transistor M3b. Regarding the thin film transistor M3b, a control terminal is connected to the input terminal 32, a first conduction terminal is connected to a second conduction terminal of the thin film transistor M3a, and a second conduction terminal is connected to the input terminal 36. Regarding the thin film transistor M4a, a control terminal is connected to the second node N2, a first conduction terminal is connected to the first node N1, and a second conduction terminal is connected to a first conduction terminal of the thin film transistor M4b. Regarding the thin film transistor M4b, a control terminal is connected to the second node N2, a first conduction terminal is connected to a second conduction terminal of the thin film transistor M4a, and a second conduction terminal is connected to the input terminal 36. Regarding the thin film transistor M9, a control terminal is connected to the second node N2, a first conduction terminal is connected to the output terminal 39, and a second conduction terminal is connected to the input terminal 36. Regarding the thin film transistor M10, a control terminal is connected to the first node N1, a first conduction terminal is connected to the input terminal 33, and a second conduction terminal is connected to the output terminal 39. Regarding the thin film transistor M11, a control terminal is connected to the input terminal 34, a first conduction terminal is connected to the output terminal 39, and a second conduction terminal is connected to the input terminal 36. Regarding the capacitor Cbst, one end is connected to the first node N1, and the other end is connected to the output terminal 39.
Next, the operation of the unit circuit 3(n) at the n-th stage in a period during which an operation mode is maintained in a normal mode will be described with reference to a signal waveform diagram illustrated in
At time t00, the set signal S changes from a low level to a high level. Thereby, the thin film transistors M1a, M1b, and M7 are set to be in an ON state. When the thin film transistors M1a and M1b are set to be in an ON state, the potential of the first node N1 rises, and the thin film transistors M6 and M10 are set to be in an ON state. When the thin film transistors M6 and M7 are set to be in an ON state, the potential of the second node N2 changes from a high level to a low level. Since the input clock signal CKA is at a low level in a period from time t00 to time t02, the output signal Q(n) is maintained at a low level even when the thin film transistor M10 is set to be in an ON state. At time t01, the set signal S changes from a high level to a low level. Thereby, the thin film transistors M1a, M1b, and M7 are set to be in an OFF state.
At time t02, the input clock signal CKA changes from a low level to a high level. At this time, the thin film transistor M10 is in an ON state, and thus the potential of the output terminal 39 rises along with a rise in the potential of the input terminal 33. Here, since the capacitor Cbst is provided between the first node N1 and the output terminal 39 as illustrated in
At time t03, the input clock signal CKA changes from a high level to a low level. Thereby, the potential of the output terminal 39 is lowered along with a decrease in the potential of the input terminal 33. That is, the potential of the output signal Q(n) changes from a high level to a low level. The potential of the first node N1 is lowered via the capacitor Cbst.
At time t04, the reset signal R changes from a low level to a high level. Thereby, the thin film transistors M3a and M3b are set to be in an ON state, and the potential of the first node N1 is set to be at a low level. When the potential of the first node N1 is set to be at a low level, the thin film transistors M6 and M10 are set to be in an OFF state. At this time, since the thin film transistors M5a, M5b, and M5c are in an ON state, the potential of the second node N2 changes from a low level to a high level when the thin film transistor M6 is set to be in an OFF state. At time t05, the reset signal R changes from a high level to a low level. Thereby, the thin film transistors M3a and M3b are set to be in an OFF state.
At time t06, the potential of the gate high-level side power source voltage GVDD is lowered. Thereby, the thin film transistors M5a, M5b, and M5c are set to be in an OFF state. Thereafter, at time t07, the clear signal GCLR changes from a low level to a high level. Thereby, the thin film transistors M2a, M2b, M8, and M11 are set to be in an ON state. When the thin film transistors M2a and M2b are set to be in an ON state, the potential of the first node N1 is brought into a completely low level. When the thin film transistor M8 is set to be in an ON state, the potential of the second node N2 changes from a high level to a low level. When the thin film transistor M11 is set to be in an ON state, the potential of the output signal Q(n) is brought into a completely low level.
At time t08, the clear signal GCLR changes from a high level to a low level. Thereby, the thin film transistors M2a, M2b, M8, and M11 are set to be in an OFF state. Thereafter, at time t09, the potential of the gate high-level side power source voltage GVDD rises. Thereby, the thin film transistors M5a, M5b, and M5c are set to be in an ON state, and the potential of the second node N2 changes from a low level to a high level.
Incidentally, the thin film transistors M4a, M4b, and M9 are in an ON state in a period during which the potential of the second node N2 is maintained at a high level. For this reason, the potential of the first node N1 and the potential of the output signal Q(n) (the potential of the output terminal 39) are reliably maintained at a low level. Thus, the operation of the gate driver 30 is stabilized.
When the above-described operations are performed in each unit circuit 3, i gate bus lines GL(1) to GL(i) provided in the liquid crystal display device are sequentially set to be in a select state, and video signals are sequentially written to the liquid crystal capacitance 23. Thereby, an image based on the image signal DA transmitted from the outside is displayed in the display portion 20.
A source start pulse signal SSP and a source clock signal SCK are input to the shift register circuit 410. The shift register circuit 410 sequentially transfers pulses included in the source start pulse signal SSP from an input end to an output end based on the source clock signal SCK. Sampling pulses SMP corresponding to the source bus lines SL are sequentially output from the shift register circuit 410 in response to the transfer of the pulses, and the sampling pulses SMP are sequentially input to the sampling circuit 420.
The sampling circuit 420 samples a digital video signal DV at the timing of the sampling pulse SMP output from the shift register circuit 410 and outputs the digital video signal DV as an internal image signal d. The latch circuit 430 takes in the internal image signal d output from the sampling circuit 420 at the timing of the pulse of the latch strobe signal LS and outputs the internal image signal d.
The gray-scale voltage generation circuit 460 generates 256 positive gray-scale voltages GV(H0) to GV(H255) and 256 negative gray-scale voltages GV(L0) to GV(L255) from the gamma power source voltage GMA supplied from the power source IC 51, and supplies the gray-scale voltages to the DA conversion circuit 440.
The DA conversion circuit 440 is constituted by a plurality of DA converters corresponding one-to-one to the plurality of source bus lines SL connected to the source output circuit 450. The 256 gray-scale voltages GV(H0) to GV(H255) for a positive polarity and the 256 gray-scale voltages GV(L0) to GV(L255) for a negative polarity are supplied to the DA conversion circuit 440 from the gray-scale voltage generation circuit 460. Each of the DA converter selects one of the gray-scale voltages GV based on a polarity control signal POL and the internal image signal d output from the latch circuit 430, and outputs the selected gray-scale voltage GV.
The source output circuit 450 performs impedance conversion on the gray-scale voltage GV output from each of the DA converters constituting the DA conversion circuit 440, and outputs the converted gray-scale voltage GV to each of the source bus lines SL as a driving video signal.
A method of driving the liquid crystal display device according to the present embodiment will be described. With respect to potentials (voltage levels) of various signals and the like, values shown below are merely examples, and the disclosure is not limited thereto.
When the pulse of the gate start pulse signal GSP is generated at time t10 and then the gate clock signal GCK1 changes from a low level to a high level at time t11, the gate bus line GL1 in the first row is set to be in a select state, and a driving video signal is applied to the pixel electrodes 22 included in the pixel forming portions 200 in the first row. Thereby, the pixel potential Vpix1 of the pixel forming portion 200 in the first row and the first column changes from 0 V to 10 V, and the pixel potential Vpix2 of the pixel forming portion 200 in the first row and the second column changes, for example, from 10 V to 0 V. In this manner, in the pixel forming portions 200 in the odd-numbered columns of the first row, a driving video signal is written to the liquid crystal capacitance 23 so that a liquid crystal application voltage has a positive polarity, and in the pixel forming portions 200 in the even-numbered columns of the first row, a driving video signal is written to the liquid crystal capacitance 23 so that a liquid crystal application voltage has a negative polarity.
When the gate clock signal GCK2 changes from a low level to a high level at time t12, the gate bus line GL2 in the second row is set to be in a select state, and a driving video signal is applied to the pixel electrodes 22 included in the pixel forming portions 200 in the second row. Thereby, the driving video signal is written to the liquid crystal capacitances 23 in the pixel forming portions 200 in the second row.
When the writing of the driving video signal to the liquid crystal capacitances 23 in the pixel forming portions 200 in the i-th row is completed at time t13, and then time t14 arrives, the potential of the gate high-level side power source voltage GVDD changes from 21 V to −7 V. When time t15 arrives in a state where the potential of the gate high-level side power source voltage GVDD is set to −7 V, the clear signal GCLR changes from a low level to a high level. Thereby, in all of the unit circuits 3 (see
At time t16, the clear signal GCLR changes from a high level to a low level. Then, at time t17, the potential of the gate high-level side power source voltage GVDD changes from −7 V to 21 V.
When an operation mode is maintained in a normal mode, the above-described operation is repeated, and a display image is updated in each frame period.
Next, the operation of the liquid crystal display device when an operation mode transitions will be described. A first transition step is realized by an operation in a first transition period, and a second transition step is realized by an operation in a second transition period.
1.5.2.1 Transition from Normal Mode to SP Mode
At time t21, all of the source bus lines SL1 to SLj are discharged. Thereby, the potentials of all of the source bus lines SL1 to SLj are set to 0 V. In
At time t22, the VCOM generation unit 517 changes the potential of the common electrode drive voltage VCOM from 5 V to 12 V. At this time, in each pixel forming portion 200, the pixel transistor 21 is maintained in an OFF state. For this reason, when the potential of the common electrode drive voltage VCOM rises from 5 V to 12 V, a pixel potential also rises in each pixel forming portion 200. For example, the pixel potential Vpix1 rises from 10 V to 17 V, and the pixel potential Vpix2 rises from 0 V to 7 V. Since a liquid crystal application voltage does not change, a display image does not change.
At time t23, the generation of the gate high power source voltage VGH, the gate low power source voltage VGL, the source power source voltage AVDD, the gamma power source voltage GMA, and the input/output power source voltage VDDIO is stopped in the power source IC 51. Thereby, the potential of the gate high power source voltage VGH, the potential of the gate low power source voltage VGL, the potential of the source power source voltage AVDD, the potential of the gamma power source voltage GMA, and the potential of the input/output power source voltage VDDIO are set to 0 V. The potential of the logic power source voltage VDD is maintained at 3.3 V. When the potential of the gate high power source voltage VGH and the potential of the gate low power source voltage VGL are set to 0 V, the power source of the level shifter IC 53 that generates the gate control signal GCTL is set to be in an OFF state. As a result, the potential of the gate start pulse signal GSP, the potential of the gate clock signal GCK1, the potential of the gate clock signal GCK2, the potential of the gate high-level side power source voltage GVDD, the potential of the gate low-level side power source voltage GVSS, and the potential of the clear signal GCLR are set to 0 V. In this manner, in a pause period of an SP mode period, the potential of the gate control signal GCTL for controlling the operation of the gate driver 30 is maintained at 0 V.
Incidentally, when the generation of the gate high power source voltage VGH and the gate low power source voltage VGL is stopped at time t23, the potential of the gate start pulse signal GSP, the potential of the gate clock signal GCK1, the potential of the gate clock signal GCK2, the potential of the gate high-level side power source voltage GVDD, the potential of the gate low-level side power source voltage GVSS, and the potential of the clear signal GCLR rise from −7 V to 0 V. Accordingly, the potential of each gate bus line GL also rises from −7 V to 0 V (the gate driver 30 changes the potential of each gate bus line GL from −7 V to 0 V). That is, the potential of each gate bus line GL rises by 7 V. In consideration of this, the VCOM generation unit 517 increases the potential of the common electrode drive voltage VCOM by 7 V at time t22 so that a leakage current flowing through the pixel transistor 21 is not generated during the pause period of the SP mode period. In this manner, in the present embodiment, a variation range of the potential of the common electrode drive voltage VCOM in the first transition period is equal to a variation range of the potential of i gate bus lines GL1 to GLi in the first transition period.
As described above, the normal mode period transitions to the SP mode period. As described above, a display image does not change in the first transition period, and thus the display image at the end point of the normal mode period immediately before the first transition period remains displayed as is also in the SP mode period.
As described above, all of the source bus lines SL1 to SLj are set to be in a high impedance state at time t21, and the generation of the source power source voltage AVDD and the gamma power source voltage GMA is stopped at time t23. In this manner, in the pause period of the SP mode period, all of the source bus lines SL1 to SLj are maintained in a high impedance state, and the power source of the source driver 40 is maintained in an OFF state.
As described above, the VCOM generation unit 517 changes the potential of the common electrode drive voltage VCOM from 5 V to 12 V at time t22. In this regard, 5 V is equivalent to a potential of a first level, and 12 V is equivalent to a potential of a second level. At time t23, the gate driver 30 changes the potential of each gate bus line GL from −7 V to 0 V. In this regard, −7 V is equivalent to a potential of a predetermined off level.
1.5.2.2 Transition from SP Mode to Normal Mode
At time t31, the VCOM generation unit 517 changes the potential of the common electrode drive voltage VCOM from 12 V to 5 V. At this time, in each pixel forming portion 200, the pixel transistor 21 is maintained in an OFF state. For this reason, when the potential of the common electrode drive voltage VCOM is lowered from 12 V to 5 V, a pixel potential is also lowered in each pixel forming portion 200. For example, the pixel potential Vpix1 is lowered from 17 V to 10 V, and the pixel potential Vpix2 is lowered from 7 V to 0 V. Since a liquid crystal application voltage does not change, a display image does not change.
At time t32, the clear signal GCLR changes from a low level to a high level. Thereby, in all of the unit circuits 3 (see
At time t33, the potential of the gate high-level side power source voltage GVDD output from the level shifter IC 53 changes from −7 V to 21 V under the control of the timing control unit 524. The source bus lines SL are electrically connected to the source driver 40, and the potentials of the source bus lines SL become equal to a potential (for example, an intermediate potential between the maximum potential and the minimum potential) immediately before the start time (time t21 in
As described above, the SP mode period transitions to the normal mode period. After the pulse of the gate start pulse signal GSP is generated, a driving video signal is written to the liquid crystal capacitances 23 included in the pixel forming portions 200 of each row based on the clock operations of the gate clock signals GCK1 and GCK2. That is, the display image is updated.
According to the present embodiment, an operation mode of the liquid crystal display device can be switched between a normal mode in which a drive frequency is set to 60 Hz and an SP mode in which a drive frequency is set to 0.01 Hz. Here, with respect to the components provided in the source driver 40 and the system substrate 5, a difference between a state in a normal mode period and a state in a pause period of an SP mode period will be described with reference to
Incidentally, in a liquid crystal display device adopting pause driving of the related art, each component in the power source IC 51 is not set to be in a pause state but set to be in a standby state so that an operation mode is rapidly switched to the normal mode in response to an action from the outside during the pause period. That is, as illustrated in
As described above,
An example of the state of power consumption in the low frequency mode of the related art is shown in a part A of
P=((P1·F1·NW)+(P2·F2))/TF (1)
Here, P1 is power in a rewrite period, F1 is the length of the rewrite period (the number of frames), NW is the number of times a display image is updated, P2 is power in a pause period, F2 is the length of the pause period (the number of frames), and TF is a total number of frames.
As a drive frequency becomes lower, a ratio of F2 to the sum of F1 and F2 becomes higher in the above Equation (1). That is, as a drive frequency becomes lower, the average power consumption P approaches the power in the pause period. From
According to the present embodiment, in a first transition period for switching an operation mode from a normal mode to an SP mode, the VCOM generation unit 517 changes the potential of the common electrode drive voltage VCOM from 5 V to 12 V before changing the potential of each gate bus line GL from −7 V to 0 V by pausing the generation of the gate high power source voltage VGH and the gate low power source voltage VGL. Thereby, it is possible to prevent a leakage current from flowing through the pixel transistor 21 due to a rise in a pixel potential in each pixel forming portion 200 and the potential of each gate bus line GL being maintained at 0 V during the SP mode period. For this reason, even when ultra-low power pause driving is performed in which an operation mode is switched between the normal mode in which a drive frequency is set to 60 Hz and the SP mode in which a drive frequency is set to 0.01 Hz, display quality is not degraded as compared with the related art.
As described above, according to the present embodiment, it is possible to realize a liquid crystal display device capable of significantly reducing power consumption as compared with the related art without degrading display quality. Thus, for example, a large liquid crystal display device for signage can be used even in a place where an external power source is not provided.
A second embodiment will be described below. Descriptions of the same points as in the first embodiment will be omitted.
As in the first embodiment, the power source IC 51 includes a VGH generation unit 511, a VGL generation unit 512, a VDD generation unit 513, a VDDIO generation unit 514, an AVDD generation unit 515, a GMA generation unit 516, and a VCOM generation unit 517. The TCON 52 includes a gate output interface (I/F) 526 in addition to the same components as those in the first embodiment. The gate output I/F 526 outputs a gate control signal GCTL (a gate start pulse signal and a gate clock signal).
In the present embodiment, since the level shifter IC 53 is not provided as described above, a gate high power source voltage VGH generated by the VGH generation unit 511 and a gate low power source voltage VGL generated by the VGL generation unit 512 are supplied to the gate driver 30 as power source voltages for operating the gate driver 30.
Also in the present embodiment, a first power source voltage is realized by a common electrode drive voltage VCOM, a second power source voltage is realized by a source power source voltage AVDD and a gamma power source voltage GMA, and a third power source voltage is realized by a gate high power source voltage VGH and a gate low power source voltage VGL.
A method of driving the liquid crystal display device according to the present embodiment will be described.
When the pulse of a gate start pulse signal GSP is generated at time t40 and then a gate clock signal GCK1 changes from a low level to a high level at time t41, a gate bus line GL1 in a first row is set to be in a select state, and a driving video signal is applied to pixel electrodes 22 included in pixel forming portions 200 in a first row. Thereby, similarly to time t11 (see
When an operation mode is maintained in a normal mode, the above-described operation is repeated, and a display image is updated in each frame period.
2.3.2.1 Transition from Normal Mode to SP Mode
At time t51, all of the source bus lines SL1 to SLj are discharged. Thereby, the potentials of all of the source bus lines SL1 to SLj are set to 0 V. Then, all of the source bus lines SL1 to SLj are set to be in a high impedance state. Since the potential of the common electrode drive voltage VCOM is maintained at 5 V in a period from time t51 to time t52, the pixel potential Vpix1 is maintained at 10 V and the pixel potential Vpix2 is maintained at 0 V.
At time t52, the VCOM generation unit 517 changes the potential of the common electrode drive voltage VCOM from 5 V to 12 V. At this time, in each pixel forming portion 200, the pixel transistor 21 is maintained in an OFF state. For this reason, when the potential of the common electrode drive voltage VCOM rises from 5 V to 12 V, a pixel potential also rises in each pixel forming portion 200. For example, the pixel potential Vpix1 rises from 10 V to 17 V, and the pixel potential Vpix2 rises from 0 V to 7 V. Since a liquid crystal application voltage does not change, a display image does not change.
At time t53, the generation of the gate high power source voltage VGH, the gate low power source voltage VGL, the source power source voltage AVDD, the gamma power source voltage GMA, and the input/output power source voltage VDDIO is stopped in the power source IC 51. Thereby, the potential of the gate high power source voltage VGH, the potential of the gate low power source voltage VGL, the potential of the source power source voltage AVDD, the potential of the gamma power source voltage GMA, and the potential of the input/output power source voltage VDDIO are set to 0 V. The potential of the logic power source voltage VDD is maintained at 3.3 V. When the potential of the gate high power source voltage VGH and the potential of the gate low power source voltage VGL are set to 0 V, the potential of each gate bus line GL is also set to 0 V.
Incidentally, at time t53, the potential of each gate bus line GL rises from −7 V to 0 V (the gate driver 30 changes the potential of each gate bus line GL from −7 V to 0 V). That is, the potential of each gate bus line GL rises by 7 V. In consideration of this, the VCOM generation unit 517 increases the potential of the common electrode drive voltage VCOM by 7 V at time t52 so that a leakage current flowing through the pixel transistor 21 is not generated during the pause period of the SP mode period. In this manner, also in the present embodiment, a variation range of the potential of the common electrode drive voltage VCOM in the first transition period is equal to a variation range of the potential of i gate bus lines GL1 to GLi in the first transition period.
After time t51, the potential of the gate start pulse signal GSP and the potential of the gate clock signal GCK are maintained at 0 V. That is, in a pause period of an SP mode period, the potential of the gate control signal GCTL for controlling the operation of the gate driver 30 is maintained at 0 V. In the pause period of the SP mode period, the power source of the timing control unit 524 (see
As described above, the normal mode period transitions to the SP mode period. Similarly to the first embodiment, a display image does not change in the first transition period also in the present embodiment, and thus the display image at the end point of the normal mode period immediately before the first transition period remains displayed as is also in the SP mode period.
2.3.2.2 Transition from SP Mode to Normal Mode
At time t61, the VCOM generation unit 517 changes the potential of the common electrode drive voltage VCOM from 12 V to 5 V. At this time, in each pixel forming portion 200, the pixel transistor 21 is maintained in an OFF state. For this reason, when the potential of the common electrode drive voltage VCOM is lowered from 12 V to 5 V, a pixel potential is also lowered in each pixel forming portion 200. For example, the pixel potential Vpix1 is lowered from 17 V to 10 V, and the pixel potential Vpix2 is lowered from 7 V to 0 V. Since a liquid crystal application voltage does not change, a display image does not change.
At time t62, the source bus lines SL are electrically connected to the source driver 40, and the potentials of the source bus lines SL become equal to a potential (for example, an intermediate potential between the maximum potential and the minimum potential) immediately before the start time (time t51 in
With respect to the gate driver 30, the source driver 40, and the components provided on the system substrate 5, a difference between a state in a normal mode period and a state in a pause period of an SP mode period will be described with reference to
In the embodiments described above, an IGZO-TFT having a general configuration including a gate terminal, a source terminal, and a drain terminal is adopted as the pixel transistor 21. However, the disclosure is not limited thereto. Consequently, a modification example of the pixel transistor 21 will be described below.
Incidentally, it is necessary to maintain a display image in an SP mode period. Although a gate-source voltage of the pixel transistor 21 is set to 0 V in the SP mode period, it is necessary to prevent a leakage current from flowing through the pixel transistor 21 in order to maintain a display image. In this respect, an off-leak current is significantly small in the thin film transistor having the dual gate structure. For this reason, it is possible to effectively maintain the display image in the SP mode period by adopting the thin film transistor having the dual gate structure as the pixel transistor 21 as in the present modification example. A drive frequency in the SP mode can be set to a lower frequency.
The thin film transistor having the double-gate structure has a higher resistance to deterioration due to light reception and a significantly smaller off-leak current than a general thin film transistor. For this reason, it is possible to effectively maintain a display image in an SP mode period by adopting the thin film transistor having the double-gate structure as the pixel transistor 21 as in the present modification example. A drive frequency in the SP mode can be set to a lower frequency.
Although the disclosure has been described in detail above, the above description is exemplary in all respects and is not limited thereto. It is understood that numerous other modifications or variations can be made without departing from the scope of the disclosure.
While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-089886 | May 2023 | JP | national |
