Patent Application
20150035740
The present invention relates to a liquid crystal display device, a driving device for a liquid crystal display panel and the liquid crystal display panel, and particularly to an active matrix liquid crystal display device, a driving device for a liquid crystal display panel and the liquid crystal display panel.
An active matrix liquid crystal display device is configured to sandwich liquid crystal between a common electrode and multiple pixel electrodes. Then, an active element such as a TFT (Thin Film Transistor) is provided for each pixel electrode, and use of the active element enables control of whether the voltage of source wiring should be set for the pixel electrode.
The common electrode is set to a predetermined potential, and each pixel electrode is set to a potential corresponding to each pixel value of an image to be displayed. Here, a state where the potential of the pixel electrode is higher than the potential of the common electrode is referred to as positive polarity. On the other hand, a state where the potential of the pixel electrode is lower than the potential of the common electrode is referred to as negative polarity.
In an active matrix liquid crystal display device, it is preferred to drive pixels in such a manner that few pixels having the same polarity will be disposed side by side in succession to prevent crosstalk.
As shown in
For example, in the typical liquid crystal display device shown in
Further, the source driver 60 changes the potentials of the source lines to reverse the polarity of each pixel each time the frame is switched. In other words, upon selection of gate lines in an odd-numbered row in the next frame that follows the above-mentioned frame, the source driver 60 sets the potentials of source lines in the odd-numbered columns lower than VCOM, and sets the potentials of source lines in the even-numbered columns higher than VCOM. On the other hand, upon selection of gate lines in an even-numbered row, the source driver 60 sets the potentials of source lines in the odd-numbered columns higher than VCOM, and sets the potentials of source lines in the even-numbered columns lower than VCOM. As a result, the polarity of each pixel becomes opposite to the polarity of each pixel shown in
In this driving method, each time the selected row is switched to another, the potential of each source line is changed from a potential higher than VCOM to a potential lower than VCOM, or from the potential lower than VCOM to the potential higher than VCOM. This increases power requirements. Particularly, since the power consumption of a liquid crystal display panel is proportional to the square of a difference between the potentials of the source line upon switching between selected rows, the power consumption increases as the number of times of switching the potential of the source line increases.
There is proposed a liquid crystal display device capable of controlling adjacent pixels to have different polarities while reducing power consumption (see Paragraph Nos. 0008 to 0018 and FIGS. 1 to 6 in Japanese Patent Application Publication (JP-P2009-181100A)). In the liquid crystal display device described in JP-P2009-181100A, TFTs connected to gate lines in an odd-numbered row are formed on the left side of source lines, and TFTs connected to gate lines in an even-numbered row are formed on the right side of source lines. This structure can prevent a change in the potential of each source line from a potential higher than VCOM to a potential lower than VCOM, or from a potential lower than VCOM to a potential higher than VCOM during each selection period.
The liquid crystal display device described in JP-P2009-181100A also includes a distribution transistor for switching the source lines to be connected to the TFTs to switch the output of a driver circuit among multiple source lines within one row selection period. For example, one of output terminals of the driver circuit is switched sequentially to the leftmost source line, the third source line from the left, the fifth source line from the left and so on within one row selection period. Similarly, another output terminal is switched sequentially to the second source line from the left, the fourth source line from the left, the sixth source line from the left, and so on within the selection period.
Further, a liquid crystal display device configured to switch between sampling timings of sampling and latching serially input image data per horizontal scanning period is described on the first page of Japanese Patent Application Publication (JP-P2006-71891A) and the like.
In the liquid crystal display device described in JP-P2009-181100A, one of the output terminals of the driver circuit is switched sequentially to the leftmost source line, the third source line from the left, the fifth source line from the left and so on within one row selection period. Similarly, another output terminal is also switched sequentially to the second source line from the left, the fourth source line from the left, the sixth source line from the left and so on within the selection period. Therefore, input data for respective pixels have to be output while changing the order of input of the data.
For example, suppose that data on respective pixels are input as shown in
In the liquid crystal display device described in JP-P2009-181100A, one of the output terminals of the driver circuit first outputs R1+ within the selection period of the first row, and the output terminal is connected to the leftmost source line at this time. Next, the output terminal outputs B1+ within the selection period, and is connected to the third source line from the left. Further, the output terminal outputs G2+ within the selection period, and is connected to the fifth source line from the left. Thus, this output terminal outputs data within one selection period as shown in
Further, since each output terminal has to set the potentials of multiple pixel electrodes within one selection period, there is a possibility that a medium- or large-sized liquid crystal display panel with a large number of pixels may not be able to set a potential necessary for each pixel electrode.
It is a general object of the present invention to provide a liquid crystal display device capable of driving pixels in such a manner to reduce the number of pixels having the same polarity and appearing consecutively while reducing power consumption without the need to change the order of output of potentials corresponding to image data from the order of input of image data, and a driving device for a liquid crystal display panel employed in the liquid crystal display device and the liquid crystal display panel.
According to an exemplary aspect of the invention, a liquid crystal display device includes; an active matrix liquid crystal display panel; and a driving device (e.g., driving device 1) for driving the liquid crystal display panel, wherein the liquid crystal display panel includes: a common electrode; a plurality of pixel electrodes arranged in a matrix; and source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side (e.g., left side) among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side (e.g., right side) opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, and the driving device includes: potential output means (e.g., potential setting section 11) having a plurality of potential output terminals from each of which a potential corresponding to an input pixel value is output, and configured to output a potential from each potential output terminal in such a manner to output a potential higher than a common electrode potential and a potential lower than the common electrode potential alternately in order of arrangement of the potential output terminals; and switch means (e.g., switch section 12) having a plurality of input terminals and switch output terminals that is one more in number than the plurality of input terminals, wherein if the k-th input terminal from the left is denoted as Ik, the k-th and k+l-th switch output terminals from the left are denoted as Ok and Ok+1, respectively, the number of input terminals is denoted as n, and k takes each value from 1 to n, the switch means connects the input terminal Ik to either of the switch output terminals Ok and Ok+1, wherein each source line of the liquid crystal display panel is connected to a corresponding switch output terminal of the switch means, the potential output means switches between output of a potential higher than the common electrode potential and output of a potential lower than the common electrode potential at each potential output terminal depending on a period for selecting each row in the odd-numbered group one by one or a period for selecting each row in the even-numbered group one by one, the switch means switches between the switch output terminals to be connected to each input terminal depending on the period for selecting each row in the odd-numbered group one by one or the period for selecting each row in the even-numbered group one by one, and the potential output means continues to output, from each potential output terminal, a potential specific to a pixel value corresponding to the potential output terminal, respectively, during a selection period of one row.
For example, the liquid crystal display device may also include control means (e.g., control section 3 or 3a) for outputting a first control signal (e.g., POL1) to control whether the potential of each potential output terminal of the potential output means is set higher or lower than the common electrode potential, and a second control signal (e.g., POL2) to give an instruction to determine to which of the switch output terminals Ok and Ok+1 the input terminal Ik is to be connected, wherein depending on whether the first control signal is at high level or low level, the potential output means switches between whether a potential higher than the common electrode potential is output from an odd-numbered potential output terminal from the left and a potential lower than the common electrode potential is output from an even-numbered potential output terminal from the left, and whether a potential lower than the common electrode potential is output from the odd-numbered potential output terminal from the left and a potential higher than the common electrode potential is output from the even-numbered potential output terminal from the left, the switch means switches between the switch output terminals Ok and Ok+1 to which the input terminal Ik is to be connected, depending on whether the second control signal is at high level or low level, and the control means switches the levels of the first control signal and the second control signal between the period for selecting each row in the odd-numbered group one by one and the period for selecting each row in the even-numbered group one by one.
Further, for example, the control means may be configured to switch, on a frame-by-frame basis, between a mode of outputting the control signals, in which when the first control signal is set to high level, the second control signal is also set to high level, while when the first control signal is set to low level, the second control signal is also set to low level, and a mode of outputting the control signals, in which when the first control signal is set to low level, the second control signal is set to high level, while when the first control signal is set to high level, the second control signal is set to low level.
Further, for example, upon switching between selection periods, the control means may be configured to put output from a potential output terminal of the potential output means into a high impedance state, and switch the level of the second control signal while the output of the potential output terminal is in the high impedance state.
Further, for example, the liquid crystal display device may include control means for outputting a first control signal to control whether the potential of each potential output terminal of the potential output means is set higher or lower than the common electrode potential and notifying the potential output means of the start of a frame, wherein the potential output means outputs a second control signal to give an instruction to determine to which of the switch output terminals Ok and Ok+1 the input terminal Ik is to be connected, and depending on whether the first control signal is at high level or low level, the potential output means switches between whether a potential higher than the common electrode potential is output from an odd-numbered potential output terminal from the left and a potential lower than the common electrode potential is output from an even-numbered potential output terminal from the left, and whether a potential lower than the common electrode potential is output from the odd-numbered potential output terminal from the left and a potential higher than the common electrode potential is output from the even-numbered potential output terminal from the left, the switch means switches between the switch output terminals Ok and Ok+1 to which the input terminal Ik is to be connected, depending on whether the second control signal is at high level or low level, the control means switches the level of the first control signal between the period for selecting each row in the odd-numbered group one by one and the period for selecting each row in the even-numbered group one by one, and when notified of the start of a frame, the potential output means controls the second control signal to connect the input terminal Ik to the switch output terminal Ok, and after that, switches the level of the second control signal between the period for selecting each row in the odd-numbered group one by one and the period for selecting each row in the even-numbered group one by one.
Further, for example, the control means may be configured to switch, on a frame-by-frame basis, between a mode of outputting the control signals, in which when the second control signal becomes high level, the first control signal is set to high level, while when the second control signal becomes low level, the first control signal is set to low level, and a mode of outputting the control signals, in which when the second control signal becomes high level, the first control signal is set to low level, while when the second control signal becomes low level, the first control signal is set to high level.
Further, for example, the control means may be such that upon switching between selection periods, the control means puts output from a potential output terminal of the potential output means into a high impedance state, and the potential output means switches the level of the second control signal while the output from the potential output terminal is in the high impedance state.
Further, for example, the liquid crystal display device may be such that every row of pixel electrodes is set as one group in such a manner that a pixel electrode in an odd-numbered row is connected to a source line on a predetermined side among source lines existing on both sides of the pixel electrode, and a pixel electrode in an even-numbered row is connected to a source line on the side opposite to the predetermined side among the source lines existing on both sides of the pixel electrode.
Further, for example, the liquid crystal display device may be such that two or more driving devices are provided, switch means of respective driving devices are placed side by side, and among adjacent two switch means, the rightmost switch output terminal of the left-hand switch means and the leftmost switch output terminal of the right-hand switch means are connected to a common source line (e.g., source line Sn+1 illustrated in
Further, for example, the potential output means may be configured to set the output potential of each potential output terminal to a potential between the maximum potential and the minimum potential output from the potential output terminal during a vertical blanking interval.
For example, the potential output means may be configured to short-circuit between a pair of adjacent two potential output terminals during a vertical blanking interval.
Further, for example, the liquid crystal panel may be configured to arrange R, G and B pixels in the same sequence on a row-by-row basis.
Further, for example, the liquid crystal panel may be configured to arrange R, G and B pixels in different sequences among a predetermined number of consecutive rows and repeat the R, G and B arrangement pattern in the predetermined number of consecutive rows.
Further, for example, the liquid crystal panel may be configured to arrange only one kind of pixels among R, G and B in each row. Further, for example, the liquid crystal panel may have a sequence of RGBW pixels, rather than RGB pixels.
According another exemplary aspect of the invention, a liquid crystal display device includes: an active matrix liquid crystal display panel; and a driving device for driving the liquid crystal display panel, wherein the liquid crystal display panel includes: a common electrode; a plurality of pixel electrodes arranged in a matrix; and source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, and the driving device includes: a DA converter for inputting each data corresponding to each of pixel values for one row, converting the input data to an analog voltage, and outputting a potential after subjected to conversion, wherein depending on whether a first control signal (e.g., POL1) input to the DA converter is at high level or low level, the DA converter switches between whether a potential higher than a common electrode potential is output from an odd-numbered potential output terminal from the left and a potential lower than the common electrode potential is output from an even-numbered potential output terminal from the left, and whether a potential lower than the common electrode potential is output from the odd-numbered potential output terminal from the left and a potential higher than the common electrode potential is output from the even-numbered potential output terminal from the left; and switch means for switching between whether the potential of a pixel electrode is set using the source line on the left side of the pixel electrode and whether the potential of the pixel electrode is set using the source line on the right side of the pixel electrode, wherein if the number of pixel columns to be driven is denoted as m, the switch means has input terminals and m+1 switch output terminals, and if the k-th input terminal from the left is denoted as Ik, the k-th and k+1-th switch output terminals from the left are denoted as Ok and Ok+1, respectively, and k takes each value from 1 to m, the switch means switches, depending on whether a second control signal (e.g., POL2) input to the switch means is at high level or low level, between whether the input terminal Ik is connected to the switch output terminal Ok and whether the input terminal Ik is connected to the switch output terminal Ok+1.
Further, the driving device may also include a voltage follower, and depending on whether the second control signal is at high level or low level, output from the leftmost potential output terminal of the voltage follower is put into a high impedance state or output from the rightmost potential output terminal of the voltage follower is put into the high impedance state.
Further, the liquid crystal display device may be configured to include two or more driving devices, and among adjacent two driving devices, the rightmost potential output terminal of the left-hand driving device and the leftmost potential output terminal of the right-hand driving device are connected to a common source line.
Further, the liquid crystal display device may be configured further to include: first latch means (e.g., first latch sections 32 for R, G and B in a sixth embodiment) for reading and holding R, G and B pixel values each for one pixel simultaneously; a shift register (e.g., shift register 31 in the sixth embodiment) for outputting a data reading instruction signal sequentially to instruct the first latch means to read each of the R, G and B pixel values each for one pixel; second latch means (e.g., second latch sections 33 for R, G and B in the sixth embodiment) for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means (e.g., level shifter 35) having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower (e.g., voltage follower 37 in the sixth embodiment) having m+1 potential input terminals and m+1 potential output terminals, and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to the pixel values of m pixels for one row, the DA converter has m+1 data input terminals and m+1 potential output terminals, the data output terminals of the second latch means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
Further, the liquid crystal display device may be configured further to include: first latch means (e.g., first latch sections 32 for R, G and B in a seventh embodiment) for reading and holding R, G and B pixel values each for one pixel simultaneously; a shift register (e.g., shift register 31 in the seventh embodiment) for outputting a data reading instruction signal sequentially to instruct the first latch means to read each of the R, G and B pixel values each for one pixel; second latch means (e.g., second latch sections 33 for R, G and B in the seventh embodiment) for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means (e.g., level shifter 45 in the seventh embodiment) having m data input terminals and m data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower (e.g., voltage follower 37 in the seventh embodiment) having m+1 potential input terminals and m+1 potential output terminals, and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to the pixel values of m pixels for one row, the DA converter has m+1 data input terminals and m+1 potential output terminals, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
Further, the liquid crystal display device may be configured further to include: first latch means (e.g., first latch sections 32 for R, G and B in an eighth embodiment) for reading and holding R, G and B pixel values each for one pixel simultaneously; a shift register (e.g., shift register 31 in the eighth embodiment) for outputting a data reading instruction signal sequentially to instruct the first latch means to read each of the R, G and B pixel values each for one pixel; second latch means (e.g., second latch sections 33 for R, G and B in the eighth embodiment) for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means (e.g., level shifters 45 for R, G and B in the eighth embodiment) having m data input terminals and m data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower (e.g., voltage follower 37 in the eighth embodiment) having m+1 potential input terminals and m+1 potential output terminals, and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to the pixel values of m pixels for one row, the DA converter has m data input terminals and m potential output terminals, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminal of the switch means are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the levels of the first control signal and the second control signal are switched alternately each time all rows belonging to a group are selected, and in one frame, when the second control signal is at high level, the first control signal also becomes high level, while when the second control signal is at low level, the first control signal also becomes high level, and in the next frame following the one frame, when the second control signal is at high level, the first control signal becomes low level, while when the second control signal is at low level, the first control signal becomes high level.
Further, the liquid crystal display device may be configured further to include: first latch means (e.g., first latch section 63 in a ninth embodiment) for reading and holding R, G and B pixel values each for one pixel simultaneously; a shift register (e.g., shift register 31 in the ninth embodiment) for outputting a data reading instruction signal sequentially to instruct the first latch means to read each of the R, G and B pixel values each for one pixel; second latch means (e.g., second latch section 43 in the ninth embodiment) for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means (e.g., level shifter 35 in the ninth embodiment) having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower (e.g., voltage follower 37 in the ninth embodiment) having m+1 potential input terminals and m+1 potential output terminals, and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the first latch means has m pixel value output terminals for causing the second latch means to read the pixel values, the second latch means has m+1 data reading terminals for reading the pixel values from the first latch means, and m+1 data output terminals for outputting data corresponding to the pixel values of pixels for one row, the DA converter has m+1 data input terminals and m+1 potential output terminals, the pixel value output terminals of the first latch means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data reading terminals of the second latch means in a one-to-one relationship, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
Further, the liquid crystal display device may be configured such that the number of columns of pixels to be driven is a multiple of 3, and the liquid crystal display device further includes: first latch means (e.g., first latch section 66 in a tenth embodiment) in which m+1 latch circuits (e.g., latch circuits 61 in the tenth embodiment) are arranged, each latch circuit having an input terminal (e.g., LS) for a data reading instruction signal to give an instruction to read a pixel value, a pixel value reading terminal (e.g., D) for reading a pixel value for one pixel input when the data reading instruction signal is input to the input terminal, and an output terminal (Q) for the pixel value; a shift register (e.g., shift register 31 in the tenth embodiment) having signal output terminals for a m/3 piece of data reading instruction signal and configured to output the data reading instruction signal sequentially from each of the signal output terminals; output of shift register switching means (e.g., output of shift register switching section 65 in the tenth embodiment) which, if the i-th signal output terminal from the left in the shift register is denoted as Ci and i takes each value from 1 to m/3, connects the signal output terminal Ci with input terminals of the 3·i−2-th, 3·i−1-th and 3·i-th latch circuits of the first latch means when the second control signal is at high level, or connects the signal output terminal Ci with input terminals of the 3·i−1-th, 3·i-th and 3·i+1-th latch circuits of the first latch means when the second control signal is at low level; second latch means (e.g., second latch section 43 in the tenth embodiment) for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means (e.g., level shifter 35 in the tenth embodiment) having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower (e.g., voltage follower 37 in the tenth embodiment) having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the m input terminals of the switch means are connected to data wiring for transferring pixel values for R, data wiring for transferring pixel values for G and data wiring for transferring pixel values for B, the switch output terminals of the switch means are connected to the pixel value reading terminals of the respective latch circuits in the first latch means in a one-to-one relationship, the second latch means has m+1 data reading terminals for reading pixel values from the first latch means and m+1 data output terminals for outputting data corresponding to pixel values of pixels for one row, DA converter has m+1 data input terminals and m+1 potential output terminals, the output terminals of the respective latch circuits in the first latch means are connected to the data reading terminals of the second latch means in a one-to-one relationship, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, the level of the second control signal is switched alternately each time all rows belonging to a group are selected after the second control signal is set to high level upon starting a frame, and the output of shift register switching means and the switch means maintain a state equal to that when the second control signal is at high level until the second control signal is generated in a first frame after power-on.
Further, the liquid crystal display device may be configured further to include: first latch means (e.g., first latch section 66 in an eleventh embodiment) having m+1 input terminals for a data reading instruction signal to give an instruction to read a pixel value, and configured such that, when the data reading instruction signal is input, the first latch means reads and holds a pixel value for one pixel corresponding to an input terminal to which the data reading instruction signal is input; a shift register (e.g., shift register 81 in the eleventh embodiment) having m signal output terminals for the data reading instruction signal and configured to output the data reading instruction signal sequentially from each signal output terminal; second latch means (e.g., second latch section 43 in the eleventh embodiment) for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means (e.g., level shifter 35 in the eleventh embodiment) having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and outputting the data from the data output terminals; and a voltage follower (e.g., voltage follower 37 in the eleventh embodiment) having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the first latch means has m+1 pixel value output terminals for causing the second latch means to read pixel values, the second latch means has m+1 data reading terminals for reading pixel values from the first latch means and m+1 data output terminals for outputting data corresponding to pixel values of pixels for one row, the DA converter has m+1 data input terminals and m+1 potential output terminals, the signal output terminals of the shift register are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the input terminals of the first latch means in a one-to-one relationship, the pixel value output terminals of the first latch means are connected to the data reading terminals of the second latch means in a one-to-one relationship, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, the level of the second control signal is switched alternately each time all rows belonging to a group are selected after the second control signal is set to high level upon starting a frame, and the switch means maintains a state equal to that when the second control signal is at high level until the second control signal is generated in a first frame after power-on.
Further, the liquid crystal display device may be configured further to include: first latch means (e.g., first latch section 66 in a twelfth embodiment) for reading and holding a pixel value on a pixel-by-pixel basis; a shift register (e.g., shift register 81 in the twelfth embodiment) for outputting a data reading instruction signal sequentially to instruct the first latch means to read a pixel value for one pixel; second latch means (e.g., second latch section 43 in the twelfth embodiment) for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means (e.g., level shifter 35 in the twelfth embodiment) having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower (e.g., voltage follower 37 in the twelfth embodiment) having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the first latch means has m pixel value output terminals for causing the second latch means to read pixel values, the second latch means has m+1 data reading terminals for reading pixel values from the first latch means, and m+1 data output terminals for outputting data corresponding to pixel values of pixels for one row, DA converter has m+1 data input terminals and m+1 potential output terminals, the pixel value output terminals of the first latch means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data reading terminals of the second latch means in a one-to-one relationship, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminal of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
Further, the liquid crystal display device may be configured further to include: first latch means (e.g., first latch section 66 in a thirteenth embodiment) for reading and holding a pixel value on a pixel-by-pixel basis; a shift register (e.g., shift register 81 in the thirteenth embodiment) for outputting a data reading instruction signal sequentially to instruct the first latch means to read a pixel value for one pixel; second latch means (e.g., second latch section 43 in the thirteenth embodiment) for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means (e.g., level shifter 35 in the thirteenth embodiment) having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower (e.g., voltage follower 37 in the thirteenth embodiment) having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to the pixel values of m pixels for one row, DA converter has m+1 data input terminals and m+1 potential output terminals, the data output terminals of the second latch means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
Further, the liquid crystal display device may be configured further to include: first latch means (e.g., first latch section 66 in a fourteenth embodiment) for reading and holding a pixel value on a pixel-by-pixel basis; a shift register (e.g., shift register 81 in the fourteenth embodiment) for outputting a data reading instruction signal sequentially to instruct the first latch means to read a pixel value for one pixel; second latch means (e.g., second latch section 43 in the fourteenth embodiment) for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means (e.g., level shifter 35 in the fourteenth embodiment) having m data input terminals and m data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower (e.g., voltage follower 37 in the fourteenth embodiment) having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to pixel values of m pixels for one row, DA converter has m+1 data input terminals and m+1 potential output terminals, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
Further, the liquid crystal display device may be configured further to include: first latch means (e.g., first latch section 66 in a fifteenth embodiment) for reading and holding a pixel value on a pixel-by-pixel basis; a shift register (e.g., shift register 81 in the fifteenth embodiment) for outputting a data reading instruction signal sequentially to instruct the first latch means to read a pixel value for one pixel; second latch means (e.g., second latch section 43 in the fifteenth embodiment) for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means (e.g., level shifter 35 in the fifteenth embodiment) having m data input terminals and m data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower (e.g., voltage follower 37 in the fifteenth embodiment) having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to the pixel values of m pixels for one row, the DA converter has m data input terminals and m potential output terminals, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminal of the switch means are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the levels of the first control signal and the second control signal are switched alternately each time all rows belonging to a group are selected, and in one frame, when the second control signal is at high level, the first control signal also becomes high level, while when the second control signal is at low level, the first control signal also becomes high level, and in the next frame following the one frame, when the second control signal is at high level, the first control signal becomes low level, while when the second control signal is at low level, the first control signal becomes high level.
According to still another exemplary aspect of the invention, there is provided a driving device for a liquid crystal display panel including a common electrode, a plurality of pixel electrodes arranged in a matrix, and source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side (e.g., left side) among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side (e.g., right side) opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, the driving device including: potential output means (e.g., potential setting section 11) having a plurality of potential output terminals from each of which a potential corresponding to an input pixel value is output, and configured to output a potential from each potential output terminal in such a manner to output a potential higher than a common electrode potential and a potential lower than the common electrode potential alternately in order of arrangement of the potential output terminals; and switch means (e.g., switch section 12) having a plurality input terminals and switch output terminals that is one more in number than the plurality input terminals, wherein if the k-th input terminal from the left is denoted as Ik, the k-th and k+1-th switch output terminals from the left are denoted as Ok and Ok+1, respectively, the number input terminals is denoted as n, and k takes each value from 1 to n, the switch means connects the input terminal Ik to either of the switch output terminals Ok and Ok+1, wherein the potential output means switches between output of a potential higher than the common electrode potential and output of a potential lower than the common electrode potential at each potential output terminal depending on a period for selecting each row in the odd-numbered group one by one or a period for selecting each row in the even-numbered group one by one, the switch means switches between the switch output terminals to be connected to each input terminal depending on the period for selecting each row in the odd-numbered group one by one or the period for selecting each row in the even-numbered group one by one, and the potential output means continues to output, from each potential output terminal, a potential specific to a pixel value corresponding to the potential output terminal, respectively, during a selection period of one row.
The driving device for a liquid crystal display panel according to the invention may be configured further to include control means (e.g., control section 3 or 3a) for outputting a first control signal (e.g., POL1) to control whether the potential of each potential output terminal of the potential output means is set higher or lower than the common electrode potential, and a second control signal (e.g., POL2) to give an instruction to determine to which of the switch output terminals Ok and Ok+1 the input terminal Ik is to be connected, wherein depending on whether the first control signal is at high level or low level, the potential output means switches between whether a potential higher than the common electrode potential is output from an odd-numbered potential output terminal from the left and a potential lower than the common electrode potential is output from an even-numbered potential output terminal from the left, and whether a potential lower than the common electrode potential is output from the odd-numbered potential output terminal from the left and a potential higher than the common electrode potential is output from the even-numbered potential output terminal from the left, the switch means switches between the switch output terminals Ok and Ok+1 to which the input terminal Ik is to be connected, depending on whether the second control signal is at high level or low level, and the control means switches the levels of the first control signal and the second control signal between the period for selecting each row in the odd-numbered group one by one and the period for selecting each row in the even-numbered group one by one.
According to yet another exemplary aspect of the invention, there is provided a driving device for a liquid crystal display panel including a common electrode, a plurality of pixel electrodes arranged in a matrix, and source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, the driving device including: a DA converter for inputting each data corresponding to each of pixel values for one row, converting the input data to an analog voltage, and outputting a potential after subjected to conversion, wherein depending on whether a first control signal input to the DA converter is at high level or low level, the DA converter switches between whether a potential higher than a common electrode potential is output from an odd-numbered potential output terminal from the left and a potential lower than the common electrode potential is output from an even-numbered potential output terminal from the left, and whether a potential lower than the common electrode potential is output from the odd-numbered potential output terminal from the left and a potential higher than the common electrode potential is output from the even-numbered potential output terminal from the left; and switch means for switching between whether the potential of a pixel electrode is set using the source line on the left side of the pixel electrode and whether the potential of the pixel electrode is set using the source line on the right side of the pixel electrode, wherein if the number of pixel columns to be driven is denoted as m, the switch means has input terminals and m+1 switch output terminals, and if the k-th input terminal from the left is denoted as Ik, the k-th and k+l-th switch output terminals from the left are denoted as Ok and Ok+1, respectively, and k takes each value from 1 to m, the switch means switches, depending on whether a second control signal input to the switch means is at high level or low level, between whether the input terminal Ik is connected to the switch output terminal Ok and whether the input terminal Ik is connected to the switch output terminal Ok+1.
Further, the driving device for a liquid crystal display panel may be configured further to include a voltage follower, wherein depending on whether the second control signal is at high level or low level, output from the leftmost potential output terminal of the voltage follower is put into a high impedance state or output from the rightmost potential output terminal of the voltage follower is put into the high impedance state.
According to yet another aspect of the invention, there is provided a liquid crystal display panel including: a common electrode; a plurality of pixel electrodes arranged in a matrix; source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes; and switch means (e.g., switch section 12) having a plurality input terminals and switch output terminals that is one more in number than the plurality of input terminals, wherein if the k-th input terminal from the left is denoted as Ik, the k-th and k+1-th switch output terminals from the left are denoted as Ok and Ok+1, respectively, the number input terminals is denoted as n, and k takes each value from 1 to n, the switch means connects the input terminal Ik to either of the switch output terminals Ok and Ok+1, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side (e.g., left side) among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side (e.g., right side) opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, each source line is connected to a corresponding switch output terminal of the switch means, and the switch means switches between the switch output terminals to be connected to each input terminal depending on the period for selecting each row in the odd-numbered group one by one or the period for selecting each row in the even-numbered group one by one.
According to yet another exemplary aspect of the invention, there is provided a liquid crystal display panel including: a common electrode; a plurality of pixel electrodes arranged in a matrix; and source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, and among the source lines, a specific odd-numbered source line has two branch portions to connect with different driving devices.
Embodiments of the present invention will now be described with reference to the accompanying drawings.
The power supply section 4 supplies voltage V0-V8 and V9-V17 to the driving device 1 (potential setting section 11 to be specifically described later). V0-V8 are voltages higher than the potential VCOM of a common electrode (not shown in
The driving device 1 controls the potentials of source lines S1 to Sn+1 provided on the liquid crystal display panel 2. The driving device 1 includes the potential setting section 11 and a switch section 12.
The potential setting section 11 captures image data under the control of the control section 3, and outputs potentials corresponding to pixel values indicated by the image data. The number of potential output terminals of the potential setting section 11 is n, and this is denoted as D1 to Dn.
In each row of the liquid crystal display panel 2, respective pixels are disposed in a repetitive pattern in order of R(red), G(green) and B(blue). Image data corresponding to pixels for one row are input into the potential setting section 11 in order from data (pixel value) corresponding to the leftmost pixel.
The potential setting section 11 captures this data for one row within one row selection period under the control of the control section 3, and outputs potentials corresponding to respective pieces of data for one row from the potential output terminals D1 to Dn during the next selection period. The potential setting section 11 outputs potentials in response to control signal STB input to the control section 3. STB is a control signal to specify a selection period of each row.
Thus, a potential corresponding to the pixel value of a corresponding pixel is output from each of the potential output terminals D1 to Dn according to the data sequence of pixels for one row sequentially input.
Further, the potential setting section 11 controls the potential output from each of the potential output terminals D1 to Dn to be a potential higher than VCOM or a potential lower than VCOM in response to control signal POL1 input from the control section 3. POL1 is a control signal to control whether the potential of each potential output terminal of the potential setting section 11 is set higher or lower than VCOM. The control section 3 alternates the level of POL1 between high level and low level in one frame per selection period. Note that one frame means a period required to select lines sequentially from the first row to the last row (for sequential line scanning).
When POL1 is at high level, the potential setting section 11 sets the potential of each of the odd-numbered potential output terminals D1, D3, D5, . . . from the left to a potential higher than VCOM (V0-V8 or a potential obtained by dividing the voltage based on V0-V8), and sets the potential of each of the even-numbered potential output terminals D2, D4, D6, . . . from the left to a potential lower than VCOM (V9-V17 or a potential obtained by dividing the voltage based on V9-V17). Hereinafter, V0-V8 or the potentials obtained by dividing the voltages based on V0-V8 are denoted as “V0-V8 or the like.” Similarly, V9-V17 or the potentials obtained by dividing the voltages based on V9-V17 are denoted as “V9-V17 or the like.” On the other hand, when POL1 is at low level, the potential setting section 11 sets the potential of each of the odd-numbered potential output terminals D1, D3, D5, . . . from the left to a potential lower than VCOM (V9-V17 or the like), and sets the potential of each of the even-numbered potential output terminals D2, D4, D6, . . . from the left to a potential higher than (V0-V8 or the like). Whether to output either of the potentials V0-V8 or the like and V9-V17 or the like is determined depending on the pixel value stored in the portion of the latch section corresponding to the potential output terminal.
The switch section 12 includes input terminals equal in number to the potential output terminals of the potential setting section 11, and switch output terminals that are one more in number than the number input terminals. In other words, the switch section 12 includes n input terminals I1 to In and n+1 switch output terminals O1 to On+1. Hereinafter, the switch output terminal is simply referred to as the output terminal.
Each of the input terminals I1 to In has a one-to-one relationship with each of the potential output terminals D1 to Dn of the potential setting section 11, and is connected to a corresponding potential output terminal. For example, I1 is connected to D1. The same holds true for the other input terminals.
If any input terminal of the input terminals is denoted as Ik (where 1≦k≦n), the input terminal Ik outputs a potential input from the corresponding potential output terminal (denoted as Dk) from any one of the output terminals Ok and Ok+1. Specifically, the input terminal Ik is connected to a first terminal of a first transistor 13, and a second terminal of the first transistor 13 is connected to the output terminal Ok. Similarly, the input terminal Ik is connected to a first terminal of a second transistor 14, and a second terminal of the second transistor 14 is connected to the output terminal Ok+1. Both the first transistor 13 and the second transistor 14 have a third terminal in addition to the first terminal and the second terminal. When a high-level signal (voltage) is input to the third terminal, electric conduction is created between the first terminal and the second terminal, while when a low-level signal (voltage) is input to the third terminal, electric conduction is blocked between the first terminal and the second terminal.
Further, a control signal POL2 is input to the third terminal of each first transistor 13 from the control section 3. The switch section 12 has a signal inversion section 15. POL2 is also input to the signal inversion section 15 from the control section 3. If input POL2 is at high level, the signal inversion section 15 inverts POL2 to low level, while if input POL2 is at low level, it inverts POL2 to high level. Then, the signal inversion section 15 inputs inverted POL2 to the third terminal of each second transistor 14.
Thus, when POL2 output from the control section 3 is at high level, high-level POL2 is input to the third terminal of each first transistor 13, and low level POL2 is input to the third terminal of each second transistor 14, causing each input terminal Ik to be electrically conducted with the output terminal Ok, but not with the output terminal Ok+1. As a result, the potential output from the potential output terminal Dk of the potential setting section 11 is output from the output terminal Ok of the switch section 12.
On the other hand, when POL2 output from the control section 3 is at low level, low-level POL2 is input to the third terminal of each first transistor 13, and high-level POL2 is input to the third terminal of each second transistor 14, causing each input terminal Ik not to be electrically conducted with the output terminal Ok, but to be electrically conducted with the output terminal Ok+1. As a result, the potential output from the potential output terminal Dk of the potential setting section 11 is output from the output terminal Ok+1 of the switch section 12.
In other words, POL2 is a control signal for controlling to which of the output terminals Ok and Ok+1 the input terminal Ik is to be connected.
The switch section 12 can also be schematically illustrated as in
The liquid crystal display panel 2 shown in
As mentioned above, in each row of the liquid crystal display panel 2, respective pixels are disposed in a repetitive pattern in order of R(red), G(green) and B(blue). In
The liquid crystal display panel 2 includes not only source lines on the left side of the pixel electrodes in each column, but also a source line on the right side of the rightmost pixel column. In other words, the number of source lines is one more than the number of columns of the pixel electrodes. Further, pixel electrodes for one column are disposed between adjacent source lines. This example shows a case where the number of columns of the pixel electrodes is n columns, and the number of source lines is n+1. The source lines are denoted as S1 to Sn+1.
Each source line corresponds to one output terminal of the switch section 12, respectively, and is connected to a corresponding output terminal of the switch section 12 according to the order of the sequence of source lines.
An active element 22 is provided for each pixel electrode 21. The following description will be made by taking, as an example, a case where the active element 22 is a TFT (Thin Film Transistor), but any active element other than TFT may be provided for each pixel electrode 21.
For each pixel electrode 21 in odd-numbered rows, the TFT 22 is provided on the left side of the pixel electrode 21, and is connected to the pixel electrode 21 and the source line on the left side thereof. On the other hand, for each pixel electrode 21 in even-numbered rows, the TFT 22 is provided on the right side of the pixel electrode 21, and is connected to the pixel electrode 21 and the source line on the right side thereof (see
Here, the TFT in the odd-numbered row is provided on the left side of the pixel electrode and the TFT in the even-numbered row is provided on the right side of the pixel electrode for descriptive purposes, but the position of the TFT is optional as long as the pixel electrode in the odd-numbered row is connected to the left source line and the pixel electrode in the even-numbered row is connected to the right source line.
For example, each TFT 22 is connected to the pixel electrode 21 in such a manner that the source is connected to the source line and the drain is connected to the pixel electrode 21.
The liquid crystal display panel 2 also includes gate lines G1, G2, G3, . . . for respective rows of the pixel electrodes arranged in a matrix. In
The display device includes a gate driver (not shown) for setting the potential of each gate line. The gate driver selects gate lines sequentially line by line and sets a selected gate line to a potential upon selection and an unselected gate line to a potential upon non-selection. Thus, the rows are selected one by one. The driving device 1 may function as the gate driver.
The control section 3 inputs, to the gate driver, a control signal (hereinafter denoted as STV) to instruct it to start one frame, and a control signal (gate clock, hereinafter denoted as CPV) to instruct it to switch the selected row to another.
When the gate potential of each TFT 22 is set to the potential upon selection, current flows between the drain and the source, while when the gate potential is set to the potential upon non-selection, no current flows between the drain and the source. As a result, each pixel electrode in the selected row becomes equal in potential to the source line connected through the TFT. On the other hand, each pixel electrode in the unselected rows is electrically disconnected from the source line.
In the example shown in
Amorphous silicon is used, for example, for each active element 22 provided on the liquid crystal display panel 2. Further, low-temperature polysilicon may be used, for example, for the driving device 1 including each active element 22.
The control section 3 inputs POL1, SCLK and STB to the potential setting section 11 and POL2 to the switch section 12 to control the driving device 1.
The control section 3 uses STB to define the selection period, and the potential setting section 11 uses SCLK to have the register capture data for one row. Then, the control section 3 causes STB to rise so that the potential setting section 11 will transfer the captured data for one row to the latch section (not shown). Further, the control section 3 causes STB to fall so that the potential setting section 11 will output, from each of the potential output terminals D1 to Dn, each of potentials corresponding to the data for one row transferred to the latch section.
Further, the control section 3 switches the levels of POL1 and POL2 between high level and low level alternately per selection period.
Note that the control section 3 switches between the level of POL1 upon selection of an odd-numbered row and the level of POL1 upon selection of an even-numbered row alternately on a frame-by-frame basis. For example, suppose that the control section 3 sets POL1 to high level upon selection of an odd-numbered row and to low level upon selection of an even-numbered row in a frame. In this case, in the next frame, the control section 3 sets POL1 to low level upon selection of an odd-numbered row and to high level upon selection of an even-numbered row. Thus, the control section 3 switches the level of POL1 on a frame-by-frame basis.
Further, the control section 3 sets the level of POL2 to high level upon selection of an odd-numbered row and to low level upon selection of an even-numbered row regardless of the frame.
Upon starting a frame, since the first row as an odd-numbered row is selected, the control section 3 needs to set the level of POL2 to high level upon starting the frame. The control section 3 has only to set the level of POL2 to high level based on the rising edge of STB and the falling edge of STB within a period during which STV (see
Next, the operation will be described.
The control section 3 causes first STB to rise in the frame. The control section 3 also causes POL1 and POL2 to rise to high level in response to the rise of STB as control in the selection period of the first row (odd-numbered row).
When STB rises, the potential setting section 11 transfers, to the latch section (not shown), the data for one row (data for the first row) stored in the register (not shown) at the time. The potential setting section 11 transfers the data to the latch section in order of data captured. In other words, the data on the leftmost pixel first input is transferred to a portion of the latch section corresponding to the leftmost potential output terminal D1, and the data on the second pixel from the left is transferred to a portion of the latch section corresponding to the second potential output terminal D2 from the left. The same holds true for the data on the other pixels.
When STB rises, the potential setting section 11 outputs a potential (any of V0-V8 or the like, or any of V9-V17 or the like) corresponding to the data on each pixel in the first row stored in the latch section to one of the potential output terminals D1 to Dn corresponding to each pixel. At this time, since POL1 is at high level, the potential setting section 11 sets the output potential of each of the odd-numbered potential output terminals D1, D3, D5, . . . from the left to a potential (any of V0-V8 or the like) higher than VCOM. Whether to output any of V0-V8 or the like may be determined according to the pixel value of each of the odd-numbered pixels from the left, respectively. Further, since POL1 is at high level, the potential setting section 11 sets the output potential of each of the even-numbered each potential output terminals D2, D4, D6, . . . from the left to a potential (any of V9-V17 or the like) lower than VCOM. Whether to output any of V9-V17 or the like may be determined according to the pixel value of each of the even-numbered pixels from the left, respectively.
Thus, since POL1 is at high level, the output potentials of the odd-numbered potential output terminals D1, D3, D5, . . . from the left become higher than VCOM and the output potentials of the even-numbered potential output terminals D2, D4, D5, . . . from the left become lower than VCOM.
Further, since the data stored in the latch section are sequenced in order of input of data for the first row, the potential output section 11 outputs the potentials corresponding to the data from the potential output terminals D1 to Dn without changing the order of the sequence of data.
POL2 is also at high level at the rise time of STB. Therefore, the odd-number input terminals (noted as I(2j−1)) from the left in the switch section 12 are electrically conducted with the odd-numbered output terminals (referred to as O(2j−1)) from the left, respectively. As a result, the odd-numbered output terminals from the left in the switch section 12 output potentials equal to the potentials of the odd-numbered potential output terminals from the left in the potential setting section 11. Specifically, the output terminals O1, O3, O5, . . . of the switch section 12 output potentials equal to the potentials of the potential output terminals D1, D3, D5, . . . , respectively (see
Thus, upon selection of the first row, each of the odd-numbered output terminals O(2j−1) from the left outputs the potential higher than VCOM to make the potentials of the odd-numbered source lines S1, S3, S5, . . . from the left higher than VCOM (see
Further, since POL2 is at high level, the even-number input terminals (denoted as I(2j)) from the left in the switch section 12 are electrically conducted with the even-numbered output terminals (referred to as O(2j)) from the left, respectively. Therefore, the even-numbered output terminals from the left in the switch section 12 output potentials equal to the potentials of the even-numbered potential output terminals from the left in the potential setting section 11. Specifically, the output terminals O2, O4, O6, . . . of the switch section 12 output potentials equal to the potentials of the potential output terminals D2, D4, D6 . . . , respectively (see
Thus, upon selection of the first row, each even-numbered output terminal O(2j) from the left outputs the potential lower than VCOM to make the potentials of the even-numbered source lines S2, S4, S6, . . . from the left lower than VCOM (see
As mentioned above, the potentials of the odd-numbered source lines from the left become higher than VCOM and the potentials of the even-numbered source lines from the left become lower than VCOM upon selection of the first row.
Each pixel electrode 21 in the first row (odd-numbered row) is connected to the source line located on the left side thereof. Therefore, each pixel electrode 21 in the first row becomes equal in potential to the left-hand source line. For example, the leftmost pixel electrode in the first row becomes equal in potential to the source line S1.
The potential setting section 11 maintains the potential output state during the selection period without changing the output potential of each potential output terminal to a potential corresponding to data on another pixel.
Next, the control section 3 causes STB to rise again. The control section 3 also changes POL1 and POL1 from high level to low level in response to the rise of STB as control in the selection period of the second row (even-numbered row) (see
When STB rises, the potential setting section 11 transfers, to the latch section (not shown), the data for one row (data for the second row) stored in the register (not shown) at the time. This operation is the same as that upon selection of the first row.
When STB rises, the potential setting section 11 outputs a potential (any of V0-V8 or the like, or any of V9-V17 or the like) corresponding to the data on each pixel in the second row stored in the latch section to one of the potential output terminals D1 to Dn corresponding to each pixel. At this time, since POL1 is at low level, the potential setting section 11 sets the output potential of each of the odd-numbered potential output terminals D1, D3, D5, . . . from the left to a potential (any of V9-V17 or the like) lower than VCOM. Whether to output any of V9-V17 or the like may be determined according to the pixel value of each of the odd-numbered pixels from the left, respectively. Further, since POL1 is at low level, the potential setting section 11 sets the output potential of each of the even-numbered each potential output terminals D2, D4, D6, . . . from the left to a potential (any of V0-V8 or the like) higher than VCOM. Whether to output any of V0-V8 or the like may be determined according to the pixel value of each of the even-numbered pixels from the left, respectively.
Thus, since POL1 is at low level, the output potentials of the odd-numbered potential output terminals D1, D3, D5, . . . from the left become lower than VCOM and the output potentials of the even-numbered potential output terminals D2, D4, D6, . . . from the left become higher than VCOM.
Further, since the data stored in the latch section are sequenced in order of input of data for the second row, the potential output section 11 outputs the potential corresponding to the data from each of the potential output terminals D1 to Dn without changing the order of the sequence of data.
POL2 is at low level at the rise time of STB. Therefore, the odd-number input terminals I(2j−1) from the left in the switch section 12 are electrically conducted with the even-numbered output terminals O(2j) from the left, respectively. As a result, the even-numbered output terminals from the left in the switch section 12 output potentials equal to the potentials of the odd-numbered potential output terminals from the left in the potential setting section 11. Specifically, the output terminals O2, O4, O6, . . . of the switch section 12 output potentials equal to the potentials of the potential output terminals D1, D3, D5, . . . , respectively (see
Thus, upon selection of the second row, each of the even-numbered output terminals O(2j) from the left outputs the potential lower than VCOM to make the potentials of the even-numbered source lines S2, S4, S6, . . . from the left lower than VCOM (see
Further, since POL2 is at low level, the even-number input terminals I(2j) from the left in the switch section 12 are electrically conducted with the odd-numbered output terminals from the left, respectively. Therefore, the odd-numbered output terminals from the left in the switch section 12 output potentials equal to the potentials of the even-numbered potential output terminals from the left in the potential setting section 11. Specifically, the output terminals O3, O5, . . . of the switch section 12 outputs potentials equal to the potentials of the potential output terminals D2, D4, . . . , respectively (see
Thus, upon selection of the second row, each of the odd-numbered each output terminals from the left in the switch section 12 outputs the potential higher than VCOM to make the potentials of the odd-numbered source lines S3, S5, . . . from the left higher than VCOM (see
As mentioned above, the potentials of the odd-numbered source lines from the left become higher than VCOM and the potentials of the even-numbered source lines from the left become lower than VCOM upon selection of the second row.
Each pixel electrode 21 in the second row (even-numbered row) is connected to the source line located on the right side thereof. Therefore, each pixel electrode 21 in the second row becomes equal in potential to the right-hand source line. For example, the leftmost pixel electrode in the second row becomes equal in potential to the source line S2.
As will be appreciated from the foregoing, even if the selected row is changed, the odd-numbered source lines from the left are kept higher in potential than VCOM and the even-numbered source lines from the left are kept lower in potential than VCOM.
After that, in this frame, the same operation as that upon selection of the first row is performed upon selection of an odd-numbered row, and the same operation as that upon selection of the second row is performed upon selection of an even-numbered row.
Therefore, in this frame, the odd-numbered source lines (source lines indicated by the solid line in
As a result of the operation in this frame, the polarity of each pixel is as shown in
In the next frame, the control section 3 sets POL1 to low level upon the first selection period, and after that, the control section 3 switches the level of POL1 per selection period. The others are the same as those in the above-mentioned frame.
The control section 3 causes first STB to rise in this frame. The control section 3 also sets POL1 to low level in response to the rise of STB as control in the selection period of the first row (odd-numbered row). Like in the previous frame, the control section 3 causes POL2 to rise to high level (see
When STB rises, the potential setting section 11 transfers, to the latch section (not shown), the data for one row (data for the first row) stored in the register (not shown) at the time. This operation is the same as that described with respect to the previous frame.
When STB rises, the potential setting section 11 outputs a potential corresponding to the data on each pixel in the first row stored in the latch section to one of the potential output terminals D1 to Dn corresponding to each pixel. At this time, since POL1 is at low level, the potential setting section 11 sets the output potential of each of the odd-numbered potential output terminals D1, D3, D5, . . . from the left to a potential (any of V9-V17 or the like) lower than VCOM. Whether to output any of V9-V17 or the like may be determined according to the pixel value of each of the odd-numbered pixels from the left, respectively. Further, since POL1 is at low level, the potential setting section 11 sets the output potential of each of the even-numbered each potential output terminals D2, D4, D6, . . . from the left to a potential (any of V0-V8 or the like) higher than VCOM. Whether to output any of V0-V8 or the like may be determined according to the pixel value of each of the even-numbered pixels from the left, respectively.
Thus, since POL1 is at low level, the output potentials of the odd-numbered potential output terminals D1, D3, D5, . . . from the left become lower than VCOM and the output potentials of the even-numbered potential output terminals D2, D4, D6, . . . from the left become higher than VCOM.
Further, since the data stored in the latch section are sequenced in order of input of data for the first row, the potential output section 11 outputs the potentials corresponding to the data from the potential output terminals D1 to Dn without changing the order of the sequence of data. This point is the same as that for the previous frame.
On the other hand, POL2 is at high level at the rise time of STB. Therefore, the odd-number input terminals I(2j−1) from the left in the switch section 12 are electrically conducted with the odd-numbered output terminals O(2j−1) from the left, respectively. As a result, the odd-numbered output terminals from the left in the switch section 12 output potentials equal to the potentials of the odd-numbered potential output terminals from the left in the potential setting section 11. Specifically, the output terminals O1, O3, O5, . . . of the switch section 12 output potentials equal to the potentials of the potential output terminals D1, D3, D5, . . . , respectively (see
Thus, upon selection of the first row, each of the odd-numbered output terminals O(2j−1) from the left outputs the potential lower than VCOM to make the potentials of the odd-numbered source lines S1, S3, S5, . . . from the left lower than VCOM (see
Further, since POL2 is at high level, the even-number input terminals I(2j) from the left in the switch section 12 are electrically conducted with the even-numbered output terminals O(2j) from the left, respectively. Therefore, the even-numbered output terminals from the left in the switch section 12 output potentials equal to the potentials of the even-numbered potential output terminals from the left in the potential setting section 11. Specifically, the output terminals O2, O4, O6, . . . of the switch section 12 output potentials equal to the potentials of the potential output terminals D2, D4, D6, . . . , respectively (see
Thus, upon selection of the first row, each of the even-numbered output terminals O(2j) from the left outputs the potential higher than VCOM to make the potentials of the even-numbered source lines S2, S4, S6, . . . from the left higher than VCOM (see
As mentioned above, the potentials of the odd-numbered source lines from the left become lower than VCOM and the potentials of the even-numbered source lines from the left become higher than VCOM upon selection of the first row.
Each pixel electrode 21 in the first row (odd-numbered row) is connected to the source line located on the left side thereof. Therefore, each pixel electrode 21 in the first row becomes equal in potential to the left-hand source line.
Next, the control section 3 causes STB to rise again. The control section 3 changes POL1 from low level to high level in response to the rise of STB as control in the selection period of the second row (even-numbered row) (see
When STB rises, the potential setting section 11 transfers, to the latch section (not shown), the data for one row (data for the second row) stored in the register (not shown) at the time.
When STB rises, the potential setting section 11 outputs a potential corresponding to the data on each pixel in the second row stored in the latch section to one of the potential output terminals D1 to Dn corresponding to each pixel. At this time, since POL1 is at high level, the potential setting section 11 sets the output potential of each of the odd-numbered potential output terminals D1, D3r D5, . . . from the left to a potential (any of V0-V8 or the like) higher than VCOM. Whether to output any of V0-V8 or the like may be determined according to the pixel value of each of the odd-numbered pixels from the left, respectively. Further, since POL1 is at high level, the potential setting section 11 sets the output potential of each of the even-numbered each potential output terminals D2, D4, D6, . . . from the left to a potential (any of V9-V17 or the like) lower than VCOM. Whether to output any of V9-V17 or the like may be determined according to the pixel value of each of the even-numbered each pixels from the left, respectively.
Thus, since POL1 is at high level, the output potentials of the odd-numbered potential output terminals D1, D3, D5, . . . from the left become higher than VCOM and the output potentials of the even-numbered potential output terminals D2, D4, D6, . . . from the left become lower than VCOM.
Further, since the data stored in the latch section are sequenced in order of input of data for the second row, the potential output section 11 outputs the potential corresponding to the data from each of the potential output terminals D1 to Dn without changing the order of the sequence of data.
On the other hand, POL2 is at low level at the rise time of STB. Therefore, the odd-number input terminals I(2j−1) from the left in the switch section 12 are electrically conducted with the even-numbered output terminals O(2j) from the left, respectively. As a result, the even-numbered output terminals from the left in the switch section 12 output potentials equal to the potentials of the odd-numbered potential output terminals from the left in the potential setting section 11. Specifically, the output terminals O2, O4, O6, . . . of the switch section 12 output potentials equal to the potentials of the potential output terminals D1, D3, D5, . . . , respectively (see
Thus, upon selection of the second row, each of the even-numbered output terminals O(2j) from the left outputs the potential higher than VCOM to make the potentials of the even-numbered source lines S2, S4, S6, . . . from the left higher than VCOM (see
Further, since POL2 is at low level, the even-number input terminals I(2j) from the left in the switch section 12 are electrically conducted with the odd-numbered output terminals from the left, respectively. Therefore, the odd-numbered output terminals from the left in the switch section 12 output potentials equal to the potentials of the even-numbered potential output terminals from the left in the potential setting section 11. Specifically, the output terminals O3, O5, . . . of the switch section 12 outputs potentials equal to the potentials of the potential output terminals D2, D4, . . . , respectively (see
Thus, upon selection of the second row, each of the odd-numbered each output terminals from the left in the switch section 12 outputs the potential lower than VCOM to make the potentials of the odd-numbered source lines S3, S5, . . . from the left lower than VCOM (see
As mentioned above, the potentials of the odd-numbered source lines from the left become lower than VCOM and the potentials of the even-numbered source lines from the left become higher than VCOM upon selection of the second row.
Each pixel electrode 21 in the second row (even-numbered row) is connected to the source line located on the right side thereof. Therefore, each pixel electrode 21 in the second row becomes equal in potential to the right-hand source line.
As will be appreciated from the foregoing, even if the selected row is changed in the frame, the odd-numbered source lines from the left are kept lower in potential than VCOM and the even-numbered source lines from the left are kept higher in potential than VCOM.
After that, in this frame, the same operation as that upon selection of the first row is performed upon selection of an odd-numbered row, and the same operation as that upon selection of the second row is performed upon selection of an even-numbered row.
Therefore, in this frame, the odd-numbered source lines from the left are maintained at the potentials lower than VCOM. On the other hand, the even-numbered source lines from the left are maintained at the potentials higher than VCOM. Thus, the power consumption can be reduced.
As a result of the operations for this frame, the polarity of each pixel is as shown in
After that, the frame operation illustrated in
According to the first embodiment, the potential of each source line is maintained higher than VCOM or lower than VCOM in a frame. This can reduce the number of pixels having the same polarity and appearing consecutively (in the first embodiment, adjacent pixels are made to have different polarities) to drive the liquid crystal display panel while reducing power consumption.
Further, it is determined on a row-by-row basis to which source line, the left-hand source line or the right-hand source line, each pixel electrode is connected. Then, the switch section 12 connects the output terminals of the potential setting section 11 to the output terminals that reach the source lines connected to the pixel electrodes, respectively. In this case, no change in connecting condition on the output terminals of the potential setting section 11 is made during the selection period. Therefore, data on each pixel included in the input data for one row can be transferred to the latch section without changing the order of the sequence of data and output a potential corresponding to the data on each pixel.
Since the connecting condition on the output terminals of the potential setting section 11 is not changed during the selection period, sufficient time required to set desired potentials of the source lines can be secured within the selection period. This eliminates the problem that the source lines may not be able to be set to desired potentials depending on the number of gate lines (the size of the display panel).
Further, the power consumption can be reduced, and this can prevent the driving device 1 from generating heat. For example, even if the liquid crystal display panel 2 is driven at double speed or quad-speed, the heat generation can be prevented.
The above has described the case where the control section 3 inputs POL2 to the switch section 12 of the driving device 1. However, the potential setting section 11 may generate and input POL2 to the switch section 12, rather than that the control section 3 generates POL2.
Further, depending on the specifications of a driver IC that accepts a TAB substrate or COG (Chip on Glass), the number of outputs in one chip may be selectable in a setting mode. For example, some driver ICs with 480-pin output may be able to switch to 402-pin output in the setting mode. In this case, unused 78 pins are set up near the center of the driver IC.
In the first embodiment, pixel electrodes in odd-numbered rows are connected to left-hand source lines and pixel electrodes in even-numbered rows are connected to right-hand source lines. In a second embodiment, two or more consecutive rows are so set as one group that pixel electrodes in each row of an odd-numbered group are connected to left-hand source lines and pixel electrodes in each row of an even-numbered group are connected to right-hand source lines.
The liquid crystal display panel 2a is configured to sandwich liquid crystal (not shown) between the multiple pixel electrodes 21 arranged in a matrix and the common electrode (not shown in
The liquid crystal display panel 2a includes not only source lines on the left side of the pixel electrodes in each column, but also a source line on the right side of the rightmost pixel column. In other words, the number of source lines is one more than the number of columns of the pixel electrodes. Further, pixel electrodes for one column are disposed between adjacent source lines. Each of source lines S1 to Sn+1 corresponds to one of output terminals of the switch section 12, respectively, and is connected to the corresponding output terminal of the switch section 12 according to the order of the sequence of source lines.
The active element 22 is provided for each pixel electrode 21, and each pixel electrode 21 is connected to a source line through the active element 22. The above configuration is the same as that of the liquid crystal display panel 2 according to the first embodiment. Like in the first embodiment, the following description will be made by taking, as an example, the case where the active element 22 is a TFT.
In the second embodiment, two or more consecutive rows of pixel electrodes 21 are combined into one group. In
The following description will be made by taking the case where two consecutive rows are combined into one group. In other words, the first row and second row of pixel electrodes 21 are grouped as the first group, and the third row and fourth row are grouped as the second group. The subsequent rows are also grouped in the same manner.
Then, each pixel electrode 21 in each row of an odd-numbered group is connected to a left-hand source line through each TFT 22. In odd-numbered groups, for example, the TFTs 22 are provided on the left side of the pixel electrodes 21, respectively. However, the position of the TFT 22 is not limited to this position, i.e., the position is optional.
Each pixel electrode 21 in each row of an even-numbered group is connected to a right-hand source line through each TFT 22. In even-numbered groups, for example, the TFTs 22 are provided on the right side of the pixel electrodes 21, respectively. However, the position of the TFT 22 is not limited to this position, i.e., the position is optional.
The operations of the power supply section 4 and the driving device 1 (the potential setting section 11 and the switch section 12) is the same as those in the first embodiment. Since the second embodiment is different from the first embodiment in the mode in which the control section 3a outputs POL1 and POL2, the potential setting section 11 and the switch section 12 operate in accordance with POL1 and POL2 input from the control section 3a.
Like in the first embodiment, the liquid crystal display device of the second embodiment also includes the gate driver (not shown) for setting the potential of each gate line. The gate driver selects gate lines sequentially one by one and sets a selected gate line to a potential upon selection and an unselected gate line to a potential upon non-selection. Thus, the rows in each group are selected one by one. The driving device 1 may function as the gate driver.
The control section 3a outputs POL1, POL2, SCLK and STB to control the potential setting section 11 and the switch section 12.
The output mode of SCLK and STB is the same as that in the first embodiment. In other words, the control section 3a uses STB to set down the selection period, and uses SCLK to cause the potential setting section 11 to capture data for one row into the register. Then, the control section 3a causes STB to rise so that the potential setting section 11 will transfer the captured data for one row to the latch section (not shown). Further, the control section 3a causes STB to fall so that the potential setting section 11 will output, from each of the potential output terminals D1 to Dn, each potential corresponding to the data for one row transferred to the latch section.
In the second embodiment, the control section 3a switches the levels of POL1 and POL2 between high level and low level alternately in one frame on a group-by-group basis.
In other words, the control section 3a switches between the level of POL1 when each row in the odd-numbered group is selected one by one and the level of POL1 when each row in the even-numbered group is selected one by one alternately on a frame-by-frame basis. For example, suppose that the control section 3a sets, in a frame, the level of POL1 to high level when each row in the odd-numbered group is selected one by one and the level of POL1 to low level when each row in the even-numbered group is selected one by one. In the next frame, the control section 3a sets the level of POL1 to low level when each row in the odd-numbered group is selected one by one and the level of POL1 to high level when each row in the even-numbered group is selected one by one.
Further, regardless of the frame, the control section 3a sets the level of POL2 to high level when each row in the odd-numbered group is selected one by one and the level of POL2 to low level when each row in the even-numbered group is selected one by one.
In the embodiment, if the control section 3 sets STB to high level in response to CPV while STV (see
Next, the operation will be described. First, a description will be made of a frame in which POL1 is set to high level during a period for selecting each row in the odd-numbered group one by one (hereinafter referred to as the selection period of the odd-numbered group for descriptive purposes) and POL1 is set to low level during a period for selecting each row in the even-numbered group one by one (hereinafter referred to as the selection period of the even-numbered group for descriptive purposes).
Upon selection period of the odd-numbered group, the control section 3a sets POL1 and POL2 to high level, respectively (see
Further, upon selection period of the even-numbered group, the control section 3a sets POL1 and POL2 to low level, respectively (see
Thus, in this frame, each source line is maintained at a potential higher than VCOM or a potential lower than VCOM.
As a result of the above frame operation, the polarity of each pixel is as shown in
Next, a description will be made of a frame in which POL1 is set to low level upon selection period of the odd-numbered group and POL1 is set to high level upon selection period of the even-numbered group.
Upon selection period of the odd-numbered group, the control section 3a sets POL1 to low level and POL2 to high level (see
Further, upon selection period of the even-numbered group, the control section 3a sets POL1 to high level and POL2 to low level (see
Thus, in this frame, each source line is also maintained at a potential higher than VCOM or a potential lower than VCOM.
As a result of the above frame operation, the polarity of each pixel is as shown in FIG. In other words, the pixels in each row in the odd-numbered group have negative polarity, positive polarity, negative polarity, positive polarity, . . . , and the pixels in each row in the even-numbered group have positive polarity, negative polarity, positive polarity, negative polarity, . . . . A comparison between
The second embodiment is the same as the first embodiment, except in that consecutive rows are so grouped that longitudinal pixels belonging to the same group will be sequenced with the same polarity. Thus, the second embodiment also has effects similar to the first embodiment. However, the first embodiment is preferred in that all adjacent pixels are different in polarity from each other.
In the second embodiment, the liquid crystal display device may also be configured such that the potential setting section 11 generates and inputs POL2 to the switch section 12, rather than that the control section 3a generates POL2. In this case, as described in the first embodiment, the control section 3a outputs STV not only to the gate driver (not shown) but also to the potential setting section 11. During a period in which STV input from the control section 3a is at high level, if STB input from the control section 3 has become high level, the potential setting section 11 switches the level of POL2 from low level to high level during the period in which STB is maintained at high level. After that, if the number of rows forming a group is denoted as g, the potential setting section 11 has just to repeat switching of the level of POL2 during a period in which STB becomes high level after g times. The others are the same as those already described, except in that the potential setting section 11 generates POL2 and STV is input to the potential setting section 11.
Note that the first embodiment corresponds to a case where the number of rows belonging to each group in the second embodiment is one. Therefore, it can be said that the first embodiment is another aspect of the second embodiment.
Further, in the second embodiment, the description is made of the case where each pixel in the odd-numbered group is connected to a left-hand source line and each pixel in the even-numbered group is connected to a right-hand source line, but the structure may be such that each pixel in the odd-numbered group is connected to a right-hand source line and each pixel in the even-numbered group is connected to a left-hand source line. In this case, the control section 3a outputs POL1 and POL2 according to this structure.
Similarly, the structure in the first embodiment may be such that each pixel in odd-numbered rows is connected to a right-hand source line and each pixel in even-numbered rows is connected to a left-hand source line. In this case, the control section 3 outputs POL1 and POL2 according to this structure. The same holds true for each embodiment to be described below.
The liquid crystal display device of the third embodiment includes two or more driving devices 1a and 1b, a liquid crystal display panel 2b, the control section 3 and the power supply section 4. Here, a case where two driving devices 1a and 1b are provided will be described, but three or more driving devices may be provided.
The driving devices 1a and 1b have the same structure as the driving device 1 in the first embodiment, including the potential setting section 11 and the switch section 12, respectively. Note that in
The potential setting section 11 provided in each of the driving devices 1a and 1b includes n potential output terminals D1 to Dn, respectively. Then, like in the first embodiment, the potential setting section 11 outputs a potential higher than VCOM and a potential lower than VCOM alternately in response to POL1 input to each potential output terminal. As for the potential of the rightmost potential output terminal Dn of the potential setting section 11 in the left driving device 1a and the potential of the leftmost potential output terminal D1 of the potential setting section 11 in the right driving device 1b, if one output potential is higher than VCOM, the other output potential is set lower than VCOM. To this end, the number, n, of potential output terminals of each potential setting section 11 is set to an even number. Further, in order to combine R, G and B into one set, the number of potential output terminals of each potential setting section 11 needs to be a multiple of 3. Therefore, in this embodiment, it is assumed that the number, n, of potential output terminals of each potential setting section 11 is a multiple of 6.
The operation of each potential setting section 11 performed in response to POL1, SCLK and STB is the same as that in the first embodiment.
Further, the left the left driving device 1a takes charge of processing the first half of image data for one row, the right driving device 1b takes charge of processing the second half of the data for one row. In other words, the potential setting section 11 of the driving device 1a captures the first half of data for one row sequentially in response to SCLK. On the other hand, the potential setting section 11 of the driving device 1b captures the second half of data for one row sequentially in response to SCLK.
The switch section 12 provided in each of the driving devices 1a and 1b is the same as the switch section 12 in the first embodiment, including input terminals I1 to In and n+1 output terminals O1 to On+1. The operation of each switch section 12 performed in response to POL2 is the same as that in the first embodiment.
The liquid crystal display panel 2b is configured to sandwich liquid crystal (not shown) between multiple pixel electrodes 21 arranged in a matrix, a common electrode (not shown in
The liquid crystal display panel 2b includes not only source lines on the left side of the pixel electrodes in each column, but also a source line on the right side of the rightmost pixel column. In other words, the number of source lines is one more than the number of columns of the pixel electrodes. Further, pixel electrodes for one column are disposed between adjacent source lines. The above is the same as in the first embodiment.
In the embodiment, however, the number of columns of pixel electrodes is more than the number, n, of potential output terminals of one potential setting section 11. Here, a case where the number of columns of pixel electrodes is 2n is taken as an example. In this case, the number of source lines is 2n+1 and the source lines are denoted as S1 to S(2n+1) from the left.
The first to n-th source lines S1 to Sn from the left correspond to the output terminals O1 to On of the switch section 12 of the left driving device 1a, respectively, and are connected to the output terminals O1 to On in order of the sequence of source lines. The n+1-th source line Sn+1 from the left is connected to the rightmost output terminal On+1 of the left switch section 12 and the leftmost output terminal O1 of the right switch section. Specifically, as shown in
The n+2-th and subsequent source lines Sn+2 to S(2n+1) from the left correspond to the output terminals O2 to On+1 of the switch section 12 of the right driving device 1b, respectively, and are connected to the output terminal O2 to On+1 in order of the sequence of source lines.
Thus, when two or more switch sections 12 exist side by side, the rightmost output terminal On+1 of the left switch section 12 and the leftmost output terminal O1 of the right switch section 12 are connected to the same source line, and each of the other output terminals is connected to one source line in order of the sequence of source lines.
In
Further, the active element 22 is provided for each pixel electrode 21, and each pixel electrode 21 is connected to a source line through the active element 22. The odd-numbered pixel electrodes 21 are connected to the left-hand source lines, and the even-numbered pixel electrodes 21 are connected to the right-hand source lines. In this point, the liquid crystal display panel 2b is the same as that of the first embodiment. Further, like in the first embodiment, the case where the active element 22 is a TFT is taken as an example.
The control section 3 outputs control signals POL1, SCLK and STB to each potential setting section 11. The output mode of POL1, SCLK and STB is the same as in the first embodiment, except in that the control signals are output to the two or more potential setting sections 11 at the same time.
Further, the control section 3 outputs POL2 to the respective switch section 12 at the same time. The output mode of POL2 is also the same as in the first embodiment, except in that POL2 is output to the two or more switch sections 12 at the same time.
Next, the operation will be described. First, a description will be made of a frame in which the control section 3 sets POL1 to high level upon selection of an odd-numbered row and sets POL1 to low level upon selection of an even-numbered row.
Upon selection of an odd-numbered row, the control section 3 sets POL1 to be output to each potential setting section 11 to high level. Therefore, each potential setting section 11 outputs potentials higher than VCOM from the odd-numbered potential output terminals D1, D3, D5, . . . from the left, and potentials lower than VCOM from the even-numbered potential output terminal D2, D4, D6, . . . from the left. At this time, the control section 3 sets POL2 to be output to each switch section 12 to high level. Thus, as shown in
As a result, the odd-numbered source lines S1, S3, S5 . . . from the left become potentials higher than VCOM, and the even-numbered source line S2, S4, S6, . . . from the left become potentials lower than VCOM. Then, each pixel electrode 21 in the selected row (odd-numbered row) is set to a potential equal to the left-hand source line.
Upon selection of an even-numbered row, the control section 3 sets POL1 to be output to each potential setting section 11 to low level. Therefore, each potential setting section 11 outputs potentials lower than VCOM from the odd-numbered potential output terminals D1, D3, D5, . . . from the left, and potentials higher than VCOM from the even-numbered potential output terminal D2, D4, D6, . . . from the left. At this time, the control section 3 sets POL2 to be output to each switch section 12 to low level. The state of each switch section 12 at this time is shown in
As a result, the odd-numbered source lines S1, S3, S5 . . . from the left become potentials higher than VCOM, and the even-numbered source line S2, S4, S6, . . . from the left become potentials lower than VCOM. Then, each pixel electrode 21 in the selected row (even-numbered row) is set to a potential equal to the right-hand source line.
Thus, in this frame, the odd-numbered source lines from the left are maintained at potentials higher than VCOM, and the even-numbered source lines from the left are maintained at potentials lower than VCOM. The polarity of each pixel in this frame is the same as shown in
Next, a description will be made of a frame in which the control section 3 sets POL1 to low level upon selection of an odd-numbered row and sets POL1 to high level upon selection of an even-numbered row.
Upon selection of an odd-numbered row, the control section 3 sets POL1 to be output to each potential setting section 11 to low level. Therefore, each potential setting section 11 outputs potentials lower than VCOM from the odd-numbered potential output terminals D1, D3, D5, . . . from the left, and potentials higher than VCOM from the even-numbered potential output terminal D2, D4, D6, . . . from the left. At this time, the control section 3 sets POL2 to be output to each switch section 12 to high level. Thus, as shown in
As a result, the odd-numbered source lines S1, S3, S5 − from the left become potentials lower than VCOM, and the even-numbered source line S2, S4, S6, . . . from the left become potentials higher than VCOM. Then, each pixel electrode 21 in the selected row (odd-numbered row) is set to a potential equal to the left-hand source line.
Upon selection of an even-numbered row, the control section 3 sets POL1 to be output to each potential setting section 11 to high level. Therefore, each potential setting section 11 outputs potentials higher than VCOM from the odd-numbered potential output terminals D1, D3, D5, . . . from the left, and potentials lower than VCOM from the even-numbered potential output terminal D2, D4, D6, . . . from the left. At this time, the control section 3 sets POL2 to be output to each switch section 12 to low level. Since POL2 is at low level, the input terminals I1 to In of each switch section 12 are electrically conducted with the output terminals O2 to On+1 as shown in
As a result, the odd-numbered source lines S3, S5, . . . from the left become potentials lower than VCOM, and the even-numbered source line S2, S4, S6, . . . from the left become potentials higher than VCOM. Then, each pixel electrode 21 in the selected row (even-numbered row) is set to a potential equal to the right-hand source line.
Thus, in this frame, the odd-numbered source lines from the left are maintained at potentials lower than VCOM, and the even-numbered source lines from the left are maintained at potentials higher than VCOM. The polarity of each pixel in this frame is the same as shown in
In the third embodiment, the operation of each of the driving devices 1a and 1b is the same as that in the first embodiment, and each source line can be maintained at a potential higher than VCOM or a potential lower than VCOM in a frame. Thus, the third embodiment has effects similar to the first embodiment.
The second embodiment may be applied to the third embodiment. In other words, it may be configured such that consecutive rows of pixel electrodes 21 are so grouped that the pixel electrodes in each row of an odd-numbered group are connected to the left-hand source lines and the pixel electrodes in each row of an even-numbered group are connected to right-hand source lines. In this case, the control section 3 may output POL1 and POL2 in the same manner as in the second embodiment.
The liquid crystal display device of the fourth embodiment includes the driving device 1, a liquid crystal display panel 2c, the control section 3 and the power supply section 4. The driving device 1 includes the potential setting section 11 and the switch section 12. The operation of the control section 3, the power supply section 4 and the driving device 1 (the potential setting section 11 and the switch section 12) is the same as in the first embodiment.
The liquid crystal display panel 2c has the same structure as that of the liquid crystal display panel 2 in the first embodiment, but the arrangement of red pixel (R), green pixel (G) and blue pixel (B) is different from the first embodiment.
Compared to the first embodiment, the liquid crystal display panel 2 in the first embodiment is such that the way of placing R, G, B is the same in any row and, if focusing on each column of pixels, the same color pixels are arrayed in units of columns (see
On the other hand, in the fourth embodiment, the arrangement of R, G, B is different among consecutive three rows. In the example of
When image data is input to the potential setting section 11 of the driving device 1, the image data may be input according to the arrangement of RGB on the liquid crystal display panel 2c. For example, data for one row may be input as data in the first row in order from data on the leftmost R pixel to data on the second G pixel from the left, data on the third B pixel from the left, . . . . As data for the second row, data for one row may be input in order from data on the leftmost G pixel to data on the second B pixel from the left, data on the third R pixel from the left, . . . . Further, as data for the third row, data for one row may be input in order from data on the leftmost B pixel to data on the second R pixel from the left, data on the third G pixel, . . . .
Note that the operation of the potential setting section 11 to capture the data for one row to be input is the same as in the first embodiment. In other words, image data corresponding to the arrangement of the liquid crystal display panel 2c has only to be prepared and input to the driving device 1. The operations of the control section 3, the driving device 1 and the power supply section 4 are the same as in the first embodiment.
Since the fourth embodiment is different from the first embodiment only in the arrangement of RGB on the liquid crystal display panel, the fourth embodiment also has effects similar to the first embodiment. Note that the arrangement of R, G and B on the liquid crystal display panel 2, is not limited to the arrangement shown in
The liquid crystal display device of the fifth embodiment includes the driving device 1, a liquid crystal display panel 2d, the control section 3 and the power supply section 4. The driving device 1 includes the potential setting section 11 and the switch section 12. The operations of the control section 3, the power supply section 4 and the driving device 1 (the potential setting section 11 and the switch section 12) are the same as in the first embodiment.
The liquid crystal display panel 2d has the same structure as that of the liquid crystal display panel 2 in the first embodiment, but the arrangement of red pixel (R), green pixel (G) and blue pixel (B) is different from the first embodiment.
The liquid crystal display panel 2d of the fifth embodiment is such that pixels in one row are of the same color. In the example shown in
When image data is input to the potential setting section 11 of the driving device 1, the image data may be input according to the arrangement of RGB on the liquid crystal display panel 2d. For example, data for one row may be input as data in the first row in order from data on the leftmost R pixel to data on the second R pixel from the left, . . . . As data for the second row, data for one row may be input in order from data on the leftmost G pixel to data on the second G pixel, . . . . Further, as data for the third row, data for one row may be input in order from data on the leftmost B pixel to data on the second B pixel from the left, . . . .
Note that the operation of the potential setting section 11 to capture the data for one row to be input is the same as in the first embodiment. In other words, image data corresponding to the arrangement of the liquid crystal display panel 2d has only to be prepared and input to the driving device 1. The operation of the control section 3, the driving device 1 and the power supply section 4 itself is the same as in the first embodiment.
Since the fifth embodiment is different from the first embodiment only in the arrangement of RGB on the liquid crystal display panel, the fifth embodiment has effects similar to the first embodiment. Note that the arrangement of R, G and B on the liquid crystal display panel 2d is not limited to the arrangement shown in
Further, in the fifth embodiment, if the number of R, G and B pixels is set equal to that in the first embodiment, the total number of source lines and gate lines can be reduced.
Further, the second embodiment or the third embodiment may be applied to the fourth embodiment and the fifth embodiment.
In each of the aforementioned first to fifth embodiments, the description has been made of the case where the potential setting section 11 captures image data for one row in response to SCLK in order from data on the leftmost pixel, the order of capturing pixel data is not limited to this order. In each embodiment, the potential setting section 11 may capture image data for one row in order from data on the rightmost pixel. Even this case has effects similar to each embodiment.
Further, in each of the aforementioned embodiments, it is preferred that output of potentials in the next frame be started after the potential setting section 11 once sets the output potential of each of the potential output terminals D1 to Dn to a potential between the maximum potential (V0 in the above example) and the minimum potential (V17 in the above example) during a vertical blanking interval. It is particularly preferred that the potential setting section 11 should set the potential of each of the potential output terminals D1 to Dn to VCOM(=(V0+V17)/2) during the vertical blanking interval. Thus, if the potentials are set during the vertical blanking interval, the load on the power supply section 4 can be reduced.
In order to set the output potential of each of the potential output terminals Di to Dn once to a potential between the maximum potential and the minimum potential, the potential setting section 11 may, for example, short-circuit between a pair of adjacent two potential output terminals. For example, potential output terminals in each pair, such as a pair of D1 and D2, a pair of D3 and D4, may be short-circuited.
Note that the vertical blanking interval is a period from when the selection of the last row is completed until the selection of the first row is started next, i.e., an interval from frame to frame.
Further, in each of the aforementioned embodiments, the case where the liquid crystal display panel is provided with R, G and B pixels to provide color display is shown, but the liquid crystal display panel may be a black-and-white liquid crystal display panel provided with black-and-white pixels, rather than R, G and B pixels.
In each of the aforementioned embodiments, a driving device for a liquid crystal display panel including the potential setting section 11 and the switch section 12 is disclosed.
In each of the aforementioned embodiments, the control section 3 or the control section 3a may be provided in the driving device 1. In other words, the driving device 1 may include the control section 3 or the control section 3a.
In each of the aforementioned embodiments, the switch section 12 may be provided on the liquid crystal display panel 2, 2a, 2b, 2c, or 2d, rather than being provided in the driving device 1. In this case, the driving device 1 has only to include the potential setting section 11. Further, in each of the aforementioned embodiments, the potential setting section 11 or the control section 3 may be a TAB substrate or COG (Chip on Glass), or be formed from polysilicon or the like.
In each of the following embodiments, a description will be made of a case where switches are included in the potential setting section.
The liquid crystal display device also includes the same gate driver (not shown) as that in the first embodiment. Since the input mode of control signals to the gate driver and the operation of the gate driver are the same as in the first embodiment, the redundant description thereof will be omitted. This holds true for the following seventh and subsequent embodiments.
The liquid crystal display panel 2b includes 2m columns of pixel electrodes, and among the columns, the left-hand m columns are driven by a first driving device and the right-hand m columns are driven by a second driving device. It is assumed that m is a multiple of 3. Like in the third embodiment, the liquid crystal display panel 2b includes source lines S1 to S2m+1 that is one more in number than the number of columns of pixel electrodes. The mode of connection of the m+l-th source line Sm+1 from the left with two voltage followers shown in
SCLK, STH and STB are input to the shift register 31 from the control section (not shown in
The first driving device includes first latch sections 32 for R, G, and B, respectively, as the first latch section 32. Each of the first latch sections 32 for R, G and B has signal input terminals L1 to Lm/3 corresponding to the signal output terminals C1 to Cm/3, respectively. Any signal output terminal Ci of the shift register 31 is connected to a signal input terminal Li in each of the first latch sections 32 for R, G and B. Thus, the shift register 31 outputs the data reading instruction signal from the signal output terminal Ci to the signal input terminals Li of the first latch sections 32 for R, G and B at the same time, respectively.
When the data reading instruction signal is input from the signal input terminal Li, the first latch section 32 for R captures the i-th R data in one line. Similarly, when the data reading instruction signal is input from the signal input terminal Li, the first latch section 32 for G captures the i-th G data in one line. When the data reading instruction signal is input from the signal input terminal Li, the first latch section 32 for B captures the i-th B data in one line. As mentioned above, since the data reading instruction signal is input to the signal input terminals Li of the first latch sections 32 for R, G and B, respectively, at the same time, each of R, G and B data is read into the first latch sections 32 in parallel. Each first latch section 32 holds the read data in order, respectively. These pieces of data are pixel values each representing the level of halftone of each pixel in one line.
The first latch sections 32 for R, G and B may be made up in an integrated fashion to capture data along the sequence of respective R, G and B data for one line.
Further, SCLK is input from the control section to the shift register 31 to provide signal output from the signal output terminals C1 to Cm/3 within one cycle of STB. Thus, during one cycle of STB, R data, G data and B data for one line are held in the first latch sections 32, respectively. These pieces of R data, G data and B data for one line are read into the second latch section 33 collectively.
Each of the above R data, G data and B data for one line is m/3 piece of data, respectively. Each first latch section 32 has m/3 output terminals L′1 to L′m/3 as terminals used for output of this m/3 piece of data.
Further, one driving device includes second latch sections 33 for R, G and B as the second latch section 33. Each of the second latch sections 33R, G and B includes data reading terminals corresponding to the output terminals L′1 to L′m/3 of the first latch section 32, respectively. Hereinafter, the data reading terminals of the second latch section 33 for R are denoted as R1 to Rm/3. Similarly, the data reading terminals for G and B are denoted as G1 to Gm/3 and B1 to Bm/3, respectively.
Further, the second latch section 33 for R includes data output terminals R′1 to R′m/3 corresponding to the data reading terminals R1 to Rm/3. The second latch section 33 for R outputs, from data output terminal R′i, data read from any data reading terminal Ri. The same holds true for the second latch sections 33 for G and B.
The timing at which each second latch section 33 reads data from the first latch section 32 and outputs the data is determined by STB. For example, the second latch section 33 for R may read R data for one line (m/3 piece of data) collectively at predetermined timing (e.g., on the falling edge of STB or the like) in each cycle of STB, and output the data from each of the data output terminals R1 to Rm/3. The same holds true for the second latch sections 33 for G and B. The control section outputs STB to the shift register 31, each second latch section 33 and the DA converter 36.
The second latch sections 33 for R, G and B may be made up in an integrated fashion to capture data along the sequence of respective R, G and B data for one line.
The switch section 34 has the same structure as the switch 12 in the first embodiment. In the example of
POL2 may be generated by the control section and input to the switch section 34. Alternatively, as described as the modification of the first embodiment, the potential setting section of the driving device may generate POL2. For example, means for generating POL2 may be provided in the potential setting section. In this case, the control section outputs STV to notify the driving device of the start time of a frame. In either case, POL2 is generated to become high level during the selection period of the first row in each frame.
The i-th data output terminal Ri of the second latch section 33 for R is connected to the input terminal I3·i−2 of the switch section 34. The i-th data output terminal Gi of the second latch section 33 for G is connected to the input terminal I3·i−1 of the switch section 34. The data output terminal Bi of the second latch section 33 for B is connected to the input terminal I3·i of the switch section 34. Thus, when POL2 is at high level, the switch section 34 outputs respective data from the output terminals O1 to Om in the following order: R, G, B, R, G, B, . . . . On the other hand, when POL1 is at low level, the switch section 34 outputs respective data from the output terminals O2 to Om+1 in the following order: R, G, B, R, G, B, . . . .
The level shifter 35 has m+1 data input terminals U1 to Um+1 and m+1 data output terminals U′1 to Each of the data input terminals U1 to Um+1 is connected to each of the output terminals O1 to Om+1 of the switch section 34 in a one-to-one relationship. The level shifter 35 shifts the level of data input to each of the data input terminals U1 to Um+1, and outputs data after subjected to level shifting from U′1 to U′m+1. For example, when the output data of the second latch section 33 is in a low voltage system (e.g., 3V system), the level shifter 35 shifts the level of the data input through the switch section 34 to a high voltage system (e.g., 15V system), and outputs the data from the data output terminals, respectively.
The DA converter 36 has m+1 data input terminals T1 to Tm+1 and m+1 potential output terminals T′1 to Tm+1. Each of the data input terminals T1 to Tm+1 is connected to the data output terminals U′1 to U′m+1 of the level shifter 35 in a one-to-one relationship. The DA converter 36 coverts data input from each of the data input terminals T1 to Tm+1 to an analog voltage, and outputs the analog voltage from each of the potential output terminals T′1 to T′m+1. Further, each voltage of V0-V8 and V9-V17 is supplied from a power supply (not shown in
POL1 is input from the control section to the DA converter 36. The DA converter 36 switches the output potential of each of the potential output terminals T′1 to T′m+1 between a potential higher than VCOM and a potential lower than VCOM depending on whether POL1 is at high level or low level. Specifically, when POL1 is at high level, the DA converter 36 sets the output potentials of the odd-numbered potential output terminals T′1, T′3, m from the left to potentials higher than VCOM, and the output potentials of the even-numbered potential output terminals T′2, T′4, . . . from the left to potentials lower than VCOM. On the other hand, when POL1 is at low level, the DA converter 36 sets the output potentials of the odd-numbered potential output terminals T′1, T′3, . . . from the left to potentials lower than VCOM, and the output potentials of the even-numbered potential output terminals T′2, T′4, . . . from the left to potentials higher than VCOM.
In other words, when POL1 is at high level, any one of potentials V0-V8 or the like is output from each of the odd-numbered potential output terminals T′1, T′3, . . . , and any one of potentials V9-V17 or the like is output from the even-numbered potential output terminals T′2, T′4, . . . . On the other hand, when POL1 is at low level, any one of potentials V9-V17 or the like is output from each of the odd-numbered potential output terminals T′1, T′3, . . . , and any one of potentials V0-V8 or the like is output from the even-numbered potential output terminals T′2, T′4, . . . .
In the embodiment, the control section switches POL1 between high level and low level alternately on a frame-by-frame basis. As a result, the output potential from each of the potential output terminals in the DA converter 36 is maintained at a potential higher than VCOM or a potential lower than VCOM during one frame. Therefore, the potential of each source line is also maintained at a potential higher than VCOM or a potential lower than VCOM during one frame.
Note that POL1 may be input to the second latch section 33. In such a case, however, the operation of the second latch section 33 is not affected by POL1.
The voltage follower 37 has potential input terminals (not shown in
Next, the operation will be described.
First, a frame in which POL1 is at high level will be described. In this frame, any input terminal Ii of the switch section 34 is connected to the output terminal Oi during period A where POL2 is at high level (e.g., during the selection period of the first row). Therefore, the switch section 34 outputs each data from the output terminals O1 to Om in the following order: R, G, B, R, G, B, . . . . The data is data output from each second latch section 33 according to the R data, G data and B data for one line, respectively. The following takes the selection period of the first row by way of example to describe the operation during period A.
The level shifter 35 receives, at the data input terminals U1 to Um, each data output from the output terminal O1 to Om of the switch section 34. Then, the level shifter 35 shifts the level of each data received at the data input terminals U1 to Um, respectively, and inputs the data to the data input terminals T1 to Tm of the DA converter 36.
Since POL1 is at high level, the DA converter 36 converts the data input to each of the odd-numbered potential output terminals T1, T3, . . . from the left into an analog voltage (V0-V8 or the like) higher than VCOM, respectively, and outputs the analog voltage from each of the potential output terminals T′1, T′3, . . . from the left. Further, the DA converter 36 converts the data input to each of the even-numbered data input terminals T2, T4, . . . from the left into an analog voltage (V9-V17 or the like) lower than VCOM, respectively, and outputs the analog voltage from each of the potential output terminals T′2, T′4, . . . from the left. The voltage follower 37 outputs the potentials output from T′1 to T′m from the potential output terminals V1 to Vm, respectively.
Since the output terminal Om+1 is not connected to the input terminal Im in the switch section 34, there is no significant output from Vm+1 in each voltage follower 37.
Each pixel electrode in the first row is set to a potential equal to the source line arranged on the left side of the pixel electrode during the selection period of the first row. As a result, the polarity of each pixel in the first row is positive, negative, positive, negative, . . . in this order from the left as shown in
Further, during period B where POL2 becomes low level in the frame in which POL1 is at high level (e.g., the selection period of the second row), any input terminal Ii of the switch section 34 is connected to the output terminal Oi+1. Therefore, the switch section 34 outputs each data from the output terminals O2 to Om+1 in the following order: R, G, B, R, G, B, . . . . This data is data output from each second latch section 33 according to the R data, G data and B data for one line, respectively. The following takes the selection period of the second row by way of example to describe the operation during period B.
The level shifter 35 receives, at the data input terminals U2 to Um+1 each of data output from the output terminals O2 to Om+1 of the switch section 34. Then, the level shifter 35 shifts the level of each data received at the data input terminals U2 to Um+1, respectively, and inputs the data to the data input terminals T2 to Tm+1 of the DA converter 36.
Since POL1 is at high level, the DA converter 36 converts the data input to each of the even-numbered data input terminals T2, T4, . . . from the left into an analog voltage (V9-V17 or the like) lower than VCOM, respectively, and outputs the analog voltage from each of the potential output terminals T′2, T′4, . . . from the left. Further, the DA converter 36 converts the data input to each of the odd-numbered potential output terminals T1, T3, . . . from the left into an analog voltage (V0-V8 or the like) higher than VCOM, respectively, and outputs the analog voltage from each of the potential output terminals T′1, T′3, . . . from the left. The voltage follower 37 outputs the potentials output from T′2 to T′m+1 from the potential output terminals V2 to Vm+1, respectively.
Since the output terminal O1 is not connected to the input terminal I1, there is no significant output from V1 in each voltage follower 37.
Each pixel electrode in the second row is set to a potential equal to the source line arranged on the right side of the pixel electrode during the selection period of the second row. As a result, the polarity of each pixel in the second row is negative, positive, negative, positive, . . . in this order from the left as shown in
After that, the operations for periods A and B are repeated in this frame. As a result, the polar state of each pixel in this frame is as shown in
Next, a frame in which POL1 is at low level will be described. In this frame, the operation of the switch section 34 and the level shifter 35 during period C where POL2 becomes high level (e.g., during the selection period of the first row) is the same as that that for period A. The following takes the selection period of the first row by way of example to describe the operation during period C.
Since POL1 is at low level during period C, the DA converter 36 converts the data input to each of the odd-numbered data input terminals T1, T3, . . . from the left into an analog voltage (V9-V17 or the like) lower than VCOM, respectively, and outputs the analog voltage from each of the potential output terminals T′1, T′3, . . . from the left. Further, the DA converter 36 converts the data input to each of the even-numbered data input terminals T2, T4, . . . from the left into an analog voltage (V0-V8 or the like) higher than VCOM, respectively, and outputs the analog voltage from each of the potential output terminals T′2, T′4, . . . from the left. The voltage follower 37 outputs the potentials output from T′1 to T′m from the potential output terminals V1 to Vm, respectively. Note that there is no significant output from Vm+1 in the each voltage follower 37 during period C. This is the same as period A. Here, High-z may be set as the insignificant output.
Each pixel electrode in the first row is set to a potential equal to the source line arranged on the left side of the pixel electrode during the selection period of the first row. As a result, the polarity of each pixel in the first row is negative, positive, negative, positive, . . . in this order from the left.
Further, during period D where POL1 becomes low level in the frame in which POL1 is at low level (e.g., the selection period of the second row), the operation of the switch section 34 and the level shifter 35 is the same as that for period B. The following takes the selection period of the second row by way of example to describe period D.
Since POL1 is at low level during period D, the DA converter 36 converts the data input to each of the even-numbered data input terminals T2, T4, . . . from the left into an analog voltage (V0-V8 or the like) higher than VCOM, respectively, and outputs the analog voltage from each of the potential output terminals T′2, T′4, from the left. Further, the DA converter 36 converts the data input to each of the odd-numbered potential output terminals T3, T5, from the left into an analog voltage (V9-V17 or the like) lower than VCOM, respectively, and outputs the analog voltage from each of the potential output terminals T′3, T′5, The voltage follower 37 outputs the potentials output from T′2 to from the potential output terminals V2 to Vm+1, respectively. Note that there is no significant output from V1 in each voltage follower 37 during period D. This is the same as period B. Here, High-z may be set as the insignificant output.
Each pixel electrode in the second row is set to a potential equal to the source line arranged on the right side of the pixel electrode during the selection period of the second row. As a result, the polarity of each pixel in the second row is positive, negative, positive, negative, from the left.
After that, the operations for periods C and D are repeated in this frame. As a result, the polar state of each pixel in this frame is as shown in
In the sixth embodiment, a potential corresponding to data on each pixel can also be output to each source line without changing the sequence of R, G and B data for one row input in parallel. In the other points, the sixth embodiment has effects similar to the first embodiment, the third embodiment, and so on.
In the embodiment, since the switch section 34 is provided on the upstream side of the voltage follower 36, there is no limitation that the level of POL2 must be switched while the output of the potential setting section is in the high impedance state. This point holds true for the seventh and subsequent embodiments. The following gives a brief description of the mode of connection between the first driving device and the second driving device. When POL2 is at high level relative to the switch section 34, the switches are thrown to the left (indicated by the solid line in
Next, a modification of the sixth embodiment will be described.
Like in the third embodiment,
Further, like in the second embodiment, two or more consecutive gate lines may be grouped. In this case, the structure of the liquid crystal panel may be made similar to the structure of the liquid crystal panel 2a in the second embodiment (see
The liquid crystal panel 2b is the same as that in the sixth embodiment.
The shift register 31, the first latch section 32 and the second latch section 33 are also the same as those in the sixth embodiment, except in that the second latch section 33 is connected to the level shifter 45.
In the embodiment, one driving device includes level shifters 45 for R, G and B as the level shifter 45. Each of the level shifters 45 for R, G and B has m/3 data input terminals and data output terminals, respectively. The data input terminals contained in the level shifter 45 for R are denoted as UR1 to URm/3. The data output terminals contained in the level shifter 45 for R are denoted as UR′1 to UR′m/3. Similarly, the data input terminals contained in the level shifter 45 for G are denoted as UG1 to UGm/3. Then, the data output terminals contained in the level shifter 45 for G are denoted as UG′1 to UG′m/3. Further, the data input terminals contained in the level shifter 45 for B are denoted as UB1 to UBm/3. The data output terminals contained in the level shifter 45 for B are denoted as UB′1 to UB′m/3.
Each of the data input terminal UR1 to URm/3 of the level shifter 45 for R is connected to each of the data output terminal R′1 to R′m/3 of the second latch section 33 for R. Then, the level shifter 45 for R shifts the level of data input to each of the data input terminals UR1 to URm/3 and outputs the data after subjected to level shifting from each of the data output terminals UR′1 to UR′m/3.
Each of the data input terminals UG1 to UGm/3 of the level shifter 45 for G is connected to each of the data output terminals G′1 to G′m/3 of the second latch section 33 for G. Each of the data input terminal UB1 to UBm/3 of the level shifter 45 for B is connected to each of the data output terminals B′1 to B′m/3 of the second latch section 33 for B. Like the level shifter 45 for R, each of the level shifters 45 for G and B shift the level of input data and outputs the data after subjected to level shifting from each of the data output terminals.
The level shifters 45 for R, G and B may be made up in an integrated fashion so that each data will be input along the sequence of respective R, G and B data for one row.
The structure of the switch section 34 is the same as the switch section 34 in the sixth embodiment, except in the following points: The i-th data output terminal UR′i in the level shifter 45 for R in the seventh embodiment is connected to the input terminal of the switch section 34. The i-th data output terminal UG′i in the level shifter 45 for G is connected to the input terminal I3·i−1 of the switch section 34. The i-th data output terminal UB′i in the level shifter 45 for B is connected to the input terminal I3·i of the switch section 34. Thus, when POL2 is at high level, the switch section 34 outputs respective data (data after subjected to level shifting) from the output terminals O1 to Om in the following order: R, G, B, R, G, B, . . . . On the other hand, when POL2 is at low level, the switch section 34 outputs respective data (data after subjected to level shifting) from the output terminals O2 to Om+1 in the following order: R, G, B, R, G, B, . . . .
The DA converter 36 and the voltage follower 37 are the same as in the sixth embodiment, except in that each of the data input terminals T1 to Tm+1 of the DA converter 36 is connected to each of the output terminals O1 to Om+1 of the switch section 34 in a one-to-one relationship.
Further, like in the sixth embodiment, the control section (not shown in
As for POL2, like in the sixth embodiment, the control section may generate and input POL2 to the switch section 34, or POL2 may be generated inside the driving device. In either case, POL2 is generated to become high level during the selection period of the first row in each frame. This is also the same as in the sixth embodiment.
The other control signals generated by the control section are the same as those in the sixth embodiment.
A comparison of the structure in the seventh embodiment with that in the sixth embodiment shows that in the seventh embodiment, the level shifter 45 is provided upstream of the switch section 34, and the level shifters 45 for R, G and B are provided. The mode of connection between each level shifter 45 and each input terminal of the switch is as already described above.
According to such a structure, data input to the DA converter 36 is the same as in the sixth embodiment. In other words, when POL2 is at high level, R data, G data and B data for one line after subjected to level shifting are input to the data input terminals T1 to Tm of the DA converter 36. On the other hand, when POL2 is at low level, R data, G data and B data for one line after subjected to level shifting are input to the data input terminals T2 to Tm+1.
The variations in POL2 input to the switch section 34 and variations in POL1 input to the DA converter 36 are the same as in the sixth embodiment (see
This embodiment also has effects similar to the sixth embodiment.
The modification of the sixth embodiment can also be applied to the seventh embodiment. In other words, the case where the two or more driving devices are connected to the liquid crystal display panel 2b like in the third embodiment is illustrated in
Further, like in the second embodiment, two or more consecutive gate lines may be grouped. In this case, the structure of the liquid crystal panel may be made similar to the structure of the liquid crystal panel 2a in the second embodiment (see
The liquid crystal panel 2b has the same structure as that in the sixth embodiment.
The shift register 31, the first latch section 32 and the second latch section 33 are also the same as those in the sixth embodiment. Further, the level shifter 45 is the same as in the seventh embodiment, and the mode of connections between the second latch sections 33 and the level shifters 45, both of which are for R, G and B, respectively, is the same as in the seventh embodiment, except in that the level shifter 45 is connected to the DA converter 46 in the eighth embodiment.
The DA converter 46 is the same as that in the sixth and seventh embodiments, except in that the number of data input terminals and the number of potential output terminals are m, respectively. The DA converter 46 converts data input from each of the level shifter 45 to the data input terminals T1 to Tm into an analog voltage, and outputs the analog voltage from each of the potential output terminals T′1 to T′m.
When input POL1 is at high level, the DA converter 46 sets the output potentials of the odd-numbered potential output terminals T′1, T′3, . . . from the left to potentials higher than VCOM, and sets the output potentials of the even-numbered potential output terminals T′2, T′4, . . . from the left to potentials lower than VCOM. On the other hand, when POL1 is at low level, the DA converter 36 sets the output potentials of the odd-numbered potential output terminal T′1, T′3, . . . from the left to potentials lower than VCOM, and sets the output potentials of the even-numbered potential output terminals T′2, T′4, . . . from the left to potentials higher than VCOM.
Here, POL1 input to the DA converter 36 will be described. In the sixth and seventh embodiments, the level of POL1 is switched on a frame-by-frame basis. On the other hand, in this embodiment, the control section (not shown in
In this embodiment, the i-th data output terminal UR′i in the level shifter 45 for R is connected to the data input terminal T3·i−2 of the DA converter 46. The i-th data output terminal UG′i in the level shifter 45 for G is connected to the data input terminal T3·i−1 of the DA converter 46. The i-th data output terminal UB′i in the level shifter 45 for B is connected to the data input terminal T3·i of the DA converter 46.
The structure of the switch section 34 is the same as the switch section 34 in the sixth and seventh embodiments, except in that in this embodiment, the switch section 34 is provided downstream of the DA converter 46, and each of the input terminals I1 to Im of the switch section 34 is connected to each of the potential output terminals T′1 to T′m of the DA converter 46 in a one-to-one relationship.
Therefore, when POL2 is at high level, the switch section 34 outputs, from each of the output terminals O1 to Om of the switch section 34, the potential output from each of the potential output terminals T′1 to T′m of the DA converter. On the other hand, when POL2 is at low level, the switch section 34 outputs, from each of the output terminals O2 to Om+1, the potential output from each of the potential output terminal T′1 to T′m of the DA converter.
As for POL2, like in the sixth and seventh embodiments, the control section may generate and input POL2 to the switch section 34, or POL2 may be generated inside the driving device. In either case, POL2 is generated to become high level during the selection period of the first row in each frame. This is also the same as in the sixth and seventh embodiments.
Output is taken from each of the output terminals O1 to Om+1 of the switch section 34 to each of m+1 potential input terminals (denoted as W1 to Wm+1) of the voltage follower 37 in one-to-one relationship. The voltage follower 37 is the same as that in the sixth and seventh embodiments, and outputs, from each of the potential output terminal V1 to Vm+1, a potential equal to the potential input to each of the potential input terminals W1 to Wm+1, respectively.
Next, the operation will be described.
In the eighth embodiment, a period where both POL1 and POL2 are at high level is denoted as “E.” A period where both POL1 and POL2 are at low level is denoted as “F.” A period where POL1 is at low level and POL2 is at high level is denoted as “G.” A period where POL1 is at high level and POL2 is at low level is denoted as “H.”
First, frame F1 in which periods E and F alternate will be described. The following takes the selection period of the first row by way of example to describe period E. During period E, the second latch section 33 for R reads R data for one row from the first latch section 32 for R, and inputs each data to the level shifter 45 for R, respectively. The second latch sections 33 for G and B operate the same way.
The level shifter 45 for R shifts the level of input data, and inputs each data after subjected to level shifting to each of the data input terminals T1, T4, . . . , Tm−2 of the DA converter 46. The level shifter 45 for G also shifts the level of input data, and inputs each data after subjected to level shifting to each of the data input terminals T2, T5, . . . , Tm−1 of the DA converter 46. The level shifter 45 for B also shifts the level of input data, and inputs each data after subjected to level shifting to each of the data input terminals T3, T6, . . . , Tm of the DA converter 46. As a result, each data (data after subjected to level shifting) for one row is input from the left-hand data input terminals to the DA converter 46 in the following order: R, G, B, R, G, B, . . . . The DA converter 46 converts this data to an analog voltage V0-V8 or the like, or V9-V17 or the like, and outputs the analog voltage from each of the potential output terminals T′1 to T′m.
Since POL1 is at high level during period E, the DA converter 46 outputs a potential (V0-V8 or the like) higher than VCOM from each of the odd-numbered potential output terminals T′1, T′3, . . . from the left, and outputs a potential (V9-V17 or the like) lower than VCOM from each of the even-numbered potential output terminal T′2, T′4, . . . from the left.
Since POL2 is at high level, the input terminal Ii of the switch section 34 is connected to the output terminal Oi. Therefore, the potentials output from the potential output terminals T′1 to T′m of the DA converter 46 are output from the output terminals O1 to Om of the switch section 34, and further output from the potential output terminals V1 to Vm of the voltage follower 37.
As a result, in each voltage follower 37, potentials higher than VCOM are output from the odd-numbered potential output terminals V1, V3, . . . from the left and potentials lower than VCOM are output from the even-numbered potential output terminals V2, V4, . . . from the left. Then, the odd-numbered source lines S1, S3, . . . from the left are set to potentials higher than VCOM, and the even-numbered source lines S2, S4, . . . from the left are set to potentials lower than VCOM. Since the output terminal Om+1 is not connected to the input terminal Im in the switch section 34, there is no output from Vm+1 in each voltage follower 37.
Each pixel electrode in the first row is set to a potential equal to the source line arranged on the left side of the pixel electrode during the selection period of the first row. As a result, the polarity of each pixel in the first row is positive, negative, positive, negative, in this order from the left.
Next, the selection period of the second row is taken by way of example to describe period F. During period F, the operation until data for one row (data after subjected to level shifting) are input to the DA converter 46 is the same as that for period E.
Since POL1 is at low level during period F, the DA converter 46 outputs a potential (V9-V17 or the like) lower than VCOM from each of the odd-numbered potential output terminals T′1, T′3, from the left, and outputs a potential (V0-V8 or the like) higher than VCOM from each of the even-numbered potential output terminals T′2, T′4, . . . from the left.
Further, since POL1 is at low level, the input terminal Ii of the switch section 34 is connected to the output terminal Oi+1. Therefore, the potentials output from the potential output terminals T′1 to T′m of the DA converter 46 are output from the output terminals O2 to Om+1 of the switch section 34, and further output from the potential output terminal V2 to Vm+1 of the voltage follower 37.
As a result, in each voltage follower 37, potentials lower than VCOM are output from the even-numbered potential output terminals V2, V4, . . . from the left and potentials higher than VCOM are output from the odd-numbered potential output terminals V3, V5, . . . from the left. Then, the even-numbered source lines S2, S4, . . . from the left are set to potentials lower than VCOM, and the odd-numbered source lines S3, S5, . . . from the left are set to potentials higher than VCOM. Since the output terminal O1 is not connected to the input terminal I1 in the switch section 34, there is no input from V1 in each voltage follower 37.
Each pixel electrode in the second row is set to a potential equal to the potential of the source line arranged on the right side of the pixel electrode during the selection period of the second row. As a result, the polarity of each pixel in the second row is negative, positive, negative, positive, . . . in this order from the left as shown in
After that, in this frame F1, the operations for periods E and F are repeated. As a result, the polar state of each pixel in this frame F1 becomes the same as shown in
Next, frame F2 in which periods G and H alternate will be described. The following takes the selection period of the first row by way of example to describe period G. The operation until data for one row (data after subjected to level shifting) are input to the DA converter 46 is the same as that for periods E and F mentioned above.
Since POL1 is at low level during period G, the DA converter 46 outputs a potential lower than VCOM from each of the odd-numbered potential output terminals T′1, T′3, . . . from the left, and outputs a potential higher than VCOM from each of the even-numbered potential output terminal T′2, T′4, . . . from the left.
Further, since POL2 is at high level, the input terminal Ii of the switch section 34 is connected to the output terminal Oi. Therefore, the potentials output from the potential output terminals T′1 to T′m of the DA converter 46 are output from the output terminals O1 to Om of the switch section 34, and further output from the potential output terminals V1 to Vm of the voltage follower 37.
As a result, in each voltage follower 37, potentials lower than \Tam are output from the odd-numbered potential output terminals V1, V3, . . . from the left and potentials higher than VCOM are output from the even-numbered potential output terminals V2, V4, . . . from the left. Then, the odd-numbered source lines S1, S3, . . . from the left are set to potentials lower than VCOM, and the even-numbered source lines S2, S4, . . . from the left are set to potentials higher than VCOM. Since the output terminal Om+1 is not connected to the input terminal Im in the switch section 34, there is no output from the potential output terminal Vm+1 in each voltage follower 37.
Then, each pixel electrode in the first row is set to a potential equal to the source line arranged on the left side of the pixel electrode. As a result, the polarity of each pixel in the first row is negative, positive, negative, positive, . . . in this order from the left.
Next, the selection period of the second row is taken by way of example to describe period H. The operation until data for one row (data after subjected to level shifting) are input to the DA converter 46 is the same as that for periods E, F and G.
Since POLL is at high level during period H, the DA converter 46 outputs a potential higher than VCOM from each of the odd-numbered potential output terminals T′1, T′3, . . . from the left, and outputs a potential lower than VCOM from each of the even-numbered potential output terminals T′2, T′4, . . . from the left.
Further, since POL2 is at low level, the input terminal Ii of the switch section 34 is connected to the output terminal Oi+1. Therefore, the potentials output from the potential output terminals T′1 to T′m of the DA converter 46 are output from the output terminals O2 to Om+1 of the switch section 34, and further output from the potential output terminal V2 to Vm+1 of the voltage follower 37.
As a result, in each voltage follower 37, potentials higher than VCOM are output from the even-numbered potential output terminals V2, V4, . . . from the left and potentials lower than VCOM are output from the odd-numbered potential output terminals V3, V5, . . . from the left. Then, the even-numbered source lines S2, S4, . . . from the left are set to potentials higher than VCOM, and the odd-numbered source lines S3, S5, . . . from the left are set to potentials lower than VCOM. Since the output terminal O1 is not connected to the input terminal I1 in the switch section 34, there is no input from the potential output terminal V1 in each voltage follower 37.
Then, each pixel electrode in the second row is set to a potential equal to the potential of the source line arranged on the right side of the pixel electrode. As a result, the polarity of each pixel in the second row is positive, negative, positive, negative, . . . in this order from the left.
After that, in this frame F2, the operations for periods G and H are repeated. As a result, the polar state of each pixel in this frame F2 becomes the same as shown in
This embodiment also has effects similar to the sixth embodiment.
The modification of the sixth embodiment can also be applied to the eighth embodiment. When two or more consecutive gate lines are grouped, the structure of the liquid crystal panel may be made similar to the structure of the liquid crystal panel 2a (see
The first latch section 63 has a structure in which the first latch sections 32 for R, G and B in the sixth embodiment and the like are integrated. The first latch section 63 captures each data along the sequence of R, G and B data for one row.
Specifically, the first latch section 63 has m latch circuits 61 each of which captures data for one pixel. The 3·i−2-th latch circuit 61 from the left captures R data. The 3·i−1-th latch circuit 61 from the left captures G data. The 3·i-th latch circuit 61 from the left captures B data.
Each latch circuit 61 includes a signal input terminal LS to which the data reading instruction signal is input from the shift register 31, a terminal D for reading data, and a terminal Q used by the second latch section 43 to read data. When the data reading instruction signal is input to the terminal LS, each latch circuit 61 reads data for one pixel from the terminal D.
The shift register 31 is the same as the shift register in the sixth embodiment. In other words, the shift register 31 outputs the data reading instruction signal from the signal output terminals C1, C2, . . . , Cm/3 in this order each time SCLK is input. In this embodiment, any signal output terminal Ci is connected to the 3·i−2 th, 3·i−1-th and 3·i-th latch circuits 61 in the first latch section 63. Therefore, when the shift register 31 outputs the data reading instruction signal from one signal output terminal, R, G and B data are read into three latch circuits in parallel, respectively. For example, the signal output terminal C1 is connected to each of the first to third latch circuit 61 from the left, respectively. Thus, when the signal is output to the signal output terminal C1, the first to third latch circuits 61 from the left read R, G and B data, each for one pixel, respectively.
The second latch section 43 captures data for one row collectively along the sequence of R, G and B data for one row. The second latch section 43 includes latch circuits 62, each of which captures and outputs data for one pixel. Note that the second latch section 43 has the latch circuits 62 that is one more in number than the number of columns, m, of pixels to be driven by the driving device. Each of the latch circuits 62 of the second latch section 43 has a terminal LS to which STB is input from the control section (not shown in
The switch section 34 is the same as the switch section 34 in the sixth embodiment. Any input terminal Ii of the switch section 34 is connected to the terminal Q of the i-th latch circuit 61 from the left in the first latch section 63. Further, any output terminal Oi of the switch section 34 is connected to the terminal D of the i-th latch circuit 62 from the left in the first latch section 43.
Thus, when POL2 input to the switch section 34 is at high level, the m latch circuits 62 numbered from the first to m-th latch circuit from the left in the second latch section 43 captures data for one row from the first latch section 63 through the switch section 34, and outputs the captured data from the terminals Q, respectively. On the other hand, when POL2 is at low level, the m latch circuits 62 numbered from the second to m+1-th latch circuit from the left in the second latch section 43 capture data for one row from the first latch section 63 through the switch section 34, and output the captured data from the terminals Q.
The level shifter 35, the DA converter 36, the voltage follower 37 and the liquid crystal display panel 2b are the same as those in the sixth embodiment. The mode of connections of these components 35, 36, 37 and 2b is also the same as in the sixth embodiment.
However, note that any data input terminal Ui of the level shifter 35 is connected to the terminal Q of the i-th latch circuit 62 from the left in the second latch section 43.
Further, the mode of outputting the control signals from the control section (not shown in
Next, the operation will be described.
First, a frame in which periods A and B (see
Since POL2 is at high level and there is no output from the output terminal Om+1 of the switch section 34, there is no input and output to and from the m+1 terminals in the level shifter 35, the DA converter 36 and the voltage follower 37.
The data output from the m latch circuits 62 numbered from the first to m-th latch circuit from the left in the second latch section 43 are input to the data input terminals U1 to Um of the level shifter 35, respectively. Further, POL1 input to the DA converter 36 during period A is at high level. Thus, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as the operation for period A described in the sixth embodiment. As a result, the polarity of each pixel during period A in this embodiment is the same as that during period A in the sixth embodiment.
Further, since POL2 becomes low level during period B, any input terminal Ii of the switch section 34 is connected to the output terminal Oi+1. Therefore, the m latch circuits 62 numbered from the second to m+l-th latch circuit from the left in the second latch section 43 read data for one row from the first latch section 63 through the switch section 34, and output respective data. In this case, there is no input and output to and from the leftmost terminal in the level shifter 35, DA converter 36 and voltage follower 37, respectively.
The data output from the m latch circuits 62 numbered from the second to m+1-th latch circuit from the left in the second latch section 43 are input to the data input terminals U2 to Um+1 in the level shifter 35. Further, POL1 input to the DA converter 36 during period B is at high level. Thus, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as the operation for period B described in the sixth embodiment. As a result, the polarity of each pixel during period B in this embodiment is the same as that during period A in the sixth embodiment.
After that, the operations for periods A and B are repeated in this frame.
Next, a frame in which period C and D (see
Further, since POL2 is at low level during period D, the state of the switch section 34 and the mode of outputting data from the second latch section 43 are the same as those for period B mentioned above. Therefore, the data output from the second latch section 43 are input to the data input terminals U2 to Um+1 in the level shifter 35. Further, POL1 input to the DA converter 36 during period D is at low level. Thus, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as the operation for period D described in the sixth embodiment. As a result, the polarity of each pixel during period D in this embodiment is the same as that during period D in the sixth embodiment.
After that, the operations for periods C and D are repeated in this frame.
The above operation allows even this embodiment to have effects similar to the sixth embodiment.
Further, each modification of the sixth embodiment can also be applied to the ninth embodiment.
The first latch section 66 has m+1 latch circuits 61, each of which captures data for one pixel. The first latch section 66 is the same as the first latch section 63 (see
The second latch section 43 is the same as the second latch section 43 (see
The output of shift register switching section 65 connects each signal output terminal Ci of the shift register with each of the terminals LS of the latch circuits 61 in the first latch section 66. Note that POL2 is input to the output of shift register switching section 65. Then, the output of shift register switching section 65 switches the connection sate depending on whether POL2 is at high level or low level.
In the first latch section 66, the terminal LS of the j-th latch circuit 61 from the left is denoted as LSj. The output of shift register switching section 65 always connects the signal output terminal Ci of the shift register 31 to the terminals LS3·i−1 and LS3·i. Then, when POL2 is at high level, it connects the signal output terminal Ci to the terminal LS3·i−2, while when POL2 is at low level, it connects the signal output terminal Ci to LS3·i+1. In other words, when POL2 is at high level, the signal output terminal Ci of the shift register 31 is connected to three terminals LS3·i−2, LS3·i−1 and LS3·i. On the other hand, when POL2 is at low level, the signal output terminal Ci is connected to three terminals LS3·i−1, LS3·i and LS3·i+1.
For example, if POL2 is at high level, the signal output terminal C1 of the shift register 31 is connected to three terminals LS1, LS2 and LS3, while if POL2 is at low level, it is connected to three terminals LS2, LS3 and LS4. The same holds true for the other signal output terminals of the shift register 31.
It is assumed that each signal output terminal Ci of the shift register 31 is connected to three terminals LS3·i−2, LS3·i−1 and LS3·1 until POL2 is input after the liquid crystal display device is turned on. After that, when POL2 is input, the output of shift register switching section 65 operates in accordance with POL2.
The switch section 34 is the same as the switch section 34 in the sixth embodiment, having m input terminals I1 to Im and m+1 output terminals O1 to Om+1. Among input terminals, the terminals I3·i−2 (specifically, I4, I7 . . . ) are connected to data wiring 71 for R used to transfer R data. Similarly, among the input terminals, the terminals I3·i−1 (specifically, I2, I5, I8 . . . ) are connected to data wiring 72 for G used to transfer G data. Further, among the input terminals, I3·i (specifically, I3, I6, I9 . . . ) B are connected to data wiring 73 for B used to transfer B data.
Further, each of the output terminals O1 to Om+1 of the switch section 34 is connected to each terminal D of the m+1 latch circuits in the first latch section 66 in a one-to-one relationship.
In the tenth embodiment, it is assumed that the switch section 34 continues to connect the input terminal Ii to the output terminal Oi until POL2 is input after the liquid crystal display device is turned on. After that, when POL2 is input, the switch section 34 operates in accordance with POL2.
The level shifter 35, the DA converter 36, the voltage follower 37 and the liquid crystal display panel 2b are the same as those in the sixth and ninth embodiments. The mode of connections of these components 35, 36, 37 and 2b is also the same as in the sixth and ninth embodiments. Further, the mode of connection between the second latch section 43 and the level shifter 35 is the same as that in the ninth embodiment.
The control section (not shown in
Further, in each of the second and subsequent frames, the control section (or the driving device) sets POL2 to high level upon the first selection period, and switched the level of POL2 alternately per cycle of STB in the frame. In each of the second and subsequent frames, POL2 is set to high level at the time of starting the frame regardless of whether POL2 before the start of the frame is at high level or low level, and after that, the level of POL2 is switched per cycle of STB.
Next, the operation will be described.
First, the operation at power-on will be described. After power-on, the output of shift register switching section 65 continues to connect the each signal output terminal Ci of the shift register 31 to the terminals LS3·i−2, LS3·i−1 and LS3·i. Further, the switch section 34 continues to connect each input terminal Ii to each output terminal O1. In this sate, when a frame is started, the shift register 31 outputs the data reading instruction signal in response to SCLK from the signal output terminals C1, C2, . . . in this order. Since the output of shift register switching section 65 and the switch section 34 are in the above-mentioned state, the first latch section 66 reads R, G and B data in parallel sequentially for each of the three latch circuits from the left. At this time, the m+1-th latch circuit 61 of the first latch section 66 reads no data.
After that, when the generation of STB is started, the first to m-th latch circuits 62 from the left in the second latch section 43 reads data for one row collectively from the first latch section 66, and inputs each data to the data input terminal U1 to Um of the level shifter 35. After that, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as that in the sixth and ninth embodiments. The operation of the DA converter 36 depends on the level of POL1 input. The above operation is referred to as the first operation.
It is assumed that POL2 is also generated together with the generation of STB, and low-level POL2 is input to the output of shift register switching section 65 and the switch section 34. As a result, the output of shift register switching section 65 switches to a state in which each signal output terminal Ci of the shift register 31 is connected to the terminals LS3·i−1, LS3·i and LS3·i+1. Further, the switch section 34 switches to a state in which each input terminal Ii is connected to the output terminal Oi+1.
The shift register 31 outputs the data reading instruction signal in response to SCLK from the signal output terminals C1, C2, . . . in this order. Since the output of shift register switching section 65 and the switch section 34 are in the above-mentioned state, the first latch circuit 61 from the left in the first latch section 66 reads no data. Then, the second to m+1-th latch circuits 61 from the left in the first latch section 66 read R, G and B data sequentially three at a time in parallel. The output of the data reading instruction signal from each of the signal output terminals C1, C2, . . . is completed during the cycle of STB.
After that, the second to m+1-th latch circuits from the left in the second latch section 43 reads data for one row collectively from the first latch section 66, and inputs each data to the data input terminal U2 to Um+1 of the level shifter 35. After that, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as that in the sixth and ninth embodiments. The operation of the DA converter 36 depends on the level of POL1 input. The above operation is referred to as the second operation.
After that, POL2 is switched between high level and low level alternately per cycle of STB. As a result, the first operation and the second operation are repeated alternately.
In each of the second and subsequent frames, POL2 is set to high level at the time of starting the frame. Since POL2 is at high level, the output of shift register switching section 65 continues to connect each signal output terminal Ci of the shift register 31 with the terminals LS3·i−2, LS3·i−1 and LS3·i. Further, the switch section 34 continues to connect each input terminal Ii to the output terminal Oi. As a result, the driving device performs the same operation as the first operation mentioned above.
Further, when POL2 becomes low level, the output of shift register switching section 65 switches to a state in which each signal output terminal Ci of the shift register 31 is connected to the terminals LS3·i−1, LS3·i and LS3·i+1. Further, the switch section 34 switches to a state in which each input terminal Ii is connected to the output terminal Oi+1. As a result, the driving device performs the same operation as the second operation mentioned above.
In each of the second and subsequent frames, since POL2 is also switched between high level and low level alternately per cycle of STB, the first operation and the second operation are performed alternately.
As a result of the above operations, the polarities of pixels adjacent to each other in the longitudinal direction and the lateral direction become opposite to each other. Further, since POL1 is switched on a frame-by-frame basis, the polar state shown in
This embodiment also has effects similar to the sixth embodiment.
Further, each modification of the sixth embodiment can also be applied to the tenth embodiment.
The liquid crystal display panel 2 is the same as that in the first embodiment. In the example shown in
The operation of the shift register 81 is the same as the shift register 31 in the sixth and tenth embodiments and the like, except in that the shift register 81 has m signal output terminal C1 to Cm as many as the number of columns of pixels (dots) on the liquid crystal display panel 2. Since the shift register 81 is the same as the shift register already described except for the number of signal output terminals, the detailed description thereof will be omitted.
The switch section 34 is the same as the switch section 34 in the sixth embodiment, having m input terminals I1 to Im and m+1 output terminals O1 to Om+1. Each of the input terminals I1 to Im is connected to each of the signal output terminal C1 to Cm of the shift register 81 in a one-to-one relationship. In the eleventh embodiment, it is assumed that the switch section 34 continues to connect the input terminal Ii to the output terminal Oi until POL2 is input after the liquid crystal display device is turned on. After that, when POL2 is input, the switch section 34 operates in accordance with POL2.
The first latch section 66 has sign input terminals L1 to Lm+1, and the sign input terminals L1 to Lm+1 are connected to the output terminal O1 to Om+1 of the switch section 34 in a one-to-one relationship. When the data reading instruction signal is input from the signal input terminal Li, the first latch section 66 captures the i-th data in one line. In the eleventh and subsequent embodiments, it is assumed that each pixel data is transferred as data for one line sequentially in the following order: R, G, B, R, G, B . . . . Therefore, the first latch section 66 reads data for one line serially in response to the data reading instruction signal input in series from the shift register 81 through the switch section 34. In other words, the first latch section 66 reads data in order one pixel (dot) by one pixel (dot). The first latch section 66 has m+1 output terminals L′1 to as terminals used to read data (m data) for one line. For example, the first latch section 66 may have the same structure as the first latch section 66 (see
Further, the liquid crystal display panel 2 may be a black-and-white liquid crystal display panel provided with black-and-white pixels. In this case, data transferred to the first latch section 66 may be data according to a black-and-white image. This point holds true for the twelfth and subsequent embodiments.
The second latch section 43 has data reading terminals Q1 to Qm+1 for reading data for one line, and the data reading terminals Q1 to Qm+1 are connected to the output terminals L′1 to L′m+1 of the first latch section 66 in a one-to-one relationship. The second latch section 43 reads m data for one line collectively from the first latch section 66 at predetermined timing (e.g., on the falling edge of STB or the like) in each cycle of STB, and outputs each data from the data output terminals Q′1 to Q′m+1, respectively. The data output terminals Q′1 to Q′m+1 contained in the second latch section 43 are connected to the data input terminals U1 to Um+1 of the level shifter 35 in a one-to-one relationship. For example, the second latch section 43 may have the same structure as the second latch section 43 in the tenth embodiment.
The level shifter 35, the DA converter 36 and the voltage follower 37 are the same as those in the sixth and tenth embodiments. The mode of connections among these components 35 to 37 is also the same as in the sixth and tenth embodiments. Each of the potential output terminals V1 to Vm+1 of the voltage follower 37 are connected to each of the source lines S1 to Sm+1 of the liquid crystal display panel 2 in a one-to-one relationship.
In the eleventh embodiment, the control section (not shown in
In each of the second and subsequent frames, the control section (or the driving device) sets POL2 to high level upon the first selection period, and after that, the level of POL2 is switched alternately per cycle of STB in the frame. In each of the second and subsequent frames, POL2 is set to high level at the time of starting the frame regardless of whether POL2 before the start of the frame is at high level or low level, and after that, the level of POL2 is switched per cycle of STB. This point also the same as that in the tenth embodiment.
Next, the operation at power-on will be described. After power-on, the switch section 34 continues to connect each input terminal Ii to the output terminal Oi. In this state, when the frame is started, the shift register 81 outputs the data reading instruction signal from the signal output terminals C1, C2, . . . in this order in response to SCLK, and the first latch section 66 reads data for one line serially one pixel by one pixel. At this time, since the switch section 34 is in the above-mentioned state, the output terminal Om+1 of the switch section 34 is not connected to the input terminal Im. Therefore, since there is no signal input to the signal input terminal Lm+1 of the first latch section 66, the data output terminal L′m+1 is not used.
After that, when the generation of STB is started, the data reading terminals Q1 to Qm of the second latch section 43 reads data for one row collectively from the first latch section 66, and inputs each data to the data input terminals U1 to Um of the level shifter 35. After that, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as that in the sixth, ninth and tenth embodiments and the like. Note that the operation of the DA converter 36 depends on the level of POL1 input. As described in the tenth embodiment, this operation is referred to as the first operation.
It is assumed that POL2 is also generated together with STB, and low-level POL2 is input to the switch section 34. As a result, the switch section 34 switches to a state in which each input terminal Ii is connected to the output terminal Oi+1.
The shift register 81 outputs the data reading instruction signal from the signal output terminals C1, C2, . . . in this order in response to SCLK, and the first latch section 66 reads data for one line serially one pixel (dot) by one pixel (dot). Since each input terminal Ii of the switch section 34 is connected to the output terminal Oi+1, there is no signal input to the signal input terminal L1 of the first latch section 66, and data output terminal L′1 is not used.
After that, the data reading terminals Q2 to Qm+1 of the second latch section 43 reads data for one row collectively from the first latch section 66, and inputs each data to the data input terminals U2 to Um+1 of the level shifter 35. After that, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as in the sixth, ninth and tenth embodiments and the like. Note that the operation of the DA converter 36 depends on the level of POL1 input. As described in the tenth embodiment, this operation is referred to as the second operation.
After that, POL2 is switched between high level and low level alternately per cycle of STB. As a result, the first operation and the second operation are repeated alternately.
In each of the second and subsequent frames, POL2 is set to high level at the time of starting the frame. Since POL2 is at high level, the switch section 34 is in the state where each input terminal Ii is connected to the output terminal Oi. As a result, the driving device performs the same operation as the first operation mentioned above.
Further, when POL2 becomes low level, the switch section 34 switches to a state in which each input terminal Ii is connected to the output terminal Oi+1. As a result, the driving device performs the same operation as the second operation mentioned above.
In each of the second and subsequent frames, since POL2 is switched between high level and low level alternately per cycle of STB, the first operation and the second operation are performed alternately.
As a result of the above-mentioned operations, the polar state of each pixel in each frame becomes the same as that in the sixth embodiment and the like.
This embodiment also has effects similar to the sixth embodiment.
Next, a modification of the eleventh embodiment will be described.
Like in the first embodiment,
Further, like in the second embodiment, two or more consecutive gate lines may be grouped. In this case, the liquid crystal panel has the same structure as the liquid crystal panel 2a (see
In the structure of the twelfth embodiment is different from that of the eleventh embodiment in that the switch section 34 is arranged between the first latch section 66 and the second latch section 43. Because of this arrangement, the first latch section 66 has m signal input terminals L1 to Lm and m output terminals L′1 to L′m in the twelfth embodiment. The sign input terminals L1 to Lm of the first latch section 66 are connected to the signal output terminal C1 to Cm of the shift register 81 in a one-to-one relationship. Further, the output terminals L′1 to L′m of the first latch section 66 are connected to the input terminals I1 to Im of the switch section 34 in a one-to-one relationship.
The structure of the switch section 34 is that same as that in the sixth and other embodiments. In this embodiment, the output terminals O1 to Om+1 of the switch section 34 are connected to the data reading terminals Q1 to Qm+1 of the second latch section 43 in a one-to-one relationship.
The second latch section 43, the level shifter 35, the DA converter 36, the voltage follower 37 and the liquid crystal display panel 2 are the same as those in the eleventh embodiment. Further, the mode of connections among these components 43, 35, 36, 37 and 2 is also the same as that in the eleventh embodiment.
The output mode of control signals from the control section (not shown in
A frame in which periods A and B (see
The data output from the data output terminals Q′1 to Q′m of the second latch section 43 are input to the data input terminal U1 to Um of the level shifter 35. Further, POL1 is at high level during period A. Therefore, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as that for period A described in the sixth embodiment.
Since POL2 becomes low level during period B (see
The data output from the data output terminals Q′2 to Q′m+1 of the second latch section 43 are input to the data input terminals U2 to Um+i of the level shifter 35. Further, POL1 is at high level during period B. Therefore, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as that for period B described in the sixth embodiment.
After that, the operations for periods A and B are repeated alternately.
Next, a frame in which periods C and D (see
Since POL2 becomes low level during period D, the second latch section 43 reads data for one row from the data reading terminals Q2 to Qm+1 through the switch section 34, and outputs each data from the data output terminals Q′2 to Q′m+1. At this time, POL1 is at low level. Therefore, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as that for period D described in the sixth embodiment.
After that, the operations for periods C and D are repeated alternately in this frame.
As a result of the above-mentioned operations, the polar state of each pixel in each frame becomes the same as that in the sixth embodiment and the like.
This embodiment also has effects similar to the sixth embodiment.
Further, each modification of the eleventh embodiment can also be applied to the twelfth embodiment.
The mode of connection between the shift register 81 and the first latch section 66 is the same as that in the twelfth embodiment.
The structure of the thirteenth embodiment is different from that of the twelfth embodiment in that the switch section 34 is arranged between the second latch section 43 and the level shifter 35. Because of this arrangement, the second latch section 43 has m data reading terminals Q1 to Qm and m data output terminals Q′1 to Q′m in the thirteenth embodiment. The data reading terminals Q1 to Qm of the second latch section 43 are connected to the output terminals L′1 to L′m of the first latch section 66 in a one-to-one relationship. Further, the data output terminals Q′1 to Q′m of the second latch section 43 are connected to the input terminal I1 to Im of the switch section 34 in a one-to-one relationship.
The structure of the switch section 34 is that same as that in the sixth and other embodiments. In this embodiment, the output terminals O1 to Om+1 of the switch section 34 are connected to the data input terminal U1 to Um+1 of the level shifter 35 in a one-to-one relationship.
The level shifter 35, the DA converter 36, the voltage follower 37 and the liquid crystal display panel 2 are the same as those in the eleventh and twelfth embodiments. The mode of connections among these components is also the same as that in the eleventh and twelfth embodiments.
As already described, the level variations of POL1 and POL2 in the thirteenth embodiment are also the same as the case shown in
Since POL2 becomes low level during period B, any input terminal Ii of the switch section 34 is connected to the output terminal Oi+1. Further, the second latch section 43 captures data for one row from the data reading terminals Q1 to Qm, and outputs each data from the data output terminals Q′1 to Q′m. Since the switch section 34 is in the above-mentioned state, the data output from the data output terminals Q′1 to Q′m are input to the data input terminals U2 to Um+1 of the level shifter 35. Further, POL1 is at high level during period B. Therefore, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as the operation for period B described in the sixth embodiment. Note that there is no input and output to and from the leftmost terminal in the level shifter 35, the DA converter 36 and the voltage follower 37.
After that, the operations for periods A and B are repeated alternately in this frame.
Next, a frame in which periods C and D (see
Since POL2 becomes low level during period D, any input terminal Ii of the switch section 34 is connected to the output terminal O1+1. Therefore, the data output from the data output terminals Q′1 to Q′m of the second latch section 43 are input to the data input terminal U2 to Um+1 of the level shifter 35. Further, POL1 is at low level during period D. Therefore, the operation of the level shifter 35, the DA converter 36 and the voltage follower 37 is the same as the operation for period D described in the sixth embodiment. Note that there is no input and output to and from the leftmost terminal in the level shifter 35, the DA converter 36 and the voltage follower 37.
After that, the operations for periods C and D are repeated alternately.
As a result of the above-mentioned operations, the polar state of each pixel in each frame becomes the same as that in the sixth embodiment and the like.
This embodiment also has effects similar to the sixth embodiment.
Further, each modification of the eleventh embodiment can also be applied to the thirteenth embodiment.
The shift register 81, the first latch section 66 and second latch section 43, and the mode of connections among them are the same as in the thirteenth embodiment.
The structure of the fourteenth embodiment is different from the thirteenth embodiment in that the switch section 34 is arranged between the level shifter 35 and the DA converter 36. Because of this arrangement, the level shifter 35 has m data input terminals U1 to Um and m data output terminals U′1 to U′m in the fourteenth embodiment. The data input terminals U1 to Um of the level shifter 35 are connected to the data output terminals Q′1 to Q′m of the second latch section 43 in a one-to-one relationship. Further, the data output terminals U′1 to U′m of the level shifter 35 are connected to the input terminals I1 to Im of the switch section 34 in a one-to-one relationship.
The structure of the switch section 34 is that same as that in the sixth and other embodiments. In this embodiment, the output terminals O1 to Om+1 of the switch section 34 are connected to the data input terminals T1 to Tm+1 of the DA converter 36 in a one-to-one relationship.
The DA converter 36, the voltage follower 37 and the liquid crystal display panel 2, and the mode of connections among them are the same as in the eleventh embodiment and the like.
As already described, the level variations of POL1 and POL2 in the fourteenth embodiment are also the same as the case shown in
Since POL2 becomes low level during period B, any input terminal Ii of the switch section 34 is connected to the output terminal Oi+1. The second latch section 43 inputs data for one row to the data input terminals U1 to Um of the level shifter 35. The level shifter 35 shifts the level of input data and outputs the data from the data output terminals U′1 to U′m. Since the switch section 34 is in the above-mentioned state, the data output from the data input terminals U1 to Um are input to the data input terminals T2 to Tm+1 of the DA converter. POL1 is at high level during period B. Therefore, the operation of the DA converter 36 and the voltage follower 37 is the same as the operation for period B described in the sixth embodiment. Note that there is no input and output to and from the leftmost terminal in the DA converter 36 and the voltage follower 37.
After that, the operations for periods A and B are repeated alternately in this frame.
Next, a frame in which periods C and D (see
Since POL2 becomes low level during period D, any input terminal Ii of the switch section 34 is connected to the output terminal Oi+1. The second latch section 43 inputs data for one row to the data input terminals U1 to Um of the level shifter 35. The level shifter 35 shifts the level of input data and outputs the data from the data output terminals U′1 to U′m. Since the switch section 34 is in the above-mentioned state, the data output from the data input terminals U1 to Um are input to the data input terminals T2 to Tm+1 of the DA converter. POL1 is at low level during period D. Therefore, the operation of the DA converter 36 and the voltage follower 37 is the same as the operation for period D described in the sixth embodiment. Note that there is no input and output to and from the leftmost terminal in the DA converter 36 and the voltage follower 37.
After that, the operations for periods C and D are repeated alternately.
As a result of the above-mentioned operations, the polar state of each pixel in each frame becomes the same as that in the sixth embodiment.
This embodiment also has effects similar to the sixth embodiment.
Further, each modification of the eleventh embodiment can also be applied to the fourteenth embodiment.
The shift register 81, the first latch section 66 and second latch section 43, and the mode of connection among them are the same as in the fourteenth embodiment.
The structure of the fifteenth embodiment is different from the fourteenth embodiment in that the switch section 34 is arranged between the DA converter 36 and the voltage follower 37. Because of this arrangement, the DA converter 36 has m data input terminals T1 to Tm and m potential output terminals T′1 to T′m in the fifteenth embodiment. The DA converter 36 is the same as that in the fourteenth and other embodiments, except in that the data input terminals and the potential output terminals are one less in number, respectively. The data input terminals T1 to Tm of the DA converter 36 are connected to the data output terminals U′1 to U′m of the level shifter 35 in a one-to-one relationship. Further, the potential output terminals T′1 to T′m of the DA converter 36 are connected to the input terminals I1 to Im of the switch section 34 in a one-to-one relationship.
The structure of the switch section 34 is that same as that in the sixth and other embodiments. In this embodiment, the output terminals O1 to Om+1 of the switch section 34 are connected to the potential input terminals W1 to Wm+1 of the voltage follower in a one-to-one relationship.
The voltage follower 37 and the liquid crystal display panel 2, and the mode of connection therebetween are the same as in the eleventh embodiment and the like.
The output mode of control signals from the control section (not shown in
The following describes frame F1 in which periods E and F (see
Since POL1 is at low level during period F, the DA converter 46 outputs a potential (V9-V17 or the like) lower than VCOM from each of the odd-numbered potential output terminals T′1, T′3, . . . from the left, and outputs a potential (V0-V8 or the like) higher than VCOM from each of the even-numbered potential output terminals T′2, T′4, . . . from the left. Since POL2 becomes low level during period F, any input terminal Ii of the switch section 34 is connected to the output terminal Oi+1. Therefore, the potentials output from the potential output terminals T′1 to T′m of the DA converter 46 are output from the output terminals O2 to Om+1 of the switch section 34, and further output from the potential output terminals V2 to Vm+1 of the voltage follower 37. Note that there is no output from the potential output terminal V1.
After that, the operations for periods E and F are repeated alternately in frame F1.
Next, frame F2 in which periods G and H (see
Since POL1 is at high level during period H, the DA converter 46 outputs a potential (V0-V8 or the like) higher than VCOM from each of the odd-numbered potential output terminals T′1, T′3, . . . from the left, and outputs a potential (V9-V17 or the like) lower than VCOM from each of the even-numbered potential output terminals T′2, T′4, . . . from the left. Further, since POL2 becomes low level during period H, any input terminal Ii of the switch section 34 is connected to the output terminal Oi+1. Therefore, the potentials output from the potential output terminals T′1 to T′m of the DA converter 46 are output from the output terminals O2 to Om+1, and further output from the potential output terminals V2 to Vm+1 of the voltage follower 37. Note that there is no output from the potential output terminal V1.
After that, the operations for periods G and H are repeated alternately in frame F2.
As a result of the above-mentioned operations, the polar state of each pixel in each frame becomes the same as that in the sixth embodiment and the like.
This embodiment also has effects similar to the sixth embodiment.
Further, each modification of the eleventh embodiment can also be applied to the fifteenth embodiment. When two or more consecutive gate lines are grouped, the control section (or the potential setting section) may set POL2 to high level during a period for selecting each row in the odd-numbered group one by one, and set POL2 to low level during a period for selecting each row in the even-numbered group one by one. Then, the cycle of switching the level of POL1 may be matched to the cycle of switching the level of POL2.
Further, in each of the sixth and subsequent embodiments, it is preferred that output of potentials in the next frame be started after the DA converter 36 once sets the output potential of each potential output terminal T′i to a potential between the maximum potential (V0 in the above example) and the minimum potential (V17 in the above example) during a vertical blanking interval. It is particularly preferred that the DA converter 36 should set the output potential of each potential output terminal T′i to VCOM(=(V0+V17)/2) during the vertical blanking interval. This setting can reduce the load on the power supply (not shown in
In order to set the output potential of each potential output terminal of the DA converter 36 once to a potential between the maximum potential and the minimum potential, DA converter 36 may, for example, short-circuit between pair of adjacent two potential output terminals.
The present invention can be applied to both normally white and normally black.
According to the present invention, the liquid crystal display panel can be so driven that the number of consecutive pixels having the same polarity will be reduced while reducing power consumption, and the liquid crystal display panel can be driven without changing the order of output of potentials corresponding to image data from the order of input of image data.
The aforementioned embodiments disclose the characteristic structures of the present invention as follows:
(Note 1) A liquid crystal display device comprising: an active matrix liquid crystal display panel; and a driving device for driving the liquid crystal display panel, wherein the liquid crystal display panel comprises: a common electrode; a plurality of pixel electrodes arranged in a matrix; and source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, and the driving device comprises: potential output means having a plurality of potential output terminals from each of which a potential corresponding to an input pixel value is output, and configured to output a potential from each potential output terminal in such a manner to output a potential higher than a common electrode potential and a potential lower than the common electrode potential alternately in order of arrangement of the potential output terminals; and switch means having a plurality of input terminals and switch output terminals that is one more in number than the plurality of input terminals, wherein if the k-th input terminal from the left is denoted as Ik, the k-th and k+1-th switch output terminals from the left are denoted as Ok and Ok+1, respectively, the number of input terminals is denoted as n, and k takes each value from 1 to n, the switch means connects the input terminal Ik to either of the switch output terminals Ok and Ok+1, wherein each source line of the liquid crystal display panel is connected to a corresponding switch output terminal of the switch means, the potential output means switches between output of a potential higher than the common electrode potential and output of a potential lower than the common electrode potential at each potential output terminal depending on a period for selecting each row in the odd-numbered group one by one or a period for selecting each row in the even-numbered group one by one, the switch means switches between the switch output terminals to be connected to each input terminal depending on the period for selecting each row in the odd-numbered group one by one or the period for selecting each row in the even-numbered group one by one, and the potential output means continues to output, from each potential output terminal, a potential specific to a pixel value corresponding to the potential output terminal, respectively, during a selection period of one row.
(Note 2) The liquid crystal display device according to Note 1, further comprising control means for outputting a first control signal to control whether the potential of each potential output terminal of the potential output means is set higher or lower than the common electrode potential, and a second control signal to give an instruction to determine to which of the switch output terminals Ok and Ok+1 the input terminal Ik is to be connected, wherein depending on whether the first control signal is at high level or low level, the potential output means switches between whether a potential higher than the common electrode potential is output from an odd-numbered potential output terminal from the left and a potential lower than the common electrode potential is output from an even-numbered potential output terminal from the left, and whether a potential lower than the common electrode potential is output from the odd-numbered potential output terminal from the left and a potential higher than the common electrode potential is output from the even-numbered potential output terminal from the left, the switch means switches between the switch output terminals Ok and Ok+1 to which the input terminal Ik is to be connected, depending on whether the second control signal is at high level or low level, and the control means switches the levels of the first control signal and the second control signal between the period for selecting each row in the odd-numbered group one by one and the period for selecting each row in the even-numbered group one by one.
(Note 3) The liquid crystal display device according to Note 2, wherein the control means switches, on a frame-by-frame basis, between a mode of outputting the control signals, in which when the first control signal is set to high level, the second control signal is also set to high level, while when the first control signal is set to low level, the second control signal is also set to low level, and a mode of outputting the control signals, in which when the first control signal is set to low level, the second control signal is set to high level, while when the first control signal is set to high level, the second control signal is set to low level.
(Note 4) The liquid crystal display device according to Note 2 or 3, wherein upon switching between selection periods, the control means puts output from a potential output terminal of the potential output means into a high impedance state, and switches the level of the second control signal while the output of the potential output terminal is in the high impedance state.
(Note 5) The liquid crystal display device according to Note 1, further comprising control means for outputting a first control signal to control whether the potential of each potential output terminal of the potential output means is set higher or lower than the common electrode potential and notifying the potential output means of the start of a frame, wherein the potential output means outputs a second control signal to give an instruction to determine to which of the switch output terminals Ok and Ok+1 the input terminal Ik is to be connected, and depending on whether the first control signal is at high level or low level, the potential output means switches between whether a potential higher than the common electrode potential is output from an odd-numbered potential output terminal from the left and a potential lower than the common electrode potential is output from an even-numbered potential output terminal from the left, and whether a potential lower than the common electrode potential is output from the odd-numbered potential output terminal from the left and a potential higher than the common electrode potential is output from the even-numbered potential output terminal from the left, the switch means switches between the switch output terminals Ok and Ok+1 to which the input terminal Ik is to be connected, depending on whether the second control signal is at high level or low level, the control means switches the level of the first control signal between the period for selecting each row in the odd-numbered group one by one and the period for selecting each row in the even-numbered group one by one, and when notified of the start of a frame, the potential output means controls the second control signal to connect the input terminal Ik to the switch output terminal Ok, and after that, switches the level of the second control signal between the period for selecting each row in the odd-numbered group one by one and the period for selecting each row in the even-numbered group one by one.
(Note 6) The liquid crystal display device according to Note 5, wherein the control means switches, on a frame-by-frame basis, between a mode of outputting the control signals, in which when the second control signal becomes high level, the first control signal is set to high level, while when the second control signal becomes low level, the first control signal is set to low level, and a mode of outputting the control signals, in which when the second control signal becomes high level, the first control signal is set to low level, while when the second control signal becomes low level, the first control signal is set to high level.
(Note 7) The liquid crystal display device according to
Note 5 or 6, wherein upon switching between selection periods, the control means puts output from a potential output terminal of the potential output means into a high impedance state, and the potential output means switches the level of the second control signal while the output from the potential output terminal is in the high impedance state.
(Note 8) The liquid crystal display device according to any one of Notes 1 to 7, wherein every row of pixel electrodes is set as one group in such a manner that a pixel electrode in an odd-numbered row is connected to a source line on a predetermined side among source lines existing on both sides of the pixel electrode, and a pixel electrode in an even-numbered row is connected to a source line on the side opposite to the predetermined side among the source lines existing on both sides of the pixel electrode.
(Note 9) The liquid crystal display device according to any one of Notes 1 to 8, wherein two or more driving devices are provided, switch means of respective driving devices are placed side by side, and among adjacent two switch means, the rightmost switch output terminal of the left-hand switch means and the leftmost switch output terminal of the right-hand switch means are connected to a common source line.
(Note 10) The liquid crystal display device according to any one of Notes 1 to 9, wherein the potential output means sets the output potential of each potential output terminal to a potential between the maximum potential and the minimum potential output from the potential output terminal during a vertical blanking interval.
(Note 11) The liquid crystal display device according to any one of Notes 1 to 10, wherein the potential output means short-circuits between a pair of adjacent two potential output terminals during a vertical blanking interval.
(Note 12) The liquid crystal display device according to any one of Notes 1 to 11, wherein R, G and B pixels are arranged on the liquid crystal panel in the same sequence on a row-by-row basis.
(Note 13) The liquid crystal display device according to any one of Notes 1 to 11, wherein R, G and B pixels are arranged on the liquid crystal panel in different sequences among a predetermined number of consecutive rows, and the R, G and B arrangement pattern in the predetermined number of consecutive rows is repeated.
(Note 14) The liquid crystal display device according to any one of Notes 1 to 11, wherein only one kind of pixels among R, G and B are arranged in each row on the liquid crystal panel.
(Note 15) A liquid crystal display device comprising: an active matrix liquid crystal display panel; and a driving device for driving the liquid crystal display panel, wherein the liquid crystal display panel comprises: a common electrode; a plurality of pixel electrodes arranged in a matrix; and source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, and the driving device comprises: a DA converter for inputting each data corresponding to each of pixel values for one row, converting the input data to an analog voltage, and outputting a potential after subjected to conversion, wherein depending on whether a first control signal input to the DA converter is at high level or low level, the DA converter switches between whether a potential higher than a common electrode potential is output from an odd-numbered potential output terminal from the left and a potential lower than the common electrode potential is output from an even-numbered potential output terminal from the left, and whether a potential lower than the common electrode potential is output from the odd-numbered potential output terminal from the left and a potential higher than the common electrode potential is output from the even-numbered potential output terminal from the left; and switch means for switching between whether the potential of a pixel electrode is set using the source line on the left side of the pixel electrode and whether the potential of the pixel electrode is set using the source line on the right side of the pixel electrode, wherein if the number of pixel columns to be driven is denoted as m, the switch means has m input terminals and m+1 switch output terminals, and if the k-th input terminal from the left is denoted as Ik, the k-th and k+l-th switch output terminals from the left are denoted as Ok and Ok+1, respectively, and k takes each value from 1 to m, the switch means switches, depending on whether a second control signal input to the switch means is at high level or low level, between whether the input terminal Ik is connected to the switch output terminal Ok and whether the input terminal Ik is connected to the switch output terminal Ok+1.
(Note 16) The liquid crystal display device according to Note 15, wherein the driving device further comprises a voltage follower, and depending on whether the second control signal is at high level or low level, output from the leftmost potential output terminal of the voltage follower is put into a high impedance state or output from the rightmost potential output terminal of the voltage follower is put into the high impedance state.
(Note 17) The liquid crystal display device according to Note 15, wherein two or more driving devices are provided, and among adjacent two driving devices, the rightmost potential output terminal of the left-hand driving device and the leftmost potential output terminal of the right-hand driving device are connected to a common source line.
(Note 18) The liquid crystal display device according to Note 15, further comprising: first latch means for reading and holding R, G and B pixel values each for one pixel simultaneously; a shift register for outputting a data reading instruction signal sequentially to instruct the first latch means to read each of the R, G and B pixel values each for one pixel; second latch means for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower having m+1 potential input terminals and m+1 potential output terminals, and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to the pixel values of m pixels for one row, the DA converter has m+1 data input terminals and m+1 potential output terminals, the data output terminals of the second latch means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
(Note 19) The liquid crystal display device according to Note 15, further comprising: first latch means for reading and holding R, G and B pixel values each for one pixel simultaneously; a shift register for outputting a data reading instruction signal sequentially to instruct the first latch means to read each of the R, G and B pixel values each for one pixel; second latch means for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means having m data input terminals and m data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower having m+1 potential input terminals and m+1 potential output terminals, and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to the pixel values of m pixels for one row, the DA converter has m+1 data input terminals and m+1 potential output terminals, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
(Note 20) The liquid crystal display device according to Note 15, further comprising: first latch means for reading and holding R, G and B pixel values each for one pixel simultaneously; a shift register for outputting a data reading instruction signal sequentially to instruct the first latch means to read each of the R, G and B pixel values each for one pixel; second latch means for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means having m data input terminals and m data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower having m+1 potential input terminals and m+1 potential output terminals, and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to the pixel values of m pixels for one row, the DA converter has m data input terminals and m potential output terminals, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminal of the switch means are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the levels of the first control signal and the second control signal are switched alternately each time all rows belonging to a group are selected, and in one frame, when the second control signal is at high level, the first control signal also becomes high level, while when the second control signal is at low level, the first control signal also becomes high level, and in the next frame following the one frame, when the second control signal is at high level, the first control signal becomes low level, while when the second control signal is at low level, the first control signal becomes high level.
(Note 21) The liquid crystal display device according to Note 15, further comprising: first latch means for reading and holding R, G and B pixel values each for one pixel simultaneously; a shift register for outputting a data reading instruction signal sequentially to instruct the first latch means to read each of the R, G and B pixel values each for one pixel; second latch means for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower having m+1 potential input terminals and m+1 potential output terminals, and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the first latch means has m pixel value output terminals for causing the second latch means to read the pixel values, the second latch means has m+1 data reading terminals for reading the pixel values from the first latch means, and m+1 data output terminals for outputting data corresponding to the pixel values of pixels for one row, the DA converter has m+1 data input terminals and m+1 potential output terminals, the pixel value output terminals of the first latch means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data reading terminals of the second latch means in a one-to-one relationship, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
(Note 22) The liquid crystal display device according to Note 15, wherein the number of columns of pixels to be driven is a multiple of 3, and the liquid crystal display device further comprises: first latch means in which m+1 latch circuits are arranged, each latch circuit having an input terminal for a data reading instruction signal to give an instruction to read a pixel value, a pixel value reading terminal for reading a pixel value for one pixel input when the data reading instruction signal is input to the input terminal, and an output terminal for the pixel value; a shift register having signal output terminals for a m/3 piece of data reading instruction signal and configured to output the data reading instruction signal sequentially from each of the signal output terminals; output of shift register switching means which, if the i-th signal output terminal from the left in the shift register is denoted as Ci and i takes each value from 1 to m/3, connects the signal output terminal Ci with input terminals of the 3·i−2-th, 3·i−1-th and 3·i-th latch circuits of the first latch means when the second control signal is at high level, or connects the signal output terminal Ci with input terminals of the 3·i−1-th, 3·i-th and 3·i+1-th latch circuits of the first latch means when the second control signal is at low level; second latch means for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the input terminals of the switch means are connected to data wiring for transferring pixel values for R, data wiring for transferring pixel values for G and data wiring for transferring pixel values for B, the switch output terminals of the switch means are connected to the pixel value reading terminals of the respective latch circuits in the first latch means in a one-to-one relationship, the second latch means has m+1 data reading terminals for reading pixel values from the first latch means and m+1 data output terminals for outputting data corresponding to pixel values of pixels for one row, DA converter has m+1 data input terminals and m+1 potential output terminals, the output terminals of the respective latch circuits in the first latch means are connected to the data reading terminals of the second latch means in a one-to-one relationship, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, the level of the second control signal is switched alternately each time all rows belonging to a group are selected after the second control signal is set to high level upon starting a frame, and the output of shift register switching means and the switch means maintain a state equal to that when the second control signal is at high level until the second control signal is generated in a first frame after power-on.
(Note 23) The liquid crystal display device according to Note 15, further comprising: first latch means having m+1 input terminals for a data reading instruction signal to give an instruction to read a pixel value, and configured such that, when the data reading instruction signal is input, the first latch means reads and holds a pixel value for one pixel corresponding to an input terminal to which the data reading instruction signal is input; a shift register having m signal output terminals for the data reading instruction signal and configured to output the data reading instruction signal sequentially from each signal output terminal; second latch means for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and outputting the data from the data output terminals; and a voltage follower having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the first latch means has m+1 pixel value output terminals for causing the second latch means to read pixel values, the second latch means has m+1 data reading terminals for reading pixel values from the first latch means and m+1 data output terminals for outputting data corresponding to pixel values of pixels for one row, the DA converter has m+1 data input terminals and m+1 potential output terminals, the signal output terminals of the shift register are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the input terminals of the first latch means in a one-to-one relationship, the pixel value output terminals of the first latch means are connected to the data reading terminals of the second latch means in a one-to-one relationship, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, the level of the second control signal is switched alternately each time all rows belonging to a group are selected after the second control signal is set to high level upon starting a frame, and the switch means maintains a state equal to that when the second control signal is at high level until the second control signal is generated in a first frame after power-on.
(Note 24) The liquid crystal display device according to Note 15, further comprising: first latch means for reading and holding a pixel value on a pixel-by-pixel basis; a shift register for outputting a data reading instruction signal sequentially to instruct the first latch means to read a pixel value for one pixel; second latch means for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the first latch means has m pixel value output terminals for causing the second latch means to read pixel values, the second latch means has m+1 data reading terminals for reading pixel values from the first latch means, and m+1 data output terminals for outputting data corresponding to pixel values of pixels for one row, DA converter has m+1 data input terminals and m+1 potential output terminals, the pixel value output terminals of the first latch means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data reading terminals of the second latch means in a one-to-one relationship, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminal of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
(Note 25) The liquid crystal display device according to Note 15, further comprising: first latch means for reading and holding a pixel value on a pixel-by-pixel basis; a shift register for outputting a data reading instruction signal sequentially to instruct the first latch means to read a pixel value for one pixel; second latch means for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means having m+1 data input terminals and m+1 data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to the pixel values of m pixels for one row, DA converter has m+1 data input terminals and m+1 potential output terminals, the data output terminals of the second latch means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
(Note 26) The liquid crystal display device according to Note 15, further comprising: first latch means for reading and holding a pixel value on a pixel-by-pixel basis; a shift register for outputting a data reading instruction signal sequentially to instruct the first latch means to read a pixel value for one pixel; second latch means for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means having m data input terminals and m data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to pixel values of m pixels for one row, DA converter has m+1 data input terminals and m+1 potential output terminals, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminals of the switch means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the level of the first control signal is switched alternately on a frame-by-frame basis, and the level of the second control signal is switched alternately each time all rows belonging to a group are selected.
(Note 27) The liquid crystal display device according to Note 15, further comprising: first latch means for reading and holding a pixel value on a pixel-by-pixel basis; a shift register for outputting a data reading instruction signal sequentially to instruct the first latch means to read a pixel value for one pixel; second latch means for reading pixel values of m pixels for one row collectively from the first latch means, and outputting data corresponding to each pixel value; level shifting means having m data input terminals and m data output terminals and configured to shift the levels of data input from the data input terminals and output the data from the data output terminals; and a voltage follower having m+1 potential input terminals and m+1 potential output terminals and configured to output, from the potential output terminals, potentials equal to potentials input from the potential input terminals, wherein the second latch means has m data output terminals for outputting data corresponding to the pixel values of m pixels for one row, the DA converter has m data input terminals and m potential output terminals, the data output terminals of the second latch means are connected to the data input terminals of the level shifting means in a one-to-one relationship, the data output terminals of the level shifting means are connected to the data input terminals of the DA converter in a one-to-one relationship, the potential output terminals of the DA converter are connected to the input terminals of the switch means in a one-to-one relationship, the switch output terminal of the switch means are connected to the potential input terminals of the voltage follower in a one-to-one relationship, the potential output terminals of the voltage follower are connected to the source lines of the liquid crystal display panel, the levels of the first control signal and the second control signal are switched alternately each time all rows belonging to a group are selected, and in one frame, when the second control signal is at high level, the first control signal also becomes high level, while when the second control signal is at low level, the first control signal also becomes high level, and in the next frame following the one frame, when the second control signal is at high level, the first control signal becomes low level, while when the second control signal is at low level, the first control signal becomes high level.
(Note 28) A driving device for a liquid crystal display panel including a common electrode, a plurality of pixel electrodes arranged in a matrix, and source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, the driving device comprising: potential output means having a plurality of potential output terminals from each of which a potential corresponding to an input pixel value is output, and configured to output a potential from each potential output terminal in such a manner to output a potential higher than a common electrode potential and a potential lower than the common electrode potential alternately in order of arrangement of the potential output terminals; and switch means having a plurality input terminals and switch output terminals that is one more in number than the plurality input terminals, wherein if the k-th input terminal from the left is denoted as Ik, the k-th and k+1-th switch output terminals from the left are denoted as Ok and Ok+1, respectively, the number input terminals is denoted as n, and k takes each value from 1 to n, the switch means connects the input terminal Ik to either of the switch output terminals Ok and Ok+1, wherein the potential output means switches between output of a potential higher than the common electrode potential and output of a potential lower than the common electrode potential at each potential output terminal depending on a period for selecting each row in the odd-numbered group one by one or a period for selecting each row in the even-numbered group one by one, the switch means switches between the switch output terminals to be connected to each input terminal depending on the period for selecting each row in the odd-numbered group one by one or the period for selecting each row in the even-numbered group one by one, and the potential output means continues to output, from each potential output terminal, a potential specific to a pixel value corresponding to the potential output terminal, respectively, during a selection period of one row.
(Note 29) The driving device for a liquid crystal display panel according to Note 28, further comprising control means for outputting a first control signal to control whether the potential of each potential output terminal of the potential output means is set higher or lower than the common electrode potential, and a second control signal to give an instruction to determine to which of the switch output terminals Ok and Ok+1 the input terminal Ik is to be connected, wherein depending on whether the first control signal is at high level or low level, the potential output means switches between whether a potential higher than the common electrode potential is output from an odd-numbered potential output terminal from the left and a potential lower than the common electrode potential is output from an even-numbered potential output terminal from the left, and whether a potential lower than the common electrode potential is output from the odd-numbered potential output terminal from the left and a potential higher than the common electrode potential is output from the even-numbered potential output terminal from the left, the switch means switches between the switch output terminals Ok and Ok+1 to which the input terminal Ik is to be connected, depending on whether the second control signal is at high level or low level, and the control means switches the levels of the first control signal and the second control signal between the period for selecting each row in the odd-numbered group one by one and the period for selecting each row in the even-numbered group one by one.
(Note 30) A driving device for a liquid crystal display panel including a common electrode, a plurality of pixel electrodes arranged in a matrix, and source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, the driving device comprising: a DA converter for inputting each data corresponding to each of pixel values for one row, converting the input data to an analog voltage, and outputting a potential after subjected to conversion, wherein depending on whether a first control signal input to the DA converter is at high level or low level, the DA converter switches between whether a potential higher than a common electrode potential is output from an odd-numbered potential output terminal from the left and a potential lower than the common electrode potential is output from an even-numbered potential output terminal from the left, and whether a potential lower than the common electrode potential is output from the odd-numbered potential output terminal from the left and a potential higher than the common electrode potential is output from the even-numbered potential output terminal from the left; and switch means for switching between whether the potential of a pixel electrode is set using the source line on the left side of the pixel electrode and whether the potential of the pixel electrode is set using the source line on the right side of the pixel electrode, wherein if the number of pixel columns to be driven is denoted as m, the switch means has m input terminals and m+1 switch output terminals, and if the k-th input terminal from the left is denoted as Ik, the k-th and k+l-th switch output terminals from the left are denoted as Ok and Ok+1, respectively, and k takes each value from 1 to m, the switch means switches, depending on whether a second control signal input to the switch means is at high level or low level, between whether the input terminal Ik is connected to the switch output terminal Ok and whether the input terminal Ik is connected to the switch output terminal Ok+1.
(Note 31) The driving device for a liquid crystal display panel according to Note 30, further comprising a voltage follower, wherein depending on whether the second control signal is at high level or low level, output from the leftmost potential output terminal of the voltage follower is put into a high impedance state or output from the rightmost potential output terminal of the voltage follower is put into the high impedance state.
(Note 32) A liquid crystal display panel comprising: a common electrode; a plurality of pixel electrodes arranged in a matrix; source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes; and switch means having a plurality input terminals and switch output terminals that is one more in number than the plurality input terminals, wherein if the k-th input terminal from the left is denoted as Ik, the k-th and k+1-th switch output terminals from the left are denoted as Ok and Ok+1, respectively, the number input terminals is denoted as n, and k takes each value from 1 to n, the switch means connects the input terminal Ik to either of the switch output terminals Ok and Ok+1, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, each source line is connected to a corresponding switch output terminal of the switch means, and the switch means switches between the switch output terminals to be connected to each input terminal depending on the period for selecting each row in the odd-numbered group one by one or the period for selecting each row in the even-numbered group one by one.
(Note 33) A liquid crystal display panel comprising: a common electrode; a plurality of pixel electrodes arranged in a matrix; and source lines provided on the left side of pixel electrodes in each column of pixel electrodes and on the right side of the rightmost column of pixel electrodes, wherein when every row or every two or more consecutive rows of pixel electrodes are set as one group, a pixel electrode in each row of an odd-numbered group is connected to a source line on a predetermined side among source lines existing on both sides of the pixel electrode, and a pixel electrode in each row of an even-numbered group is connected to a source line on the side opposite to the predetermined side among the source lines existing on both sides of the pixel electrode, and among the source lines, a specific odd-numbered source line has two branch portions to connect with different driving devices.
While the present invention has been described with reference to each of the aforementioned embodiments and modifications, the present invention is not intended to be limited to each of the aforementioned embodiments and modifications. Any change that those skilled in the art can contemplate may be added to each of the aforementioned embodiments and modifications within the scope of the present invention.
The present invention is preferably applied to active matrix liquid crystal display devices. For example, the present invention is applicable to TFT liquid crystal display devices, electronic paper using a TFT liquid crystal display device, and handheld liquid crystal display devices. Note that these are just illustrative examples, and the present invention may also be applied to medium- and large-sized liquid crystal display devices.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-244732 | Oct 2009 | JP | national |
| 2010-154897 | Jul 2010 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12903569 | Oct 2010 | US |
| Child | 14454387 | US |
