Patent Grant
6980190
The present invention relates to a liquid crystal display device and a method of driving the liquid crystal display device and, in particular, to a technology suitable for a driving method such as an N-line-inversion driving method in which the polarity of a gray scale voltage applied to a pixel is inverted every N scanning lines.
An active matrix type display device in which an active element (e.g., a thin film transistor) is provided to each pixel and is switched on and off is widely used as a display device for notebook personal computers (hereinafter referred to simply as personal computers), etc.
Among the active matrix type liquid crystal display devices, well known is a TFT type liquid crystal module comprising a liquid crystal display panel using thin film transistors (TFT) as its active elements, drain drivers disposed at the long side of the liquid crystal panel, gate drivers disposed at the short side of the liquid crystal panel, and an interface section disposed on the back of the liquid crystal display panel.
One of these liquid crystal display modules is known in which a precharge voltage is applied to drain signal lines in a liquid crystal display panel to charge the drain signal lines up to the precharge voltage during a pre-determined period at the beginning of one horizontal scanning period (hereinafter referred to as a precharge period).
Such a technique is described, for example, in Japanese Patent Laid-Open No. Hei 11-85107 (laid open on Mar. 30, 1999).
In general, if the same voltage (DC voltage) is applied across a liquid crystal layer for a long time, the tilt angle of liquid crystal molecules is fixed and as a result, the liquid crystal layer presents a phenomenon of image retention, and consequently, lifetime of the liquid crystal layer is shortened.
In order to prevent occurrence of this phenomenon, in a liquid crystal display module, the polarity of a voltage applied across a liquid crystal layer is inverted at intervals of a fixed length of time. A gray scale voltage applied to a pixel electrode is alternated between positive and negative polarities with respect to a common-electrode voltage applied on a common electrode at intervals of a fixed length of time.
Two driving methods are known which apply ac voltages across a liquid crystal layer, one is a symmetrical-about-fixed-common-electrode-voltage driving method, and the other is a common-electrode-voltage-inverting driving method.
The common-electrode-voltage-inverting driving method makes one of the common voltage on the common electrode and the gray scale voltage on the pixel electrode positive in polarity when the other is negative in polarity and vice versa.
The symmetrical-about-fixed-common-electrode-voltage-driving method keeps the common voltage applied on the common electrode fixed and alternates the gray scale voltage applied on the pixel electrode between positive and negative polarities with respect to the common-electrode voltage applied on the common electrode. Among examples of this driving method, known are a dot-inversion driving method and an n-line (e.g., two-line) inversion driving method.
In this specification, polarities of gray scale voltages applied on pixel electrodes are defined with respect to a voltage applied on a common electrode associated with the pixel electrodes in common.
In the dot-inversion driving method, as shown in
The polarities of the voltages on each of the scanning lines is inverted on successive frames. As shown in
With the dot-inversion driving method, the voltages of opposite polarities are applied to adjacent drain signal lines, and consequently, currents flowing through adjacent gate electrodes cancel each other, which makes it possible to reduce power consumption.
It is also possible to minimize deterioration of display quality since the current flowing into the common-electrode is small, hence the voltage drop due to the current is small, and the voltage on the common-electrode is stable.
However, in the case of a personal computer incorporating a liquid crystal display module employing the dot-inversion driving method, there has been a problem in that flicker occurs in a specific display pattern on a liquid crystal display panel and thereby display quality is degraded when there is a particular relationship between timing of polarity inversion and a displayed image pattern (for example, an ending pattern of Windows (a registered trade mark)).
This problem can be solved by adopting the N-line-inversion (for example, two-scanning-line inversion) driving method in which polarities of gray scale voltages supplied to drain signal lines from a drain driver are inverted every N scanning lines.
However, in a case where N-scanning-line-inversion (for example, two-scanning-line inversion) driving method is employed, there has been a problem in that spurious horizontal lines appear every N scanning lines as shown in
With the market demand for larger-sized liquid crystal panels in liquid crystal display devices such as liquid crystal display modules, the liquid crystal panels are required to increase their resolution capable of displaying XGA (Extended Graphics Array) display mode of 1024×768 pixels, SXGA (Super Extended Graphics Array) display mode of 1280×1024 pixels, and UXGA (Ultra Extended Graphics Array) display mode of 1600×1200 pixels.
Therefore, with increase in the number of horizontal scanning lines in one vertical scanning period, time available for writing per horizontal line is decreased, and consequently, a delay time (tDD) in output of the drain driver causes a serious problem.
Specifically, when the ratio of the delay time (tDD) in the output of the drain driver to the time available for writing per horizontal scanning line increases, pixel-writing voltage becomes insufficient, which causes remarkable deterioration in quality of the display on the liquid crystal display panel.
Therefore, a conventional liquid crystal display module is configured such that during a precharge period a precharge voltage is supplied to the drain signal lines to charge up the drain signal lines to the precharge voltage.
However, even if the precharge voltage is supplied to the drain signal line during the precharge period, the precharge voltage does not reach the required precharge voltage in the far-end portion of the drain signal lines far from the drain driver.
Thus, the write voltage becomes insufficient for the pixels disposed far from the drain driver, and it is thought that the display quality of images displayed on the liquid crystal display panel is greatly deteriorated.
The present invention has been made in order to solve the problems of the prior art, and an object of the present invention is to provide a technique for a liquid crystal display device and its driving method capable of preventing occurrence of spurious horizontal lines in a display area in the case where polarities of gray scale voltages are inverted every N (N≧2) scanning lines and to enhance the display quality of displayed images.
Another object of the present invention is to provide a technique in a liquid crystal display device and its driving method capable of reducing voltage differences between voltages charged in the near-end portions of video signal lines proximate to a drain driver during the precharge period and voltages charged in the far-end portions of the video signal lines far from the drain driver during the precharge period, compared with the conventional techniques.
The above-mentioned objects and novel features of the present invention will be made clear by the following description and the accompanying drawings.
The representative structures of the present invention are as follows:
In accordance with an embodiment of the present invention, there is provided a method of driving a liquid crystal display device, said liquid crystal display device including a liquid crystal layer, a plurality of pixels arranged in a matrix configuration, each of said plurality of pixels being provided with a pixel electrode for generating an electric field in said liquid crystal layer between said pixel electrode and a common electrode associated with said plurality of pixels in common, a plurality of video signal lines coupled to said plurality of pixels, a plurality of scanning lines arranged to intersect said plurality of video signal lines and coupled to said plurality of pixels, and a driver circuit for outputting a charging voltage at a beginning of a horizontal scanning period and then a gray scale voltage corresponding to a display data to said plurality of video signal lines, said method comprising: inverting a polarity of said gray scale voltage with respect to a common voltage on said common electrode every N lines of said plurality of scanning lines, where N≧2; and making a first charging time of said charging voltage corresponding to a first line of N lines of said plurality of scanning lines scanned immediately after inversion of said polarity of said gray scale voltage, different from a second charging time of said charging voltage corresponding to a second line of said N lines scanned immediately succeeding said first line.
In accordance with another embodiment of the present invention, there is provided a method of driving a liquid crystal display device, said liquid crystal display device including a liquid crystal layer, a plurality of pixels arranged in a matrix configuration, each of said plurality of pixels being provided with a pixel electrode for generating an electric field in said liquid crystal layer between said pixel electrode and a common electrode associated with said plurality of pixels in common, a plurality of video signal lines coupled to said plurality of pixels, a plurality of scanning lines arranged to intersect said plurality of video signal lines and coupled to said plurality of pixels, and a driver circuit for outputting a charging voltage at a beginning of a horizontal scanning period and then a gray scale voltage corresponding to a display data to said plurality of video signal lines, said method comprising varying a charging time of said charging voltage with a distance from said driver circuit to a scanned one of said plurality of scanning lines.
In accordance with another embodiment of the present invention, there is provided a method of driving a liquid crystal display device, said liquid crystal display device including a liquid crystal layer, a plurality of pixels arranged in a matrix configuration, each of said plurality of pixels being provided with a pixel electrode for generating an electric field in said liquid crystal layer between said pixel electrode and a common electrode associated with said plurality of pixels in common, a plurality of video signal lines coupled to said plurality of pixels, a plurality of scanning lines arranged to intersect said plurality of video signal lines and coupled to said plurality of pixels, a driver circuit for outputting a charging voltage at a beginning of a horizontal scanning period and then a gray scale voltage corresponding to a display data to said plurality of video signal lines, and a display control device for outputting an ac-driving signal for controlling ac-driving of said liquid crystal layer and for outputting a charge-control clock to said driver circuit, said method comprising: inverting a polarity of said gray scale voltage with respect to a common voltage on said common electrode every N lines of said plurality of scanning lines based upon said ac-driving signal, where N≧2; and varying a duration of a first level of said charge-control clock with time such that a first charging time of said charging voltage corresponding to a first line of N lines of said plurality of scanning lines scanned immediately after inversion of said polarity of said gray scale voltage is different from a second charging time of said charging voltage corresponding to a second line of said N lines scanned immediately succeeding said first line.
In accordance with another embodiment of the present invention, there is provided a method of driving a liquid crystal display device, said liquid crystal display device including a liquid crystal layer, a plurality of pixels arranged in a matrix configuration, each of said plurality of pixels being provided with a pixel electrode for generating an electric field in said liquid crystal layer between said pixel electrode and a common electrode associated with said plurality of pixels in common, a plurality of video signal lines coupled to said plurality of pixels, a plurality of scanning lines arranged to intersect said plurality of video signal lines and coupled to said plurality of pixels, a driver circuit for outputting a charging voltage at a beginning of a horizontal scanning period and then a gray scale voltage corresponding to a display data to said plurality of video signal lines, and a display control device for outputting a charge-control clock to said driver circuit, said method comprising varying a duration of a first level of said charge-control clock with time such that a charging time of said charging voltage varies with a distance from said driver circuit to a scanned one of said plurality of scanning lines.
In accordance with another embodiment of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal layer; a plurality of pixels arranged in a matrix configuration, each of said plurality of pixels being provided with a pixel electrode for generating an electric field in said liquid crystal layer between said pixel electrode and a common electrode associated with said plurality of pixels in common; a plurality of video signal lines coupled to said plurality of pixels; a plurality of scanning lines arranged to intersect said plurality of video signal lines and coupled to said plurality of pixels; a driver circuit for outputting a charging voltage at a beginning of a horizontal scanning period and then a gray scale voltage corresponding to a display data to said plurality of video signal lines; and a display control device for outputting an ac-driving signal for controlling ac-driving of said liquid crystal layer and for outputting a charge-control clock to said driver circuit, wherein said display control device is provided with a pulse-duration-varying circuit for varying a duration of a first level of said charge-control clock, and said driver circuit includes: a polarity-inverting circuit for inverting a polarity of said gray scale voltage with respect to a common voltage on said common electrode every N lines of said plurality of scanning lines based upon said ac-driving signal, where N≧2, and a charging-time control circuit for controlling a charging time of said charging voltage based upon said duration of said first level of said charge-control clock such that a first charging time of said charging voltage corresponding to a first line of N lines of said plurality of scanning lines scanned immediately after inversion of said polarity of said gray scale voltage is different from a second charging time of said charging voltage corresponding to a second line of said N lines scanned immediately succeeding said first line.
In accordance with another embodiment of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal layer; a plurality of pixels arranged in a matrix configuration, each of said plurality of pixels being provided with a pixel electrode for generating an electric field in said liquid crystal layer between said pixel electrode and a common electrode associated with said plurality of pixels in common; a plurality of video signal lines coupled to said plurality of pixels; a plurality of scanning lines arranged to intersect said plurality of video signal lines and coupled to said plurality of pixels; a driver circuit for outputting a charging voltage at a beginning of a horizontal scanning period and then a gray scale voltage corresponding to a display data to said plurality of video signal lines; and a display control device for outputting a charge-control clock, wherein said display control device is provided with a pulse-duration-varying circuit for varying a duration of a first level of said charge-control clock, and said driver circuit includes a charging-time control circuit for varying a charging time of said charging voltage based upon said duration of said first level of said charge-control clock such that said charging time of said charging voltage varies with a distance from said driver circuit to a scanned one of said plurality of scanning lines.
In the accompanying drawings, in which like reference numerals designate similar components throughout the figures, and in which:
The preferred embodiments of the present invention will now be described in detail referring to the drawings.
In the figures referred to for the explanation of embodiments, the components having the same function are given like reference numerals and the repetition of the explanation will be omitted.
Basic Configuration of a TFT Type Liquid Crystal Display Module to which the Present Invention is Applicable
In the liquid crystal module shown in
Configuration of the Liquid Crystal Display Panel 10 Shown in
Each pixel has thin film transistors (TFT1, TFT2). Source electrodes of the thin film transistors (TFT1, TFT2) of each pixel are connected to a pixel electrode (ITO1). A liquid crystal layer is provided between the pixel electrode (ITO1) and a common electrode (ITO2), and therefore an equivalent liquid-crystal-formed capacitance (CLC) formed by the liquid crystal layer is illustrated as connected between the pixel electrode (ITO1) and the common electrode (ITO2). Further, a storage capacitance (CADD) is connected between the source electrodes of the thin film transistors (TFT1, TFT2) and an immediately-preceding gate signal line (G).
In the example shown in
The present invention is applicable to both the two liquid crystal display panels illustrated in
In the liquid crystal display device of the vertical electric field type, the transmission of light at each pixel is controlled by a vertical electric field applied across a layer of a liquid crystal material sandwiched between a pair of opposing transparent electrodes formed on the inner surfaces of a pair of opposing transparent substrates. Each pixel is formed by two electrodes formed on the inner surfaces of the two opposing transparent substrates, respectively. For the purpose of device construction and operation, U.S. Pat. No. 3,918,796, issued to Fergason on Nov. 11, 1975, is hereby incorporated by reference.
In the liquid crystal display panel 10 shown in
The gate electrodes of thin film transistors (TFT1 TFT2) of all the pixels arranged in the same row are connected to the same gate signal line (G), and each gate signal line (G) is connected to the gate driver 140 which supplies the scanning drive voltage (positive or negative bias voltage) to the gate electrodes of thin film transistors (TFT1 TFT2) of each of the pixels arranged in a corresponding one of the rows during one horizontal scanning period.
Configuration of the Interface Section 100 Shown in
The display control device 110 shown in
Upon receipt of the display timing signal (DTMG), the display control device 110 judges it as a display start position and outputs a start pulse (a display-data-take-in start signal) to the first drain driver 130 via a signal line 135, and then outputs received display data corresponding to one row of pixels to the drain drivers 130 via a display data bus 133. At this time the display control device 110 outputs display-data-latch clocks (CL2) (hereinafter referred to simply as clocks (CL2) which serves as display control signals for latching display data, to a data latch circuit (not shown) of each of the drain drivers 130 via a signal line 131.
The display data sent from the computer main body are transmitted in the form of trios of red (R), green (G) and blue (B) display data each comprising six bits per pixel, for example, during a specified time.
Latching operation of the data latch circuit in the first drain driver 130 is controlled by the start pulse input to the first drain driver 130. After completion of the latching operation of the data latch circuit in the first drain driver 130 is over, a start pulse is output from the first drain driver 130 to the second drain driver 130, and the latching operation of the data latch circuit in the second drain driver 130 is controlled by the start pulse. Continuing in a like manner, the latching operation of the data latch circuits in successive drain drivers 130 is controlled such that the display data are properly written into the data latch circuits.
At a time when inputting of the display timing signal (DTMG) has been completed, or at a specified time after the inputting of the display timing signal (DTMG), the display control device judges that inputting of display data corresponding to one horizontal scanning line has been completed, and then the display control device 110 supplies to the respective drain drivers 130 via signal lines 132, output-timing-control clocks (CL1) (hereinafter referred to simply as the clocks (CL1)) which serve as display control signals for outputting gray scale voltages corresponding to the display data stored in the data latch circuits of the drain drivers 130, to the drain signal lines (D) of the liquid crystal display panel 10.
When the display control device 110 is supplied with the first display timing signal (DTMG) after the input of a vertical sync signal (Vsnc), the display control device 110 judges the first display timing signal (DTMG) as a time for the first display line and then outputs a frame start command signal (FLM) to one of the gate drivers 140 through a signal line 142.
Based on the horizontal sync (Hsync), the display control device 110 outputs clocks (CL3) which serve as shift clocks having a repetition period equal to one horizontal scanning period, to the gate drivers 140 via a signal line 141 such that the gate drivers 140 apply positive bias voltages to respective ones of the gate signal lines (G) of the liquid crystal display panel 10 successively with a horizontal scanning period. With this, a plurality of thin film transistors (TFT1 TFT2) connected to each of the gate signal lines (G) of the liquid crystal display panel 10 are conducting during one horizontal scanning period. The operation mentioned in the above display images on the liquid crystal display panel 10.
Configuration of the Power Supply Circuit 120 shown in
A power supply circuit 120 shown in
Configuration of Drain Drivers 130 Shown in
In
A shift register circuit 153 in a control circuit 152 of the drain driver 130 generates a data-take-in signal to be used in an input register circuit 154 based on a clock (CL2) supplied from the display control device 110 (see
Upon receipt of the clock (CL1) from the display control device 110, a storage register circuit 155 latches in the storage register circuit 155 the display data stored in the input register circuit 154. The display data taken in the storage register circuit 155 are input to the output circuit 157 via a level shift circuit 156.
The output circuit 157 selects gray scale voltages corresponding to display data from among the positive-polarity 64 gray scale voltages and negative-polarity 64 gray scale voltages, and outputs the selected gray scale voltages to corresponding ones of the drain signal lines (D).
In
A switch section (1) 262 and the switch section (2) 264 are controlled based on the ac-driving signal (M). Reference characters D1 to D6 denote the first to sixth drain signal lines (D), respectively.
In the drain driver 130 shown in
The following explains the decoder section 261 and the amplifier-pair circuit 263. A precharge control circuit (hereinafter referred to simply as the precharge circuit) 30 will be explained later.
The decoder section 261 includes a high-voltage decoder circuit 278 and a low-voltage decoder circuit 279. The high-voltage decoder circuit 278 selects positive-polarity gray-scale voltages corresponding to the display data supplied from respective data latch circuits 265 (to be more specific, the storage register 155 shown in
A pair of the high-voltage decoder circuit 278 and the low-voltage decoder circuit 279 are provided to a pair of adjacent data latch circuits 265. The amplifier-pair circuit 263 is composed of a high-voltage amplifier circuit 271 and a low-voltage amplifier circuit 272. The high-voltage amplifier circuit 271 receives positive-polarity gray-scale voltages generated in the high-voltage decoder circuit 278, current-amplifies the positive-polarity gray-scale voltages, and then outputs them. The low-voltage amplifier circuit 272 receives the negative-polarity gray-scale voltages generated in the low-voltage decoder circuit 279, current-amplifies the negative-polarity gray-scale voltages, and then outputs them.
In the dot-inversion driving method, the polarities of the gray scale voltages applied to the two adjacent drain signal lines D1, D4, for example for displaying the same color, respectively, are opposite from each other. An arrangement of the high-voltage amplifier circuits 271 and the low-voltage amplifier circuits 272 of the amplifier-pair circuits 263 is in the order of the high-voltage amplifier circuit 271→the low-voltage amplifier circuit 272→the high-voltage amplifier circuit 271→the low-voltage amplifier circuit 272.
Initially, by switching data-take-in signals inputted to the data latch circuit 265 by the switch section (1) 262, one of two display data inputted to the adjacent drain signal lines D1, D4, for example, respectively, for displaying the same color, the data for the drain signal line D1, for example, is inputted to a D1/D4 data latch in
Next, by switching the switch section (1) 262 such that the data for the drain signal line D1 is inputted to the D1/D4 data latch of the data latch circuit 265 connected to the low-voltage amplifier circuit 272, and the data for the drain signal line D4 is inputted to the D1/D4 data latch of the data latch circuit 265 connected to the high-voltage amplifier circuit 271, and at this time the switch section (2) 264 is set such that an output from the low-voltage amplifier circuit 272 is supplied to the drain signal line D1 and an output from the high-voltage amplifier circuit 271 is supplied to the drain signal line D4.
With the above configuration, the first drain signal line D1 and the fourth drain signal D4 are supplied with gray scale voltages of opposite polarities, respectively, and the polarities of the gray scale voltages supplied to the first and fourth drain signal lines are inverted periodically.
Operation of a Precharge Circuit 30
As shown in
The precharge circuits 30 are provided between the high-voltage decoder circuit 278 and the high-voltage amplifier circuit 271, and between the low-voltage decoder circuit 279 and the low-voltage amplifier circuit 272.
The precharge circuit 30 includes a transfer circuit (TG31) connected between the high-voltage decoder circuit 278 and the high-voltage amplifier circuit 271, and includes a transfer gate (TG32) connected between the low-voltage decoder circuit 279 and the low-voltage amplifier circuit 272. These transfer gate circuits (TG31, TG32) are controlled by control signals (DECT, DECN), and during a precharge period, the high-voltage decoder circuit 278 and the low-voltage decoder circuit 279 are respectively disconnected from the high-voltage amplifier circuit 271 and the low-voltage amplifier circuit 272. The precharge circuit 30 also includes transfer gate circuits (TG33, TG34).
These transfer gate circuits (TG33, TG34) are controlled by control signals (PRET, PREN), and during the precharge period the precharge circuit supplies a precharge voltage (hereinafter a high-voltage precharge voltage, e.g., an arbitrary positive-polarity gray-scale voltage) (VHpre) for application of positive-polarity gray-scale voltages, to the high-voltage amplifier circuit and also supplies a precharge voltage (hereinafter a low-voltage precharge voltage, e.g., an arbitrary negative-polarity gray-scale voltage) (VLpre) for application of negative-polarity gray-scale voltages, to the low-voltage amplifier circuit 272.
In the liquid crystal display module shown in
The operation of precharging the drain signal lines (D) by the high-voltage amplifier circuit 271 and the low-voltage amplifier circuit 272 are performed simultaneously with the decoding operation by the high-voltage decoder circuit 278 and the low-voltage decoder circuit 279.
After the termination of the precharge period, the high-voltage amplifier circuit 271 and the low-voltage amplifier circuit 272 track the outputs of the high-voltage decoder circuit 278 and the low-voltage decoder circuit 279, respectively, and supply the gray-scale voltages (VLCH, VLCL) corresponding to the display data to the drain signal lines (D), respectively.
In this way, by charging the drain signal line (D) with the high-voltage precharge voltage (VHpre) or the low-voltage precharge voltage (VLpre) during the precharge period, the potential of the drain signal line (D) can track quickly gray-scale voltages corresponding to the display data after the termination of the precharge period.
During the time interval when the control signal (HIZCNT) is at the H level, the control signals (ACKEP, ACKOP) are switched to a low level (hereinafter referred to as an L level), and the control signals (ACKEN, ACKON) are switched to a H level. Thereby, all the transfer gate circuits (TG1 to TG4) are switched off.
A control signal (PRECNT) shown in
The control signal (DECT) changes from the H level to the L level before the control signal (PREN) is switched from the H level to the L level. The control signal (DECN) changes from the L level to the H level before the control signal (PRET) is switched from L level to H level. Thereby, at first, the transfer gates (TG31, TG32) are switched off, and then, a time (tD1) after, the transfer gate circuits (TG33, TG34) are switched on.
The control signal (PREN) changes from the L level to the H level before the control signal (DECT) changes from the L level to the H level. The control signal (PRET) changes from the H level to the L level before the control signal (DECN) is switched from the H level to the L level. Thereby, at first, the transfer gate circuits (TG33, TG34) are switched off, and then, a time (tD2) after, the transfer gate circuits (TG31, TG32) are switched on.
As shown in
Voltage Value in the Precharge Circuit Shown in
As is apparent from
However, in a case where the midpoint of the positive-polarity gray scale voltage range is adopted as the high-voltage precharge voltage (VHpre), as shown in
Therefore, as shown in
Outline of the Present Invention
The liquid crystal display module shown in the present embodiments employs a two-line-inversion driving method.
The two-line-inversion driving method is similar to the dot inversion driving method explained in connection with
For example, in a case where a picture having an area of the same gray scale level ranging over several scanning lines is displayed on the liquid crystal display panel 10, with the two-line-inversion driving method, the drain driver 130 outputs gray scale voltages whose polarities are inverted every 2 scanning lines to the drain signal lines (D).
The following explains by referring to
Now consider a case where the polarity of the gray scale voltage supplied to the drain signal lines (D) from the drain driver 130 changes from negative to positive.
In this case, the gray scale voltages on the drain signal lines (D) are negative in polarity before the inversion of the polarities, and after the inversion of the polarities, the gray scale voltages become positive in polarity, but, since the drain signal lines (D) can be regarded as distributed constant lines, the gray scale voltages on the drain signal lines cannot change from negative to positive in polarity immediately, and consequently, the voltages on the drain signal lines (D) change from the negative-polarity gray scale voltages to the positive-polarity gray scale voltages after some time delay.
Therefore, even if a precharge voltage (Vpre) is applied to the drain signal lines (D) during a precharge period A indicated in
The above-explained phenomenon occurs when the drain driver 130 switches the polarity of the gray scale voltages for the drain signal lines (D) from positive to negative.
Therefore, even when pixels on the scanning line LINE 4 are intended to display the same gray scale level as pixels on the scanning line LINE 3 immediately after the polarity inversion, the voltage written into the pixels on the scanning line LINE 4 are not the same as the voltage written into the pixels on the scanning line LINE 3 with a voltage difference (VLCH−VLCHa) indicated in
The spurious horizontal lines become conspicuous when resolution of the liquid display panel 10 is increased as in the case of the SXGA display mode of 1280×1024 pixels, the UXGA display mode of 1600×1200 pixels, or the like.
As described in the above, the spurious horizontal lines occur due to the difference between the voltages written into pixels on the scanning line (LINE 3, for example) immediately after the polarity inversion and the voltages written into pixels on the scanning line (LINE 4, for example) succeeding the scanning line (LINE 3) immediately after the polarity inversion to the above scanning line (LINE 3).
In the present invention, as shown in
That is to say, the precharge period A for the scanning line (LINE 3) immediately after the inversion of voltage polarity is made longer than the precharge period B for the scanning line (LINE 4) succeeding the scanning line (LINE 3) immediately after the inversion of voltage polarity. This configuration makes it possible to charge the drain signal lines (D) to the precharge voltage (Vpre) during the precharge period A and the precharge period B shown in
Further, a duration of a high (H) level of a clock (CL1) for a scanning line farthest from the drain driver 130 is selected to be longest, and the durations of the H level of the clock (CL1) for the scanning lines are made successively shorter as the scanning lines approach the drain driver 130 such that the precharge period for the scanning lines becomes longer with increasing distance from the drain driver 130 to the scanning lines. By applying the precharge voltages of the above configuration on the drain signal lines (D), the charged voltage at the near-end portion of the drain signal line (D) proximate to the drain driver 130 is made equal to the charged voltage at the far-end portion of the drain signal line (D) farthest from the drain driver 130.
Features of the Liquid Crystal Display Module of the Embodiments in Accordance with the Present Invention
In this embodiment according to the present invention, for the purpose of making the precharge period A for the scanning line immediately after the inversion of voltage polarity longer than the precharge period B for the scanning line succeeding the scanning line immediately after the inversion of voltage polarity, the duration of the H level of the clock (CL1) for the precharge period A is made longer than that of the H level of the clock (CL1) for the precharge period B.
As explained in connection with
As shown in
The following explains the configuration of the display control device 110 for varying the duration of the clock (CL1) H level.
In a CL1 H-level width setting circuit 50 of the present embodiment, the number of clock pulses (hereinafter called the maximum number of clock pulses) of an external clock (DCLK) is set such that the maximum number of clock pulses corresponds to the maximum width (the width of the H level of a clock (CL1) required for the first (top) scanning line shown in
The following explains a method of generating an AC driving signal (M) in the present embodiment.
As shown in
The Qn output of the counter 62 is input to the exclusive OR circuit 63, and the output of the exclusive OR circuit is provided as the AC driving signal (M).
As explained above, in the present embodiment the precharge period A for the scanning line immediately after the inversion of voltage polarity is made longer than the precharge period B for the scanning line succeeding the scanning line immediately after the inversion of voltage polarity, thereby the voltages applied on pixels on the scanning line immediately after the inversion of voltage polarity is made equal to the voltages applied on pixels on the scanning line succeeding the scanning line immediately after the inversion of voltage polarity, and consequently, occurrence of the above-explained spurious horizontal lines is prevented.
Further, the duration of the H level of the clock (CL1) is made longest for the scanning line farthest from the drain driver 130, and the durations of the H level of the clock (CL1) for the respective scanning lines are made successively shorter with decreasing distance from the respective scanning lines to the drain driver 130 such that the precharge periods for the respective scanning lines are made longer with increasing distance from the respective scanning lines to the drain driver 130, and consequently, the charged voltage at the near-end portion of the drain signal line (D) proximate to the drain driver 130 can be made equal to the charged voltage at the far-end portion of the drain signal line (D) farthest from the drain driver 130. This prevents severe degradation in quality of a display on the liquid display panel caused by insufficiency of the voltage level for writing into the pixels at the far-end portion of the drain signal line farthest from the drain driver 130.
Further, in the present embodiment, the high-voltage precharge voltage (VHpre) can be selected to be a midpoint of the positive-polarity gray scale voltage range, and the low-voltage precharge voltage (VLpre) can be selected to be a midpoint of the negative-polarity gray scale voltage range.
However, the high-voltage precharge voltage (VHpre) can be selected to be a voltage displaced toward the maximum gray scale voltage from the midpoint of the positive-polarity gray scale voltage range, and the low-voltage precharge voltage (VLpre) can be selected to be a voltage displaced toward the maximum negative gray scale voltage from the midpoint of the negative-polarity gray scale voltage range. This configuration ensures more that the charged voltage at the far-end portion of the drain signal line (D) farthest from the drain driver 130 is made equal to the charged voltage at the near-end portion of the drain signal line (D) proximate to the drain driver 130.
The above description explained the embodiments in which the present invention is applied to the liquid crystal display panel of the vertical electric field type. However, the present invention is not limited to this and it can be applied to the liquid crystal display panel of the horizontal electric field type.
In the liquid crystal display device of the horizontal electric field type (commonly called the in-plane switching (IPS) type), the transmission of light at each pixel is controlled by a horizontal electric field applied in parallel with a layer of liquid crystal material sandwiched between a pair of opposing transparent substrates. Each pixel is formed by two electrodes formed on the inner surface of one of the opposing transparent substrates. For the purpose of device construction and operation, U.S. Pat. No. 5,598,285, issued to Kondo et al. on Jan. 28, 1997, is hereby incorporated by reference.
In the case of the liquid crystal display panel of the vertical electric field type shown in
The invention made by the present inventor has been explained concretely based on the preferred embodiments according to the present invention, but the present invention is not limited to the above-mentioned preferred embodiments, and they are illustrative and not restrictive, and various kinds of modifications may be made without departing from the scope and spirit of the invention.
The advantages provided by representative ones of the present inventions disclosed in the present specification will be simply explained in the following.
(1) In a case where the polarities of the gray-scale voltages are inverted every N (N≧2) scanning lines, the present invention is capable of preventing occurrence of spurious horizontal lines on a display screen and thereby improving quality of a display on the display screen.
(2) The present invention is capable of reducing a difference between a charged voltage at the near-end portion of the drain signal line proximate to the drain driver and a charged voltage at the far-end portion of the drain signal farthest from the drain driver, during the precharge period, as compared with the conventional technique, and thereby improving quality of a display on the display screen.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2002-007336 | Jan 2002 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5604511 | Ohi | Feb 1997 | A |
| 6307532 | Aoki | Oct 2001 | B1 |
| 6342876 | Kim | Jan 2002 | B1 |
| 6492970 | Furuhashi et al. | Dec 2002 | B1 |
| 6549187 | Matsubara et al. | Apr 2003 | B1 |
| 6628253 | Hiroki | Sep 2003 | B1 |
| 6842161 | Song et al. | Jan 2005 | B2 |
| 20040150612 | Okuzono et al. | Aug 2004 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20030132903 A1 | Jul 2003 | US |
