Patent Grant
8451205
The present invention relates to a liquid crystal display device for displaying an image by applying a voltage to liquid crystal, a method for driving the liquid crystal display device, and a television receiver.
A liquid crystal display device is a flat display device having excellent properties such as high definition, a flat shape, light weight, and low power consumption. Recently, due to an increase in display ability, an increase in production ability, and an increase in price competitiveness against other display devices, the market of the liquid crystal display device has spread rapidly.
An in-plane switching mode (IPS mode, see Patent Literature 1) and a multi-domain vertical aligned mode (MVA mode, see Patent Literature 2) in particular are applied to liquid crystal televisions as a liquid crystal display device of a wide viewing angle which is free from a problem such as a great decrease in a display contrast ratio and inversion of display gradations when a display surface is seen from a skew direction.
Although display quality of a liquid crystal display device has been improved, there appears a new problem of viewing angle dependency: a problem of difference in gamma characteristic when seen from a front and gamma characteristic when seen from a skew direction, i.e. a problem of viewing angle dependency in gamma characteristic. Gamma characteristic here indicates dependency of display luminance on gradations, and gamma characteristic being different between when seen from a front and when seen from a skew direction indicates that the state of gradation display varies depending on a direction in which the display surface is seen. This is problematic particularly when displaying an image such as photograph and when displaying television broadcasting etc.
The viewing angle dependency of gamma characteristic is more evident in the MVA mode than in the IPS mode. On the other hand, it is more difficult to produce a liquid crystal panel of the IPS mode with high contrast ratio when seen from the front than to produce a liquid crystal panel of the MVA mode with high contrast ratio when seen from the front. In view of the above, it is desirable to improve viewing angle dependency of gamma characteristic in the liquid crystal display device of the MVA mode in particular.
With respect to this problem, Patent Literature 3 discloses a liquid crystal display device and a driving method thereof, each capable of improving viewing angle dependency in gamma characteristic, excess brightness characteristic in particular, by separating one pixel into a plurality of sub-pixels with different brightness. Such display or driving is referred to as area coverage modulation display, area coverage modulation drive, multi-pixel display, or multi-pixel drive.
To be specific, an auxiliary capacitor (Cs) is provided for each of a plurality of sub-pixels (SP) in one pixel (P), and an auxiliary capacitor counter electrode (connected with a CS bus line) constituting the auxiliary capacitor is electrically independent with respect to each sub-pixel. By changing a voltage to be supplied to the auxiliary capacitor counter electrode (the voltage may be referred to as an auxiliary capacitor counter voltage, an auxiliary capacitor signal voltage, an auxiliary capacitor signal, or a CS signal), effective voltages applied on individual liquid crystal layers of the plurality of sub-pixels are made different with use of a capacitive divider.
However, if the multi-pixel structure described in Patent Literature 3 is applied to a liquid crystal television with high definition or with a large size, cycle of oscillation of an oscillating voltage gets shorter as a display panel has higher definition or larger size. This raises a problem such as difficulty in preparation of a circuit for generating an oscillating voltage, an increase in power consumption, greater influence of rounding of a waveform due to electric load impedance of a CS bus line. With respect to this problem, Patent Literature 4 discloses providing a plurality of CS main lines that are electrically independent from each other and connecting a plurality of CS bus lines with each of the CS main lines so as to lengthen a cycle of oscillation of an oscillating voltage to be applied to an auxiliary capacitor counter electrode via the CS bus line.
If a current voltage continues to be applied to a liquid crystal layer of such liquid crystal display device for a long time, elements get deteriorated. Therefore, in order to secure a long life of such liquid crystal display device, it is necessary to perform alternating driving (inversion driving) in which the polarity of a voltage to be applied is inverted periodically. However, in a case where an active matrix liquid crystal display device employs frame inversion driving in which the polarity of a voltage is inverted with respect to each frame, it is inevitable that some unbalance is seen in a plus/minus voltage to be applied to liquid crystal due to anisotropy of liquid crystal dielectric constant, variation in pixel potential that is caused by parasitic capacitance between a gate and a source of a pixel TFT, and a slip of a center value of a counter electrode signal. Consequently, a minor variation in luminance occurs at a frequency that is a half of a frame frequency, making a user see flickers. In order to solve this problem, there is generally employed inversion driving in which pixel signals have opposite polarities between adjacent lines or adjacent pixels as well as voltages are inverted with respect to each frame.
When dot inversion in which the polarity of a voltage is inverted with respect to each pixel is performed, a charging rate of a pixel drops due to signal delay in a data signal line. In order to solve this problem, there is proposed a technique for inverting the polarity of a data signal voltage with respect to a plurality of horizontal periods (a plurality of rows). However, this technique still raises a problem that a charging rate of a pixel drops at a row where the polarity of a data signal voltage is inverted.
In order to solve this problem, Patent Literature 5 discloses a technique in which a dummy horizontal period is provided after inversion of the polarity of a data signal and gate-on pulses whose pulse width corresponds to a plurality of horizontal periods are applied to all scanning signal lines in such a manner that the gate-on pulses have the same pulse width.
Further, Patent Literature 6 discloses a technique in which the width of a gate-on pulse after inversion of the polarity of a data signal is made larger than the width of a gate-on pulse with no inversion of the polarity of a data signal so as to increase a charging rate of a first row where the polarity of the data signal is inverted.
Patent Literature 1
Patent Literature 2
Patent Literature 3
Patent Literature 4
Patent Literature 5
Patent Literature 6
However, in a case where a dummy horizontal period is provided in the multi-pixel drive, there is a possibility that a polarity inversion cycle of a data signal varies depending on timing, which results in disparity between the polarity inversion cycle of a data signal and a polarity inversion cycle of a retention capacitor signal. In this case, writing data in a pixel when the waveform of the retention capacitor signal is rounded may cause display unevenness.
The present invention was made in view of the foregoing problems. An object of the present invention is to provide a liquid crystal display device, a liquid crystal display device drive method and a television receiver, each capable of displaying a high-quality image with subdued display unevenness, without being influenced by the rounding of a data signal waveform and the rounding of a retention capacitor signal when inverting the polarity.
In order to solve the foregoing problem, the liquid crystal display device of the present invention is an active-matrix liquid crystal display device, including: scanning signal lines extending in a row direction; data signal lines extending in a column direction; retention capacitor lines extending in a row direction; a first transistor and a second transistor that are provided near each of intersections of the scanning signal lines and the data signal lines and that are connected with each of the scanning signal lines and each of the data signal lines; and pixel regions each including a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode being connected with the first transistor and the second sub-pixel electrode being connected with the second transistor, the first sub-pixel electrode and the second sub-pixel electrode being connected with different ones of the retention capacitor lines to form retention capacitors, respectively, the scanning signal lines being divided into one or more blocks, and scanning signal lines included in each block being divided into a first group consisting of odd scanning signal lines and a second group consisting of even scanning signal lines, the liquid crystal display device comprising: a scanning signal driving section for sequentially scanning blocks of scanning signal lines and sequentially scanning groups of scanning signal lines in each block such that the scanning signal lines in each block are interlace-scanned, so as to sequentially apply gate-on pulses on the scanning signal lines, each of the gate-on pulses causing one of the scanning signal lines to be in a selected state; a data signal driving section for applying, on the data signal lines, data signals whose polarities are switched with predetermined timing; and a retention capacitor signal driving section for applying, on the retention capacitor lines, retention capacitor signals whose polarities are switched with predetermined timing, the data signal driving section providing a dummy insertion period right after a moment of polarity inversion of a data signal and causing a polarity of a data signal applied on a data signal line during the dummy insertion period to be equal to a polarity of a data signal applied on the data signal line during a horizontal period right after the dummy insertion period, and the retention capacitor signal driving section causing polarity inversion timing of individual retention capacitor signals at least in an adjacent line writing time difference period to be equal among successive frames, the adjacent line writing time difference period being a period from a moment of application of a gate-on pulse on a scanning signal line that is one of adjacent two scanning signal lines and that belongs to a first group or a second group firstly subjected to application of a gate-on pulse to a moment of application of a gate-on pulse on a scanning signal line that is the other of the adjacent two scanning signal lines and that belongs to a second group or a first group secondly subjected to application of a gate-on pulse.
In order to solve the foregoing problem, the method of the present invention for driving a liquid crystal display device is a method for driving an active-matrix liquid crystal display device, including: scanning signal lines extending in a row direction; data signal lines extending in a column direction; retention capacitor lines extending in a row direction; a first transistor and a second transistor that are provided near each of intersections of the scanning signal lines and the data signal lines and that are connected with each of the scanning signal lines and each of the data signal lines; and pixel regions each including a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode being connected with the first transistor and the second sub-pixel electrode being connected with the second transistor, the first sub-pixel electrode and the second sub-pixel electrode being connected with different ones of the retention capacitor lines to form retention capacitors, respectively, the scanning signal lines being divided into one or more blocks, and scanning signal lines included in each block being divided into a first group consisting of odd scanning signal lines and a second group consisting of even scanning signal lines, the method comprising: (i) sequentially scanning blocks of scanning signal lines and sequentially scanning groups of scanning signal lines in each block such that the scanning signal lines in each block are interlace-scanned, so as to sequentially apply gate-on pulses on the scanning signal lines, each of the gate-on pulses causing one of the scanning signal lines to be in a selected state; (ii) applying, on the data signal lines, data signals whose polarities are switched with predetermined timing; and (iii) applying, on the retention capacitor lines, retention capacitor signals whose polarities are switched with predetermined timing, in the step (ii), a dummy insertion period being provided right after a moment of polarity inversion of a data signal and a polarity of a data signal applied on a data signal line during the dummy insertion period being caused to be equal to a polarity of a data signal applied on the data signal line during a horizontal period right after the dummy insertion period, and in the step (iii), polarity inversion timing of individual retention capacitor signals at least in an adjacent line writing time difference period being caused to be equal among successive frames, the adjacent line writing time difference period being a period from a moment of application of a gate-on pulse on a scanning signal line that is one of adjacent two scanning signal lines and that belongs to a first group or a second group firstly subjected to application of a gate-on pulse to a moment of application of a gate-on pulse on a scanning signal line that is the other of the adjacent two scanning signal lines and that belongs to a second group or a first group secondly subjected to application of a gate-on pulse.
With the arrangement or the method, the dummy insertion period is provided right after the moment of polarity inversion (of a data signal, and the polarity of a data signal applied on the data signal line during the dummy insertion period is equal to the polarity of a data signal applied on the data signal line during a horizontal period right after the dummy insertion period. This allows reducing drop in a pixel charging ratio due to rounding of a waveform of a data signal that is caused when inverting the polarity. This allows high-quality display with subdued display unevenness.
Further, as described above, in a case where a dummy insertion period is inserted, there is a possibility that a polarity inversion cycle of a data signal varies depending on timing, which results in disparity between the polarity inversion cycle of a data signal and a polarity inversion cycle of a retention capacitor signal. In contrast thereto, with the above configuration of the present invention, polarity inversion timing of individual retention capacitor signals at least in an adjacent line writing time difference period is caused to be equal among successive frames. This allows the polarity inversion timing of the retention capacitor signal to be in synchronization with the moments of applying gate-on pulses on all the scanning signal lines. Consequently, it is possible to prevent display unevenness due to rounding of a waveform of a CS signal.
An active-matrix liquid crystal display device, including: scanning signal lines extending in a row direction; data signal lines extending in a column direction; retention capacitor lines extending in a row direction; a first transistor and a second transistor that are provided near each of intersections of the scanning signal lines and the data signal lines and that are connected with each of the scanning signal lines and each of the data signal lines; and pixel regions each including a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode being connected with the first transistor and the second sub-pixel electrode being connected with the second transistor, the first sub-pixel electrode and the second sub-pixel electrode being connected with different ones of the retention capacitor lines to form retention capacitors, respectively, the scanning signal lines being divided into one or more blocks, and scanning signal lines included in each block being divided into a first group consisting of odd scanning signal lines and a second group consisting of even scanning signal lines, the liquid crystal display device comprising: a scanning signal driving section for sequentially scanning blocks of scanning signal lines and sequentially scanning groups of scanning signal lines in each block such that the scanning signal lines in each block are interlace-scanned, so as to sequentially apply gate-on pulses on the scanning signal lines, each of the gate-on pulses causing one of the scanning signal lines to be in a selected state; a data signal driving section for applying, on the data signal lines, data signals whose polarities are switched with predetermined timing; and a retention capacitor signal driving section for applying, on the retention capacitor lines, retention capacitor signals whose polarities are switched with predetermined timing, the data signal driving section providing a dummy insertion period right after a moment of polarity inversion of a data signal and causing a polarity of a data signal applied on a data signal line during the dummy insertion period to be equal to a polarity of a data signal applied on the data signal line during a horizontal period right after the dummy insertion period, and the retention capacitor signal driving section causing polarity inversion cycles of all of the retention capacitor signals to be equal at least in an adjacent line writing time difference period, the adjacent line writing time difference period being a period from a moment of application of a gate-on pulse on a scanning signal line that is one of adjacent two scanning signal lines and that belongs to a first group or a second group firstly subjected to application of a gate-on pulse to a moment of application of a gate-on pulse on a scanning signal line that is the other of the adjacent two scanning signal lines and that belongs to a second group or a first group secondly subjected to application of a gate-on pulse.
A method for driving an active-matrix liquid crystal display device, including: scanning signal lines extending in a row direction; data signal lines extending in a column direction; retention capacitor lines extending in a row direction; a first transistor and a second transistor that are provided near each of intersections of the scanning signal lines and the data signal lines and that are connected with each of the scanning signal lines and each of the data signal lines; and pixel regions each including a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode being connected with the first transistor and the second sub-pixel electrode being connected with the second transistor, the first sub-pixel electrode and the second sub-pixel electrode being connected with different ones of the retention capacitor lines to form retention capacitors, respectively, the scanning signal lines being divided into one or more blocks, and scanning signal lines included in each block being divided into a first group consisting of odd scanning signal lines and a second group consisting of even scanning signal lines, the method comprising: (i) sequentially scanning blocks of scanning signal lines and sequentially scanning groups of scanning signal lines in each block such that the scanning signal lines in each block are interlace-scanned, so as to sequentially apply gate-on pulses on the scanning signal lines, each of the gate-on pulses causing one of the scanning signal lines to be in a selected state; (ii) applying, on the data signal lines, data signals whose polarities are switched with predetermined timing; and (iii) applying, on the retention capacitor lines, retention capacitor signals whose polarities are switched with predetermined timing, in the step (ii), a dummy insertion period being provided right after a moment of polarity inversion of a data signal and a polarity of a data signal applied on a data signal line during the dummy insertion period being caused to be equal to a polarity of a data signal applied on the data signal line during a horizontal period right after the dummy insertion period, and in the step (iii), polarity inversion cycles of all of the retention capacitor signals being caused to be equal at least in an adjacent line writing time difference period, the adjacent line writing time difference period being a period from a moment of application of a gate-on pulse on a scanning signal line that is one of adjacent two scanning signal lines and that belongs to a first group or a second group firstly subjected to application of a gate-on pulse to a moment of application of a gate-on pulse on a scanning signal line that is the other of the adjacent two scanning signal lines and that belongs to a second group or a first group secondly subjected to application of a gate-on pulse.
With the arrangement or the method, the dummy insertion period is provided right after the moment of polarity inversion of a data signal, and the polarity of a data signal applied on the data signal line during the dummy insertion period is equal to the polarity of a data signal applied on the data signal line during a horizontal period right after the dummy insertion period. This allows reducing drop in a pixel charging ratio due to rounding of a waveform of a data signal that is caused when inverting the polarity. This allows high-quality display with subdued display unevenness.
Further, as described above, in a case where a dummy insertion period is inserted, there is a possibility that a polarity inversion cycle of a data signal varies depending on timing, which results in disparity between the polarity inversion cycle of a data signal and a polarity inversion cycle of a retention capacitor signal. In contrast thereto, with the above configuration of the present invention, polarity inversion timing of individual retention capacitor signals at least in an adjacent line writing time difference period is caused to be equal among successive frames. This allows the polarity inversion timing of the retention capacitor signal to be in synchronization with the moments of applying gate-on pulses on all the scanning signal lines. Consequently, it is possible to prevent display unevenness due to rounding of a waveform of a CS signal.
The liquid crystal display device of the present invention may be arranged so that the data signal driving section provides a dummy insertion period right after a moment of polarity inversion of a data signal and causes a data signal applied on a data signal line during the dummy insertion period to be equal to a data signal applied on the data signal line during a horizontal period right after the dummy insertion period.
The method of the present invention may be arranged so that in the step (ii), a dummy insertion period is provided right after a moment of polarity inversion of a data signal and a data signal applied on a data signal line during the dummy insertion period is caused to be equal to a data signal applied on the data signal line during a horizontal period right after the dummy insertion period.
With the arrangement or the method, the data signal applied on a data signal line during the dummy insertion period is equal to the data signal applied on the data signal line during a horizontal period right after the dummy insertion period. This makes it unnecessary to newly generate a data signal to be inserted during the dummy insertion period, easily realizing insertion of the dummy insertion period. Further, it is easy to cause the polarity of a data signal applied on the data signal line during the dummy insertion period to be equal to the polarity of a data signal applied on the data signal line during a horizontal period right after the dummy insertion period.
The liquid crystal display device of the present invention may be arranged so that the scanning signal driving section does not apply the gate-on pulse during the dummy insertion period.
However, the technique disclosed in Patent Literature 5 is problematic in that since a pixel charged when the polarity of a data signal is inverted is charged during a period when rounding of a data signal waveform is great, it is impossible to completely improve a difference in charging rate between the pixel charged when the polarity of a data signal is inverted and a pixel charged during the same gate-on time when the polarity of a data signal is not inverted.
Further, in the technique disclosed in Patent Literature 6, a pixel charged when the polarity of a data signal is inverted is charged during a period when rounding of a data signal waveform is great. Besides, since the amount of delay of a data signal differs according to positions of a display area, rounding of a waveform of a data signal also differs depending on positions of the display area. Consequently, even if a gate-on pulse is lengthened after the polarity of a data signal is inverted, it is impossible to evenly improve display unevenness in the display area due to the difference in a charging property. This problem is particularly evident in a large liquid crystal display device with high definition, and further particularly evident in a case where image writing frequency is made higher (e.g. 120 Hz) in order to increase visibility of a moving image.
On the other hand, with the above configuration of the present invention, the dummy insertion period in which the gate-on pulse is not applied to the scanning signal line is provided right after the moment of polarity inversion of a data signal. This prevents a pixel from being charged during a period in which the rounding of a waveform of a data signal due to polarity inversion is great. This allows further effectively preventing display unevenness etc.
The liquid crystal display device of the present invention may be arranged so that the number of the blocks of scanning signal lines is one, and the data signal driving section applies the data signals on the data signal lines such that a polarity of a data signal is inverted at a moment of switching groups of scanning signal lines to be scanned.
The arrangement realizes driving in which the polarity of a data signal is inverted with respect to each data signal line.
The liquid crystal display device of the present invention may be arranged so that the number of the blocks of scanning signal lines is two or more, and the data signal driving section applies the data signals on the data signal lines such that a polarity of a data signal is inverted at a moment of switching groups of scanning signal lines to be scanned.
With the arrangement, the scanning signal lines are separated into a plurality of blocks, and scanning signal lines of each block are subjected to interlace scan driving. This case allows reducing a difference in scanning timing between groups of each block, compared with a case where all of scanning signal lines are subjected to interlace scan driving. Consequently, it is possible to prevent later-mentioned combing, and therefore it is possible to further increase display quality.
The liquid crystal display device of the present invention may be arranged so that a polarity inversion cycle of a retention capacitor signal is obtained by dividing the adjacent line writing time difference period by k (k is an integer of 1 or more).
With the arrangement, during the adjacent line writing time difference period, the polarity of a retention capacitor signal is inverted even times (2k (k is an integer of 1 or more). This keeps bright-dark state of a sub-pixel constant, preventing decrease in display quality. This allows inverting the order of brightness and darkness of individual sub-pixels aligned in a column direction with respect to every line, and thus prevents jaggyness.
The liquid crystal display device of the present invention may be arranged so that k is 1.
With the arrangement, a polarity inversion cycle of a retention capacitor signal is ½ of the adjacent line writing time difference period. In this case, the polarity inversion cycle of the retention capacitor signal is longest. Therefore, applying a gate-on pulse after inversion of the polarity of the retention capacitor signal and right before next inversion allows writing data into individual sub-pixels at a moment when the waveform of the retention capacitor signal gets sufficiently gentle.
The liquid crystal display device of the present invention may be arranged so that also in a period other than the adjacent line writing time difference period, a polarity of a retention capacitor signal is periodically inverted with a polarity inversion cycle of the adjacent line writing time difference period.
With the arrangement, the polarity of the retention capacitor signal is inverted periodically with a predetermined polarity inversion cycle in all periods. Consequently, a retention capacitor signal to be applied to one retention capacitor line can be used as a retention capacitor signal to be applied to another retention capacitor line. Therefore, it is possible to drive all retention capacitor lines with fewer kinds of retention capacitor signals.
The liquid crystal display device of the present invention may be arranged so that a polarity continuation period of a retention capacitor signal during a period to which the dummy insertion period is inserted is longer by the dummy insertion period than a polarity continuation period of a retention capacitor signal during a period other than the period to which the dummy insertion period is inserted, the polarity continuation period being a period during which one polarity of a retention capacitor signal continues.
The liquid crystal display device of the present invention may be arranged so that a polarity continuation period of a retention capacitor signal is either a polarity continuation period with a first length or a polarity continuation period with a second length that is a sum of the first length and a length of the dummy insertion period, the polarity continuation period being a period during which one polarity of a retention capacitor signal continues.
The arrangement increases a possibility that a retention capacitor signal to be applied to one retention capacitor line can be used as a retention capacitor signal to be applied to another retention capacitor line. Therefore, it is possible to drive all retention capacitor lines with fewer kinds of retention capacitor signals.
The liquid crystal display device of the present invention may be arranged so that when supplying a retention capacitor signal to retention capacitor lines to which retention capacitor signals with a same phase are applied, the retention capacitor signal driving section supplies the retention capacitor signal via one retention capacitor signal supply line.
With the arrangement, when supplying a retention capacitor signal to retention capacitor lines to which retention capacitor signals with a same phase are applied, the retention capacitor signal is applied via one retention capacitor signal supply line. This allows reducing the number of retention capacitor signal supply lines. This allows simplifying the configuration of the liquid crystal display device and downsizing the liquid crystal display device.
The liquid crystal display device of the present invention may be arranged so that the retention capacitor signal driving section applies retention capacitor signals with a same phase on a plurality of retention capacitor signal supply lines.
With the arrangement, it is possible to reduce the number of retention capacitor signal supply lines. This allows simplifying the configuration of the liquid crystal display device and downsizing the liquid crystal display device.
The liquid crystal display device of the present invention may be arranged so that the dummy insertion period is a multiple number of a horizontal period.
With the arrangement, the dummy insertion period is a multiple number of a horizontal period, and therefore it is possible to drive a data signal and a scanning signal with the length of 1 horizontal period as a unit. Consequently, a conventional clock signal can be used as a clock signal in accordance with which a data signal and a scanning signal are driven. This allows simplifying the configuration of the liquid crystal display device.
The liquid crystal display device of the present invention may be arranged so that a phase of a retention capacitor signal to be applied on n+2nd retention capacitor line is delayed by 1 horizontal period with respect to a phase of a retention capacitor signal to be applied on nth retention capacitor line.
With the arrangement, the retention capacitor signal is delayed by 1 horizontal period with respect to every two retention capacitor lines. This allows all retention capacitor lines to write data into individual sub-pixels after the same time has elapsed from inversion of the polarity of the retention capacitor signal and at a moment when the waveform of the retention capacitor signal gets sufficiently gentle. Therefore, it is possible to prevent display unevenness due to rounding of the waveform of the retention capacitor signal.
The liquid crystal display device of the present invention may be arranged so that the retention capacitor signal driving section generates m kinds of retention capacitor signals, drives two retention capacitor lines with one retention capacitor line therebetween with use of retention capacitor signals with a same phase, and regards at least one polarity continuation period as a (k×m) horizontal period, and a phase of a retention capacitor signal to be applied on (n+2(k+1))th retention capacitor line is delayed by (k+1) horizontal period with respect to a phase of a retention capacitor signal to be applied on nth retention capacitor line.
With the arrangement, it is possible to lengthen a polarity continuation period of a retention capacitor signal without increasing the number of retention capacitor signal supply lines. That is, it is possible to increase a reaching ratio of a retention capacitor signal voltage at a moment of gate-off without providing additional lines and circuits. This allows reducing display unevenness due to rounding of an actual waveform of a retention capacitor signal voltage. Further, this allows retention capacitor lines to write data into individual sub-pixels after the same time has elapsed from inversion of the polarity of the retention capacitor signal and at a moment when the waveform of the retention capacitor signal gets sufficiently gentle. Therefore, it is possible to prevent display unevenness due to rounding of the waveform of the retention capacitor signal.
The liquid crystal display device of the present invention may be arranged so that polarity continuation periods are equal with one another, each of the polarity continuation periods being a period in which a polarity of a retention capacitor signal continues.
With the arrangement, a polarity continuation period of one polarity is equal to a polarity continuation period of the other polarity in the waveform of the retention capacitor signal. This allows making an effective potential substantially equal among individual sub-pixels. Therefore, it is possible to prevent striped display unevenness.
The liquid crystal display device of the present invention may be arranged so as to further include a display control circuit for supplying, to the data signal driving section, a data signal and a data signal application control signal for controlling timing with which the data signal driving section applies the data signal on a data signal line, a plurality of video data that respectively correspond to data signal lines being sequentially supplied from an external signal source to the display control circuit with an interval between the plurality of video data, and the display control circuit regards certain number of video data as a set in accordance with polarity inversion, inserts dummy data at a predetermined position of the set, assigns a dummy insertion period to an output of a signal potential corresponding to the dummy data, and assigns a horizontal period shorter than the interval to an output of a signal potential corresponding to each video data.
By setting one horizontal period during which a signal potential corresponding to individual video data is output to be shorter than an interval for inputting individual video data (horizontal period set to input data sequence) as described above, it is possible to create, from the sum total of times resulting from the shortening, a dummy insertion period for outputting dummy data. This allows inserting dummy data to input video data and assigning a dummy insertion period to the dummy data, without increasing a vertical display period. Further, it is also possible to prevent an increase in difference of time between data input and data output, allowing reduction of memory (buffer) usage.
The liquid crystal display device of the present invention may be arranged so that a product of the number of video data in a set and the interval is equal to a sum of a whole dummy insertion period assigned to dummy data in the set and a whole horizontal period assigned to the video data in the set.
This allows providing (inserting) a dummy insertion period without changing a vertical display period (without reducing a vertical blanking period). Further, since difference of time between data input and data output does not increase, it is possible to further reduce memory (buffer) usage.
The liquid crystal display device of the present invention may be arranged so that the display control circuit inserts dummy data at a head of each set.
This enables accurate display without skip of data, even when the liquid crystal display device is designed such that a pixel is not charged during a period in which the rounding of a data signal waveform due to polarity inversion is great.
The liquid crystal display device of the present invention may be arranged so as to further include a display control circuit for supplying, to the data signal driving section, a data signal and a data signal application control signal for controlling timing with which the data signal driving section applies the data signal on a data signal line, a plurality of video data that respectively correspond to data signal lines being sequentially supplied from an external signal source to the display control circuit with an interval between the plurality of video data, and the display control circuit regards certain number of video data as a set in accordance with polarity inversion, assigns one or more dummy insertion periods as well as one horizontal period to an output of a signal potential corresponding to predetermined video data in each set, and assigns a horizontal period shorter than the interval to outputs of signal potentials respectively corresponding to individual video data other than the predetermined video data in each set.
By setting one horizontal period in an actual output to be shorter than an interval for inputting individual video data (horizontal period set to input data sequence) as described above, it is possible to create, from the sum total of times resulting from the shortening, a time for a dummy insertion period. This allows providing a dummy insertion period, without increasing a vertical display period. Further, it is also possible to prevent an increase in difference of time between data input and data output, allowing reduction of memory (buffer) usage.
The liquid crystal display device of the present invention may be arranged so that a product of the number of video data in each set and the interval is equal to a sum of a whole horizontal period assigned to the predetermined video data in each set, a whole dummy insertion period assigned to the predetermined video data in each set, and a whole horizontal period assigned to the individual video data other than the predetermined video data in each set.
This allows providing a dummy scanning period without changing a vertical display period (without reducing a vertical blanking period). Further, since difference of time between data input and data output does not increase, it is possible to further reduce memory (buffer) usage.
The liquid crystal display device of the present invention may be arranged so that the predetermined video data in each set is first data in each set.
This enables accurate display without skip of data, even when the liquid crystal display device is designed such that a pixel is not charged during a period in which the rounding of a data signal waveform due to polarity inversion is great.
The liquid crystal display device of the present invention may be arranged so that the dummy insertion period is shorter than the interval.
The liquid crystal display device of the present invention may be arranged so that the dummy insertion period is equal to one horizontal period. This makes individual scanning periods (dummy insertion period, horizontal period) equal with one another, simplifying a signal process or a configuration for the signal process.
The liquid crystal display device of the present invention may be arranged so that the dummy insertion period is shorter than one horizontal period. This allows a horizontal period to be longer, resulting in a higher charging ratio of a pixel.
The liquid crystal display device of the present invention may be arranged so that the dummy insertion period is longer than one horizontal period. Consequently, in a configuration in which the polarity of a signal potential is inverted with respect to each set, it is possible to increase a charging ratio of a data signal line right after polarity inversion.
The liquid crystal display device of the present invention may be arranged so that the retention capacitor signal driving section provides, in a polarity continuation period of a retention capacitor signal, a period during which a first voltage is applied and a period during which a second voltage of a same polarity as the first voltage and with a larger absolute value than the first voltage is applied.
With the arrangement, it is possible to improve rounding of a waveform at rise or fall of a pulse of a retention capacitor signal. In other words, even when a time from a moment of polarity inversion of a retention capacitor signal to gate-off timing is short, it is possible to increase a reaching ratio of a retention capacitor signal voltage at gate-off timing. This allows reducing a difference in reaching ratio between voltages of retention capacitor signals, which difference is caused by a difference in time from rise or fall of a retention capacitor signal to gate-off timing. Further, even when the period from rise or fall of a retention capacitor signal to gate-off timing is short in one row and long in the other row, it is possible to prevent display unevenness due to a difference in a reaching ratio of a retention capacitor signal voltage.
The liquid crystal display device of the present invention may be arranged so that in accordance with a length of a polarity inversion cycle of a retention capacitor signal, the retention capacitor signal driving section changes at least one of the period in which the second voltage is applied and timing of applying the second voltage.
With the arrangement, when a reacting ratio of a voltage of a retention capacitor signal differs depending on the length of a polarity inversion cycle, this difference can be cancelled by changing at least one of the period in which the second voltage is applied and timing of applying the second voltage.
The liquid crystal display device of the present invention may be arranged so that the number of scanning signal lines in one block is α (α is a natural number), a dummy insertion period is inserted at two or more positions while scanning one block, and the retention capacitor lines are driven in response to retention capacitor signals with at least α/k (k is a natural number and α/k is an integer)+2 phases.
With the arrangement, the number of scanning signal lines in one block is α (α is a natural number). Accordingly, by supplying a retention capacitor signal via one retention capacitor signal supply line to retention capacitor lines to which retention capacitor signals with a same polarity are applied, it is possible to drive the retention capacitor lines with use of retention capacitor signals with n phases. However, in this case, a time from a moment when a gate-on pulse gets off to a moment when the polarity of a retention capacitor signal is inverted at a portion to which a dummy insertion period is inserted is greatly different from the time in other line. This causes display unevenness. On the other hand, with the arrangement, the phases of retention capacitor signals are at least α/k+2 phases. Therefore, it is possible to apply a suitable retention capacitor signal at a portion to which a dummy insertion period is inserted. This allows preventing the display unevenness.
The liquid crystal display device of the present invention may be arranged so that the number of scanning signal lines in one block is α (α is a natural number), two retention capacitor lines with one retention capacitor line therebetween of first half α/2 (α/2 is a natural number) retention capacitor lines in each block are driven in response to retention capacitor signals with a same phase, and two retention capacitor lines with one retention capacitor line therebetween of second half α/2 retention capacitor lines in each block are driven in response to retention capacitor signals with a same phase, so that all of the retention capacitor lines are driven in response to retention capacitor signals with at least α/2k (k is an integer of 2 or more and α/2k is an integer) phases.
With the arrangement, it is possible to reduce the number of phases of necessary retention capacitor signals without shortening a polarity continuation period of a retention capacitor signal. This allows increasing a reaching ratio of a voltage of a retention capacitor signal at a moment of gate-off without providing additional lines and circuits. This allows reducing display unevenness due to the rounding of an actual waveform of the voltage of the retention capacitor signal.
The liquid crystal display device of the present invention may be arranged so that during a period including a dummy insertion period, in which one block is scanned, a difference between a period in which a retention capacitor signal is in H level and a period in which the retention capacitor signal is in L level is equal to or less than 1 horizontal period.
With the arrangement, it is possible to reduce a difference between the H level of a retention capacitor signal and the L level of the retention capacitor signal in 1 frame regardless of timing for applying a gate-on pulse. Consequently, deviation in time required for steep rise/fall of a voltage applied on a pixel electrode due to a change in H and L levels of a retention capacitor signal is prevented. This prevents a difference in luminance between rows of bright and dark sub-pixels, allowing prevention of display unevenness.
The liquid crystal display device of the present invention may be arranged so that during a period including a dummy insertion period, in which one block is scanned, a ratio of a difference between a period in which a retention capacitor signal is in H level and a period in which the retention capacitor signal is in L level to 1 frame period is equal to or less than 0.13% and more preferably equal to or less than 0.09%.
With the arrangement, deviation in time required for steep rise/fall of a voltage applied on a pixel electrode due to a change in H and L levels of a retention capacitor signal in a retention capacitor line is prevented regardless of the number of driving frequencies and the number of scanning lines. This prevents a difference in luminance between rows of bright and dark sub-pixels, allowing prevention of display unevenness.
Further, it is possible to produce a television receiver including the liquid crystal display device of the present invention and a tuner section for receiving television broadcasting.
One embodiment of the present invention is described below with reference to the attached drawings.
(Structure of Liquid Crystal Display Device)
The display section 100 in the liquid crystal display device includes gate lines GL1-GLm that are a plurality of (m) scanning signal lines, source lines SL1-SLn that are a plurality of (n) data signal lines each intersecting each of the gate lines GL1-GLm, and a plurality of (m×n) pixel formation sections provided respectively at intersections of the gate lines GL1-GLm and the source lines SL1-SLn. The pixel formation sections are disposed in a matrix manner so as to form pixel arrays. Hereinafter, a direction in which a gate line extends in a pixel array is referred to as a row direction and a direction in which a source line extends in a pixel array is referred to as a column direction.
Each pixel formation section includes: a TFT 10 serving as a switching element whose gate terminal is connected with a gate line GLj that crosses a corresponding intersection and whose source terminal is connected with a source line SLi that crosses the intersection; a pixel electrode connected with a drain terminal of the TFT 10; a common electrode Ec serving as a counter electrode provided commonly for the plurality of pixel formation sections; and a liquid crystal layer that is provided commonly for the plurality of pixel formation sections and that is sandwiched between the pixel electrode and the common electrode Ec. A liquid crystal capacitor formed by the pixel electrode and the common electrode Ec serves as a pixel capacitor Cp. In general, an auxiliary capacitor (retention capacitor) is provided in parallel with a liquid crystal capacitor in order that a pixel capacitor retains a voltage surely. However, the auxiliary capacitor is not explained here and not shown in the drawings since the auxiliary capacitor is not directly related to the present embodiment.
The source driver 300 and the gate driver 400 supply to a pixel electrode in each pixel formation section a potential corresponding to an image to be displayed, and a power circuit (not shown) supplies a predetermined potential Vcom to the common electrode Ec. Consequently, a voltage corresponding to a potential difference between the pixel electrode and the common electrode Ec is applied to liquid crystal. The application of a voltage controls light transmittance of the liquid crystal layer, thus enabling image display. It should be noted that a polarization plate is used when the application of a voltage to the liquid crystal layer controls light transmittance, and a polarization plate in the present embodiment is provided in such a manner as to realize a normally black mode. Therefore, each pixel formation section forms a black pixel when no voltage is applied to the pixel capacitor Cp of the pixel formation section.
The backlight 600 is a planer illuminating device for illuminating the display section 100 from backward, and includes a cold-cathode tube and an optical waveguide for example. The backlight 600 is driven by the light source drive circuit 700 to emit light to each pixel formation section of the display section 100.
The display control circuit 200 receives, from an outside signal source, a digital video signal Dv indicative of an image to be displayed; a horizontal sync signal HSY and a vertical sync signal VSY each corresponding to the digital video signal Dv; and a control signal Dc for controlling display operation. Further, the control circuit 200 generates, based on the signals Dv, HSY, VSY, and Dc thus received, a data start pulse signal SSP, a data clock signal SCK, a latch strobe signal (data signal application control signal) LS, a polarity inversion signal POL, a digital image signal DA indicative of an image to be displayed (signal corresponding to video signal Dv), a gate start pulse signal GSP, a gate clock signal GCK, and a gate driver output control signal (scanning signal output control signal) GOE, each serving as a signal for enabling the display section 100 to display an image indicated by the digital video signal Dv, and the control circuit 200 outputs these signals.
To be more specific, the video signal Dv is subjected to timing adjustment etc. in an internal memory if necessary and then outputted as the digital image signal DA from the display control circuit 200. The data clock signal SCK is generated as a signal consisting of pulses corresponding to pixels of an image indicated by the digital image signal DA. The data start pulse signal SSP is generated, based on the horizontal sync signal HSY, as a signal which has a high (H) level only during a predetermined period with respect to each horizontal scanning period. The gate start pulse signal GSP (GSPa, GSPb) is generated, based on the vertical sync signal VSY, as a signal which has a H level only during a predetermined period with respect to each frame period (each vertical scanning period). The gate clock signal GCK (GCKa, GCKb) is generated based on the horizontal sync signal HSY. The latch strobe signal LS and the gate driver output control signal GOE (GOEa, GOEb) are generated based on the horizontal sync signal HSY and the control signal Dc.
Among the signals thus generated by the display control circuit 200, the digital image signal DA, the latch strobe signal LS, the data start pulse signal SSP, the data clock signal SCK, and the polarity inversion signal POL are input to the source driver 300, and the gate start pulse signal GSP, the gate clock signal GCK, and the gate driver output control signal GOE are input to the gate driver 400.
Based on the digital image signal DA, the data start pulse signal SSP, the data clock signal SCK, the latch strobe signal LS, and the polarity inversion signal POL, the source driver 300 sequentially generates data signals S(1)-S(n) that are analog voltages corresponding to pixel values in each horizontal scanning line of an image represented by the digital image signal DA, and applies the data signals S(1)-S(n) to source lines SL1-SLn, respectively.
Based on the gate start pulse signal GSP (GSPa, GSPb), the gate clock signal GCK (GCKa, GCKb), and the gate driver output control signal GOE (GOEa, GOEb), the gate driver 400 generates scanning signals G(1)-G(m) and applies the scanning signals G(1)-G(m) to gate lines GL1-GLm, respectively, so as to selectively drive the gate lines GL1-GLm. Selective driving of the gate lines GL1-GLm is realized by applying, as the scanning signals G(1)-G(m), gate-on pulses whose selection periods equal to pulse widths. It should be noted that in the present embodiment, all of pulse widths of gate-on pulses Pw to be applied to individual gate lines have the same length, except for a certain example of driving. This makes charging conditions for individual pixels equal, enabling display more even over the whole display screen. This increases display quality.
As described above, the source driver 300 and the gate driver 400 drive the source lines SL1-SLn and the gate lines GL1-GLm of the display section 100, so that a voltage of a source line SLi is supplied to the pixel capacitor Cp via the TFT 10 connected with the selected gate line GLj (i=1 to n and j=1 to m). Thus, in individual pixel formation sections, a voltage corresponding to the digital image signal DA is applied to the liquid crystal layer, and application of the voltage controls transmittance of light from the backlight 600, enabling the display section 100 to display an image indicated by the digital video signal Dv from the outside.
Examples of a display method include progressive scan and interlace scan. The progressive scan is a method in which when displaying one frame, i.e. during one frame period, the gate lines GL1-GLm are sequentially selected one by one from top to bottom.
The interlace scan is a method in which the gate lines GL1-GLm are divided into a plurality of groups in such a manner that gate lines positioned with a predetermined line distance from each other belong to one group, and individual groups are scanned sequentially. In a case where the gate lines GL1-GLm are divided into two groups in such a manner that gate lines positioned with a distance of 1 line belong to one group, odd gate lines or even gate lines of the gate lines GL1-GLm are selected sequentially from top to bottom, and then even gate lines or odd gate lines of the gate lines GL1-GLm are selected sequentially from top to bottom.
(Example of Driving by Progressive Scan)
As shown in
In order to deal with this problem, in the above driving, the gate-on pulse Pw is not applied during 1 horizontal period right after the inversion of the polarity in order to provide a dummy horizontal period. Consequently, in a horizontal period next to a dummy insertion period, a data signal with the predetermined voltage is written in individual pixels.
Providing the dummy insertion period in this manner allows increasing a reaching ratio (charging ratio) of an actual voltage to an application voltage in the source lines SL1-SLn (data signal lines) when writing pixel data after polarity inversion. This prevents display unevenness with respect to every 10 rows which is caused by rounding of the data signal waveform at the moment of polarity inversion.
It should be noted that during the dummy insertion period, the display control circuit 200 stops application of an on-pulse of an LS signal to be input to the source driver 300. Consequently, a data signal to be written during the dummy insertion period is written during a horizontal period next to the dummy insertion period. Therefore, providing the dummy insertion period does not result in skip of data to be displayed, and allows suitable display.
Alternatively, the display control circuit 200 may output, in a horizontal period next to the dummy insertion period, a data signal equal to a data signal to be applied during the dummy insertion period right after the polarity inversion. Also in this case, providing the dummy insertion period does not result in skip of data to be displayed, and allows suitable display.
In the example shown in
Therefore, by setting the length of the dummy insertion period in such a manner that the dummy insertion period includes a time for the actual data signal to reach a predetermined voltage after polarity inversion, it is possible to write the data signal with the predetermined voltage in individual pixels during a horizontal period next to the dummy insertion period. For example, in a case where rounding of the data signal waveform is seen in a 1 horizontal period corresponding to 60 Hz, the dummy insertion period is set to be 1 horizontal period (1H). In a case where 120 Hz driving is performed in the same liquid crystal display device, since rounding of the data signal waveform is seen in 2 horizontal periods corresponding to 120 Hz, and therefore the dummy insertion period is set to be 2 horizontal periods (2H).
Providing the dummy insertion period in this manner allows increasing a reaching ratio of an actual voltage to an application voltage in the source lines SL1-SLn when writing pixel data after the inversion of the polarity. This prevents display unevenness with respect to every 10 rows which is caused by rounding of the data signal waveform at the moment of the inversion of the polarity.
In the above examples, the dummy insertion period is 2H or 3H. Alternatively, the dummy insertion period may be set to be 4H or more according to the degree of rounding of the data signal waveform at the moment of inversion of the polarity. It should be noted that setting the dummy insertion period to have a predetermined length or more may cause inconvenience such as tearing, in which an image is seen shifted in a horizontal direction between gate lines around the moment of inversion of the polarity. How the tearing is seen depends on the length of the dummy insertion period.
To be more specific, in a case where the dummy insertion period is provided as described above, a difference in display timing occurs between a pixel on a gate line where display is performed before inversion of the polarity and a pixel on a gate line where display is performed after inversion of the polarity.
In view of the above, when the difference in display timing around the moment of polarity inversion gets more than 0.8 msec, tearing gets likely to be seen, which deteriorates display quality. Therefore, by setting the time from the moment of polarity inversion to the moment of an application start of a gate-on pulse nearest to the moment of polarity inversion among gate-on pulses applied after the moment of polarity inversion to be equal to 0.8 msec or less, it is possible to perform excellent display with little or no tearing.
(Example of Driving by Interlace Scan)
In the interlace scan, a polarity inversion cycle is ½F. Accordingly, the interlace scan allows reduction of power consumption and reduction of heat generated by the source driver 300. Further, in the interlace scan, the polarity of a voltage to be applied on pixels appears to be inverted with respect to 1 row. This allows reducing flickers compared with the progressive scan, and allows reducing display unevenness due to coupling capacitance by pixels that are adjacent in a longitudinal direction.
As in the progressive scan, also in the interlace scan, an actual waveform of a data signal is rounded at the moment of inversion of the polarity of the data signal. That is, it takes approximately 1 horizontal period for the data signal to reach a predetermined voltage right after the inversion of the polarity. In order to deal with this problem, in the above driving, the gate-on pulse Pw is not applied during 1 horizontal period right after the inversion of the polarity in order to provide a dummy horizontal period. Consequently, in a horizontal period next to the dummy insertion period, a data signal with the predetermined voltage is written in individual pixels.
Providing the dummy insertion period in this manner allows increasing a reaching ratio (charging ratio) of an actual voltage to an application voltage in the source lines SL1-SLn (data signal lines) when writing pixel data after the inversion of the polarity.
It should be noted that, as in the progressive scan, also in the interlace scan, during the dummy insertion period, the display control circuit 200 stops application of an on-pulse of an LS signal to be input to the source driver 300. Consequently, a data signal to be written during the dummy insertion period is written during a horizontal period next to the dummy insertion period. Alternatively, the display control circuit 200 may output, in a horizontal period next to the dummy insertion period, a data signal equal to a data signal to be applied during the dummy insertion period right after the inversion of the polarity.
Data signals have been permutated beforehand by a data signal permutation circuit included in the display control circuit 200 in such a manner as to correspond to the interlace scan as shown in the drawing. The data signals thus permutated are subjected to a necessary process such as a timing process, and then supplied as digital image signals DA to the source driver 300. The data signal permutation circuit receives digital video signals Dv that are digital RGB signals supplied chronologically from an external signal source to the display control circuit 200, causes the digital video signals Dv to be temporarily stored in a memory, and then read out a signal corresponding to a scanning signal line driven currently, and thus permutates the data signals.
(Block-Divided Interlace Scan)
Under such circumstances, moving a vertically oblong image shown in (a) of
As with the cause of tearing as explained above, combing is caused by disparity in display timing between adjacent gate lines. Therefore, the result of sensory analysis for tearing is also true for combing. That is, combing is seen when the time Tc is approximately 0.8 ms or more. Consequently, in the example shown in
In contrast thereto, in the present embodiment, the gate lines GL1-GLm are divided into a plurality of blocks and interlace scan is performed with respect to each block (block-divided interlace scan). This allows reducing the time Tc, making combing less likely to be seen.
In the above steps, a first block including the 1st to αth gate lines are written in such a manner that odd rows are written firstly and even rows are written secondly, and a second block including the α+1st to 2αth gate lines are written in such a manner that even rows are written firstly and odd rows are written secondly. That is, in the odd block, odd rows are written firstly and even rows are written secondly, and in the even block, even rows are written firstly and odd rows are written secondly. When the last line in one block is written and then the first line in next block is written, a data signal voltage maintains the same polarity. This makes it unnecessary to perform inversion of the polarity when switching blocks to be written, thus reducing power consumption.
The time Tc which is a difference in time between writing in adjacent rows in the block-divided interlace scan is represented by an equation below.
Tc=(α/2)/(Vtotal)×(frame cycle)
wherein Vtotal represents 1 vertical period, that is, whole scanning lines. Since (frame cycle)/(Vtotal)=(time of 1 horizontal period), the above equation may be written as follows.
Tc=(α/2)×(1H, time of 1 horizontal period)
For example, in a case of 120 Hz driving in 52 type full HD (the number of all scanning lines including blanking period is 1125), if α=48, the time Tc that would cause abnormal display state is
Tc=(48/2)/1125×(1/120)×10^6=177.8 μs
and consequently combing is so prevented as not to be seen.
Further, in a case of 60 Hz driving in 37 type full HD (the number of all scanning lines including blanking period is 1125), if α=20, similar calculation shows that Tc=148.1 μs, and consequently combing is so prevented as not to be seen.
(Example of Driving in Block-Divided Interlace Scan)
In this driving example, a first block including 1st-20th gate lines is written in such a manner that odd rows are written firstly and even rows are written secondly, and a second block including 21st-40th gate lines is written in such a manner that even rows are written firstly and odd rows are written secondly. Therefore, in the 1st-40th gate lines, inversion of the polarity is made when switching from odd rows to even rows in the first block and when switching from even rows to odd rows in the second block. To be specific, even rows corresponding to 20H in the 1st-40th gate lines are scanned while a data signal maintains the same polarity (here, −polarity). 20 odd rows from 21st gate line are scanned while a data signal maintains the same polarity (here, +polarity). Therefore, except for the first scan, scan is performed with the polarity of a data signal inverted with respect to every 20 rows.
In this example, it takes substantially 1 horizontal period right after inversion of the polarity for an actual data signal waveform to reach a predetermined voltage. Consequently, there is a case where display unevenness is caused by rounding of the data signal at the moment of polarity inversion.
Therefore, as described above, by setting the length of a dummy insertion period in such a manner that the dummy insertion period includes the time for a data signal to reach a predetermined voltage after inverting its polarity, a data signal with the predetermined voltage is written in individual pixels in a horizontal period next to the dummy insertion period. Providing the dummy insertion period in this manner allows increasing a reaching ratio of an actual voltage to an application voltage in the source lines SL1-SLn when writing pixel data after inversion of the polarity. This allows preventing display unevenness with respect to approximately every 20 rows that is caused by rounding of the data signal waveform at the moment of polarity inversion.
Further, compared with the above progressive scan, in this driving, the polarity of a voltage applied to a pixel is inverted with respect to each row, which reduces flickers and reduces display unevenness caused by coupling capacitance of pixels adjacent in a longitudinal direction. In addition, since the block-divided interlace scan is employed, it is possible to prevent the combing.
Data signals have been permutated beforehand by a data signal permutation circuit included in the display control circuit 200 in such a manner as to correspond to the block-divided interlace scan as shown in the drawing. The data signals thus permutated are subjected to a necessary process such as a timing process, and then supplied as digital image signals DA to the source driver 300. The data signal permutation circuit receives digital video signals Dv that are digital RGB signals supplied chronologically from an external signal source to the display control circuit 200, causes the digital video signals Dv to be temporarily stored in a memory, and then read out a signal corresponding to a scanning signal line driven currently, and thus permutates the data signals.
In the driving example shown in
In the driving example shown in
Also in this driving example, providing the dummy insertion period yields the same effect as above. However, compared with the above driving examples in
Further, in the driving example in
In the driving example shown in
Unlike the driving example in
In the example shown in
Although the length of the dummy insertion period in the above example is set to 2H, the length may be set to 3H or more according to the degree of rounding of the data signal waveform after inversion of the polarity.
(Control of Application of Gate-on Pulse)
The following explains the dummy insertion period in more details. In the above driving examples, a period from the moment of inversion of the polarity to the moment of first application of a gate-on pulse Pw is provided as one or more horizontal periods, thereby preventing the influence of rounding of a data signal waveform. However, this period is not limited to one or more horizontal periods. If this period is as defined below, this period can prevent the influence of rounding of a data signal waveform.
Initially, when a last end of a gate-on pulse nearest to a moment of polarity inversion of a data signal among gate-on pulses applied before the moment of polarity inversion is earlier than an end time of a horizontal period during which the gate-on pulse is applied, a period that starts at the last end of the gate-on pulse and ends at the end time of the horizontal period is defined as a first period. Further, a period that starts at the moment of the polarity inversion and ends at a moment of an application start of a gate-on pulse nearest to the moment of the polarity inversion among gate-on pulses applied after the polarity inversion is defined as a second period. The gate-on pulse Pw should be applied so that the second period is longer than the first period.
In the above driving examples, the second period corresponds to the dummy insertion period, and the first period corresponds to a period from the time when a gate-on pulse Pw is off in one horizontal period to the time when the horizontal period ends. Therefore, it is evident that the second period is longer than the first period in each of the above driving examples. Further, although not described as the above driving examples, driving may be performed in such a manner that a horizontal period in which a gate-on pulse Pw is not applied is provided right before inversion of the polarity. Also in this case, it is evident that the second period is longer than the first period.
With such driving, a gate-on pulse Pw is not applied at the moment of inversion of the polarity. This allows preventing data signals with opposite polarities from being simultaneously applied to two adjacent gate lines to which gate-on pulses Pw are applied before and after inversion of the polarity, respectively. This allows preventing image display from being disturbed at the moment of inversion of the polarity.
Further, among the gate-on pulses Pw applied after the moment of inversion of the polarity, the gate-on pulse Pw nearest to the moment of inversion of the polarity is gated on after a period longer than the first period has elapsed from the moment of inversion of the polarity. This prevents charge of a pixel from being carried out during a period where a data signal waveform is greatly rounded due to inversion of the polarity. This allows displaying an image with high quality that is free from display unevenness etc.
Further, the period from the moment of inversion of the polarity to the moment of first application of a gate-on pulse Pw may be set as follows. That is, a gate-on pulse may be applied so that a period from the moment of polarity inversion to the moment of application start of a gate-on pulse Pw nearest to the moment of polarity inversion among gate-on pulses Pw applied after the moment of polarity inversion is equal to or more than the length of a horizontal display period that is obtained by subtracting a horizontal blanking period from a horizontal period.
In the above driving examples, the period from the moment of polarity inversion to the moment of application start of a gate-on pulse Pw nearest to the moment of polarity inversion among gate-on pulses Pw applied after the moment of polarity inversion corresponds to a dummy insertion period. Accordingly, it is evident that the dummy insertion period is longer than the horizontal display period in each of the driving examples.
The length of a horizontal period is equal to the sum of the length of a horizontal display interval and the length of a horizontal blanking period. In general, a data signal to be applied to a source line is designed to have a signal waveform that allows a pixel to be charged within 1 horizontal display period. Accordingly, at the time when 1 horizontal display interval or more has elapsed from the moment of polarity inversion, the influence of rounding of a data signal waveform due to polarity inversion is prevented. This allows preventing charge of a pixel from being carried out during a period where a data signal waveform is greatly rounded due to polarity inversion. This allows displaying an image with high quality which is free from display unevenness etc.
As described above, a data signal to be applied to a source line is basically designed to have a signal waveform that allows a pixel to be charged within 1 horizontal display period. However, the case of carrying out polarity inversion causes a larger change in a voltage of a data signal waveform than the case of not carrying out the polarity inversion. Consequently, under a certain condition of designing a device, there is a possibility that a pixel is not charged within 1 horizontal display period. In order to deal with such a case, the dummy insertion period may be set to be 2H or more as in the above driving examples.
Another embodiment of the present invention is described below with reference to the drawings. Configurations having the same functions as those in Embodiment 1 are given the same reference numerals and explanations thereof are omitted here.
(Configuration of Liquid Crystal Display Device)
The CS control circuit 90 is a circuit for controlling the phase, the width etc. of a waveform of a CS (retention capacitor) signal to be applied to an auxiliary capacitor line (retention capacitor line; CS line). Control by the CS control circuit 90 and the auxiliary capacitor line will be detailed later.
When employing such a multi-pixel structure, it is preferable that at least two of the sub-pixels have different luminance. If at least two of the sub-pixels have different luminance, then one pixel includes a bright sub-pixel and a dark sub-pixel, allowing the liquid crystal display device to display a half tone with use of area coverage modulation. This is suitable for reducing excess brightness when viewing a liquid crystal screen in a skew direction.
Electrostatic capacitances of the first sub-pixel capacitor Csp1 and the second sub-pixel capacitor Csp2 have the same value, and they depend on effective voltages applied on individual liquid crystal layers. Further, a first auxiliary capacitor Cs1 and a second auxiliary capacitor Cs2 are provided independently of the first sub-pixel capacitor Csp1 and the second sub-pixel capacitor Csp2, and electrostatic capacitances of the first auxiliary capacitor Cs1 and the second auxiliary capacitor Cs2 have the same value.
One electrodes of the first sub-pixel capacitor Csp1 and the first auxiliary capacitor Cs1 are connected with a drain electrode of the first TFT 12a, and the other electrode of the first sub-pixel capacitor Csp1 is connected with the counter electrode Ec, and the other electrode of the first auxiliary capacitor Cs1 is connected with an auxiliary capacitor line (CS line) 52a. On the other hand, one electrodes of the second sub-pixel capacitor Csp2 and the second auxiliary capacitor Cs2 are connected with a drain electrode of the second TFT 12b, and the other electrode of the second sub-pixel capacitor Csp2 is connected with the counter electrode Ec, and the other electrode of the second auxiliary capacitor Cs2 is connected with an auxiliary capacitor line (CS line) 52b.
Gate electrodes of the first TFT 12a and the second TFT 12b are connected with a scanning line 16, and source electrodes of the first TFT 12a and the second TFT 12b are connected with a signal line 15.
The CS control circuit 90 outputs CS signals with different signal waveforms to the CS main lines 52M, respectively. In the example shown in
Each of the CS lines 52 is provided between adjacent gate lines GLm-1 and GLm in such a manner as to be along with the gate line GLm. Further, each CS line 52 is connected with one of the CS main lines 52M. In the example shown in
In the liquid crystal display device having the above multi-pixel structure, when a source driver 300 drives the source lines SL1-SLn of the display section 100 and a gate driver 400 drives the gate lines GL1-GLm of the display section 100, a voltage of a source line SLi is applied on a pixel capacitor via a TFT 10 connected with a selected gate line GLj (i=1 to n, j=1 to m). Then, the CS control circuit 90 drives the CS lines 52 and controls, with use of a CS signal, the voltage of the source line SLi which is supplied to the pixel capacitor.
This allows voltages corresponding to digital image signals DA are applied on a liquid crystal layer in individual pixel formation sections. Transmittance of light from a backlight 600 is controlled in response to application of the voltages, causing the display section 100 to display an image indicated by a digital video signal Dv from outside.
(Example of Interlace Scan Drive)
Bright-dark states of two sub-pixels that correspond to individual CS lines 52 are shown in
When a period from the time of applying a gate-on pulse on an odd gate line that is one of two adjacent gate lines and that firstly receives application of a gate-on pulse to the time of applying a gate-on pulse on an even line that is the other of the two adjacent gate lines and that secondly receives application of a gate-on pulse is regarded as an adjacent line writing time difference period, inversion of the polarity is performed even times (2k (k is an integer of 1 or more)) during at least the adjacent line writing time difference period. In other words, if a polarity inversion cycle of a CS signal is the sum of a first polarity continuation period and a second polarity continuation period, setting that (polarity inversion cycle of CS signal)=(adjacent line writing time difference period)/k (k is an integer of 1 or more) enables a bright-dark state to be completely inverted between sub-pixels adjacent to each other in a column direction. That is, this enables to keep a bright-dark state of a sub-pixel constant, thereby preventing deterioration in display quality. Further, since the order of brightness and darkness of individual sub-pixels is inverted between an odd line and an even line with respect to each line, it is possible to prevent occurrence of jaggyness of an image.
In the example in
Further, the phase of a CS signal to be applied to the n+2nd CS line 52 is delayed by 1H with respect to the phase of a CS signal to be applied to the nth CS line 52. This allows writing of data into individual sub-pixels at the moment after the same time has elapsed from the time of inversion of the polarity of a CS signal in all the CS lines 52 and at the moment when the waveform of the CS signal sufficiently achieves a steady state. Therefore, it is possible to prevent display unevenness due to rounding of the waveform of the CS signal.
In order to meet the above first and second conditions, CS signals in twice the number of a horizontal period included in a half period of a polarity inversion cycle of a data signal waveform, i.e. a period where one polarity continues. In the example in
As described above, in the interlace scan, the polarity inversion cycle is ½F. Accordingly, the interlace scan allows reducing power consumption and heat, of the source driver 300, compared with the progressive scan. Further, in the interlace scan, the polarity of a voltage applied on a pixel appears to be inverted with respect to 1 row, allowing reduction of flickers, and allowing reduction of unevenness due to coupling capacitance of pixels adjacent in a longitudinal direction.
Data signals have been permutated beforehand by a data signal permutation circuit included in the display control circuit 200 in such a manner as to correspond to the interlace scan as shown in the drawing. The data signals thus permutated are subjected to a necessary process such as a timing process, and then supplied as digital image signals DA to the source driver 300. The data signal permutation circuit receives digital video signals Dv that are digital RGB signals supplied chronologically from an external signal source to the display control circuit 200, causes the digital video signals Dv to be temporarily stored in a memory, and then reads out a signal corresponding to a scanning signal line driven currently, and thus permutates the data signals. This holds for other driving examples below.
Also in this interlace scan, an actual data signal shows rounding of waveform, as described above. In the example in the drawing, it takes substantially 1 horizontal period right after inversion of the polarity for an actual data signal waveform to reach a predetermined voltage. Accordingly, there is a possibility that display unevenness due to rounding of the waveform of the data signal occurs.
An example of driving capable of improving display unevenness due to rounding of the waveform of the data signal is a driving example shown in
In the example shown in
As described above, providing the dummy insertion period allows increasing a reaching ratio (charging ratio) of an actual voltage to an application voltage in the source lines SL1-SLn (data signal lines) when writing pixel data after inversion of the polarity.
It should be noted that, as in Embodiment 1, during the dummy insertion period, the display control circuit 200 stops application of an on-pulse of an LS signal to be input to the source driver 300. Consequently, a data signal to be written during the dummy insertion period is written during a horizontal period next to the dummy insertion period. Alternatively, the display control circuit 200 may output, in 2 horizontal periods next to the dummy insertion period, a data signal equal to a data signal to be applied during the dummy insertion period right after the inversion of the polarity.
On the other hand, simply inserting a dummy insertion period as in the present driving example raises the following problem in the multi-pixel driving. That is, insertion of the dummy insertion period lengths the polarity inversion cycle of a data signal waveform, whereas the polarity inversion cycle of a CS signal does not change. This causes disparity between phases of the data signal waveform and the CS signal. This makes the bright-dark state of a sub-pixel unstable, dropping display quality.
In
One example of a driving method that improves the problem due to the difference between a polarity inversion cycle of a CS signal and a polarity inversion cycle of a data signal waveform is a driving example shown in
In the example in
With the above driving, insertion of a dummy insertion period allows lengthening the polarity inversion cycle of a data signal waveform and lengthening the polarity inversion cycle of a CS signal. This allows keeping relationship in phase between the data signal waveform and the CS signal. Further, at least in an adjacent line writing time difference period, each of the CS signals has the same polarity inversion timing among successive frames. This stabilizes the state of brightness-darkness of sub pixels, preventing deterioration in display quality. Further, since the order of brightness and darkness of individual sub-pixels is inverted between an odd line and an even line with respect to each line, it is possible to prevent occurrence of jaggyness of an image.
Further, with the configuration, in all the CS lines, it is possible to write data into individual sub-pixels at a time when the same time has elapsed from the moment of inversion of the polarity of a CS signal and when the waveform of the CS signal sufficiently achieves a steady state. This allows preventing display unevenness due to rounding of the waveform of a CS signal.
Such driving can be realized by delaying the phase of a CS signal applied to an n+2nd CS line 52 by 1H with respect to the phase of a CS signal applied to an nth CS line 52 during a period when a data signal waveform continues to have the same polarity.
The CS signal lines 52 are divided into a block including upper 10 rows and a block including lower 11 rows, and CS signals in two rows in the upper 10 rows are paired, and the order of CS signals in each pair is inverted in the lower 10 rows, and a CS signal at the lower 11th row is made identical with a CS signal at the upper 1st row. Thus, the above driving is realized using 10 kinds of CS signals.
In the above example, the dummy insertion period is 2H. Alternatively, the dummy insertion period may be 1H or 3H or more depending on the degree of rounding of a data signal waveform.
On the other hand, in the driving example, two polarities have different polarity continuation periods in a waveform of a CS signal. In this case, there is a possibility that an effective voltage of a sub-pixel varies depending on the difference in the polarity continuation period, resulting in striped display unevenness.
One example of a driving method that improves the problem due to the difference in the polarity continuation period is a driving example shown in
In the example in
It should be noted that the dummy insertion period is set in such a manner that half the length of the polarity inversion cycle of a data signal waveform to which the dummy insertion period is added is equal to the length corresponding to positive integer number of 1 horizontal periods. This allows setting the polarity continuation period by the length of 1 horizontal period as a unit. This prevents a circuit for generating a CS signal waveform from being complicated.
As in the case of the driving example in
In the present driving example, the CS lines 52 are divided into a block including upper 12 rows and a block including lower 9 rows, and CS signals in two rows in the upper 8 rows in the block including upper 12 rows are paired, and the order of CS signals in each pair is inverted in the lower 8 rows, and a CS signal at lower 9th row is made identical with a CS signal at upper 10th row. This provides 12 kinds of (phases of) CS signals, allowing the above driving.
Another example of a driving method that improves the problem due to the difference in the polarity continuation period in the driving example in
According to the driving example, in a period that is a half of the polarity inversion cycle of a data signal, that is, in a period during which a data signal polarity POL continues to be the same, a dummy insertion period is inserted not only at a time right after inversion of the polarity but also at another time. At the time when the dummy insertion period is inserted, a gate-on pulse Pw is not applied.
Further, the polarity inversion cycle of a CS signal is set to be half the length of the polarity inversion cycle of the data signal polarity POL to which cycle all the dummy insertion periods are added, and the polarity continuation period of the CS signal is kept constant regardless of the polarity.
As with the driving example in
The driving example is designed such that in two CS lines 52 corresponding to a gate line GLj to which a gate-on pulse Pw is applied right after insertion of a dummy insertion period, the phase of a CS signal to be applied to a CS line 52 that is the former of the two CS lines 52 in terms of a sub scanning order is delayed by 2H (length of inserted dummy insertion period)+1H with respect to the phase of a CS signal to be applied to a CS line 52 that is prior to the former one of the two CS lines 52 in terms of a sub scanning order. On the other hand, in other CS lines 52, the phase of a CS signal to be applied to n+2nd CS line 52 is delayed by 1H with respect to the phase of a CS signal to be applied to nth CS line 52.
This driving allows writing data into individual sub-pixels in all the CS lines 52 at a time when the same time has elapsed from inversion of the polarity of a CS signal and the waveform of the CS signal sufficiently achieves a steady state. This allows preventing display unevenness due to rounding of a CS signal waveform.
In the above driving example, the number of horizontal periods (5H) actually written between the first dummy insertion period and a second dummy insertion period next to the first dummy insertion period is equal to the number of horizontal periods (5H) actually written between the second dummy insertion period and a first dummy insertion period next to the second dummy insertion period.
Consequently, when the CS lines 52 are divided into a block including upper 10 rows and a block including lower 11 lines, and CS signals in two rows in the upper 10 rows are paired, and the order of CS signals in each pair is inverted in the lower 10 rows, and a CS signal at lower 11th row is made identical with a CS signal at upper 1st row, it is possible to realize the above driving using 10 kinds of (phases of) CS signals. In this regard, the driving example in
The following explains a driving example that allows preventing shortage in charging of a pixel at a moment of inversion of the polarity of a data signal in the driving example in
The driving example in
(Example of Block-Divided Interlace Scan Drive)
In Embodiment 1, the block-divided interlace scan was explained as a method for preventing inconvenient combing that occurs when carrying out driving by normal interlace scan. The following explains a driving example in which the block-divided interlace scan is applied to the present embodiment.
In this driving example, a first block including 1st-20th gate lines is written in such a manner that odd rows are written firstly and even rows are written secondly, and a second block including 21st-40th gate lines is written in such a manner that even rows are written firstly and odd rows are written secondly. Therefore, from the 1st-40th gate lines, inversion of the polarity is made when switching from odd rows to even rows in the first block and when switching from even rows to odd rows in the second block. To be specific, even rows corresponding to 20H in the 1st-40th gate lines are scanned while a data signal maintains the same polarity (here, polarity). 20 odd rows from the 21st gate line are scanned while a data signal maintains the same polarity (here, +polarity). Therefore, except for the first scan, scan is performed with the polarity of a data signal inverted with respect to scan of every 20 rows.
In this example, it takes substantially 1 horizontal period right after inversion of the polarity for an actual data signal waveform to reach a predetermined voltage. Consequently, there is a case where display unevenness is caused by rounding of the data signal when inverting the polarity.
Therefore, as described above, by setting the length of a dummy insertion period in such a manner that the dummy insertion period includes the time for a data signal to reach a predetermined voltage after inverting its polarity, a data signal with the predetermined voltage is written in individual pixels in a horizontal period next to the dummy insertion period. Providing the dummy insertion period in this manner allows increasing a reaching ratio of an actual voltage to an application voltage in the source lines SL1-SLn when writing pixel data after inversion of the polarity. This allows preventing display unevenness with respect to approximately every 20 rows that is caused by rounding of the data signal waveform at the time of inverting the polarity.
Further, compared with the above progressive scan, in this driving, the polarity of a voltage applied to a pixel appears to be inverted with respect to each row, which reduces flickers and reduces display unevenness caused by coupling capacitance of pixels adjacent in a longitudinal direction. In addition, since the block-divided interlace scan is employed, it is possible to prevent the combing.
When a period from the time of applying a gate-on pulse on an odd gate line that is one of two adjacent gate lines and that firstly receives application of a gate-on pulse to the time of applying a gate-on pulse on an even line that is the other of the two adjacent gate lines and that secondly receives application of a gate-on pulse is regarded as an adjacent line writing time difference period, inversion of the polarity is performed even times (2k (k is an integer of 1 or more)) during at least the adjacent line writing time difference period. In other words, if a polarity inversion cycle of a CS signal is the sum of a first polarity continuation period and a second polarity continuation period, setting that (polarity inversion cycle of CS signal)=(adjacent line writing time difference period)/k (k is an integer of 1 or more) enables a bright-dark state to be completely inverted between sub-pixels adjacent to each other in a column direction. Further, each of individual CS signals has the same polarity inversion timing between successive frames at least during the adjacent line writing time difference period. This makes the state of brightness-darkness of a sub-pixel constant, preventing deterioration in display quality. Further, since the order of brightness and darkness of individual sub-pixels between an odd line and an even line is inverted with respect to each line, it is possible to prevent the occurrence of jaggyness of an image.
In the example in
Further, during a period when the same polarity of a data signal waveform continues, the phase of a CS signal to be applied to the n+2nd CS line 52 is delayed by 1H or 2H with respect to the phase of a CS signal to be applied to the nth CS line 52. This allows writing of data into individual sub-pixels at the time after 4H or more has elapsed from the time of inversion of the polarity of a CS signal in all the CS lines 52 and at the time when the waveform of the CS signal sufficiently achieves a steady state. Therefore, it is possible to prevent display unevenness due to rounding of the waveform of the CS signal.
The CS lines 52 are divided into blocks each including 10 rows, CS signals in two rows in a block are paired, and the order of CS signals in each pair is inverted in 10 rows in a block posterior by one to the block in the sub-scanning order. Thus, the above driving is realized with use of 10 kinds (phases) of CS signals.
Data signals have been permutated beforehand by a data signal permutation circuit included in the display control circuit 200 in such a manner as to correspond to the block-divided interlace scan as shown in the drawing. The data signals thus permutated are subjected to a necessary process such as a timing process, and then supplied as digital image signals DA to the source driver 300. The data signal permutation circuit receives digital video signals Dv that are digital RGB signals supplied chronologically from an external signal source to the display control circuit 200, causes the digital video signals Dv to be temporarily stored in a memory, and then reads out a signal corresponding to a scanning signal line driven currently, and thus permutates the data signals. This holds for other driving examples below.
In the above driving example, the length of a polarity continuation period of one polarity of a CS signal waveform is different from the length of a polarity continuation period of the other polarity of the CS signal waveform. For example, at a CS line 52 serving as CS_A, in a period in which the polarity of a data signal waveform is minus, H level period of the CS signal waveform is 5H+5H=10H, whereas L level period of the CS signal waveform is 5H+6H=11H. Such difference is seen in individual CS lines 52, causing a difference in actual potential between sub-pixels due to a difference in the length of a polarity continuation period of a CS signal waveform. This may cause striped display unevenness.
The following explains differences between the driving example in
Further, to a polarity continuation period of a CS signal at timing when the dummy insertion period is inserted is added a period to which the dummy insertion period is inserted, i.e. 1H. That is, a polarity continuation period of the CS signal at timing when the dummy insertion period is inserted is set to 6H and a polarity continuation period of other CS signal is set to 5H.
With the driving, the length of a polarity continuation period of one polarity of a CS signal waveform is equal to the length of a polarity continuation period of the other polarity of the CS signal waveform. For example, at a CS line 52 serving as CS_A, in a period in which the polarity of a data signal waveform is minus, H level period of the CS signal waveform is 5H+6H=11H, and L level period of the CS signal waveform is 5H+6H=11H. This allows making an effective potential substantially equal between sub-pixels, preventing striped display unevenness.
The driving example is designed such that in two CS lines 52 corresponding to a gate line GLj to which a gate-on pulse Pw is applied right after insertion of a dummy insertion period, the phase of a CS signal to be applied to a CS line 52 that is the former of the two CS lines 52 in terms of a sub scanning order is delayed by 1H (length of inserted dummy insertion period)+1H with respect to the phase of a CS signal to be applied to a CS line 52 that is prior to the former one of the two CS lines 52 in terms of a sub scanning order. On the other hand, in other CS lines 52, the phase of a CS signal to be applied to n+2nd CS line 52 is delayed by 1H with respect to the phase of a CS signal to be applied to nth CS line 52.
This driving allows writing data into individual sub-pixels in all the CS lines 52 at a time when 4H or more has elapsed from inversion of the polarity of a CS signal and the waveform of the CS signal sufficiently achieves a steady state. This allows preventing display unevenness due to rounding of a CS signal waveform.
In the above driving example, the number of horizontal periods (5H) actually written between the first dummy insertion period and a second dummy insertion period next to the first dummy insertion period is equal to the number of horizontal periods (5H) actually written between the second dummy insertion period and a first dummy insertion period next to the second dummy insertion period.
Thus, the CS lines 52 are divided into blocks each including 10 rows, CS signals in two rows in a block are paired, and the order of CS signals in each pair is inverted in 10 rows in a block posterior by one to the block in the sub-scanning order. Thus, the above driving is realized with use of 10 kinds (phases) of CS signals.
In the above example, the first dummy insertion period and the second dummy insertion period are set to 1H. Alternatively, they may be set to 2H or more.
In the example in
Therefore, as described above, by setting the length of the dummy insertion period to include the time for a data signal to reach a predetermined voltage after inversion of the polarity, a data signal with the predetermined voltage is written into individual pixels in a horizontal period next to the dummy insertion period.
In this driving example, each block is configured such that only in a period (adjacent line writing time difference period) from the time of applying a gate-on pulse Pw on an odd or even line that is one of two adjacent gate lines and that firstly receives application of the gate-on pulse Pw to the time of applying a gate-on pulse Pw on an even or odd line that is the other of the two adjacent gate lines and that secondly receives application of the gate-on pulse Pw, a CS signal dummy period corresponding to a dummy insertion period (1H) of a data signal is inserted into at least one of polarity continuation periods for a CS signal. In this case, each of CS signals has the same polarity inversion timing between successive frames at least in the adjacent line writing time difference period.
In this case, other than in the adjacent line writing time difference period, a CS signal may be a periodic signal that has a certain polarity continuation period and may be a signal with a certain value whose potential is the same as that of a common electrode. It should be noted that application of a gate-on pulse Pw and a CS signal is required to be controlled so that the gate-on pulse Pw is applied other than in a period during which a dummy insertion period is inserted into a data signal and the gate-on pulse Pw is applied at the latter part of the polarity continuation period of a CS signal. Further, since all CS signals are independent, the number of kinds of CS signals and the number of CS main lines 52M are required to be identical with the number of CS lines 52. Signals may be independently supplied to individual CS lines 52 without using the CS main lines 52M.
With the above example, the number of a polarity continuation period to which a dummy insertion period is inserted in a CS signal is one per one frame, and therefore a difference in a ratio of a polarity continuation period of one polarity to a polarity continuation period of the other polarity is slight. This allows keeping an effective potential of a sub-pixel substantially constant, thereby preventing striped display unevenness.
In the above driving example, a CS signal dummy period corresponding to a dummy insertion period (1H) is inserted into at least one of polarity continuation periods for a CS signal in the adjacent line writing time difference period. Alternatively, dummy insertion periods may be evenly assigned to all of polarity continuation periods of CS signals in the adjacent line writing time difference period and individually inserted in, the polarity continuation periods (each polarity continuation period is 0.5H).
In this driving example, each polarity continuation period of a CS signal is 5.5H. This allows keeping an effective potential of a sub-pixel almost evenly, preventing striped display unevenness.
Further, the phase of a CS signal to be applied on an n+2nd CS line 52 is delayed by 1H with respect to the phase of a CS signal to be applied on an nth CS line 52 and each polarity continuation period is 5.5H. Consequently, CS signals show the same waveform with respect to every 22 lines. Accordingly, it is possible to supply CS signals to individual CS lines 52 via 22 CS main lines 52M.
In the above example, the dummy insertion period is 1H. Alternatively, the dummy insertion period may be 2H or more.
In the example in
Therefore, by setting the length of the dummy insertion period in such a manner that the dummy insertion period includes a time for a data signal to reach a predetermined voltage after inversion of the polarity, it is possible to write the data signal with the predetermined voltage in individual pixels during a horizontal period next to the dummy insertion period.
Further, the phase of a CS signal to be applied on an n+2nd CS line 52 is delayed by 1H with respect to the phase of a CS signal to be applied on an nth CS line 52, and each polarity continuation period is 6H. In this case, CS signals show the same waveform with respect to every 24 lines. However, use of CS signals whose phases are opposite to each other allows realizing the above example by using 12 kinds (phases) of CS signals. That is, it is possible to supply CS signals to individual CS lines 52 by using 12 CS main lines 52M. It should be noted that signals may be supplied to individual CS lines 52 independently without using the CS main lines 52.
Here, in this driving example, when a polarity continuation period of a CS signal is regarded as c (=6H) and a dummy period of a CS signal is regarded as b (=1H), a basic polarity inversion cycle n2 of a data signal is calculated as n2=(c−b)×4k (k is a natural number)=(6−1)×4×1=20(H). Further, a dummy insertion period m is calculated as m=2b×k=2×1×1=2(H). Further, the number of phases of a CS signal is calculated as 2×c=2×6=12 (phases). On the other hand, the polarity continuation period c of a CS signal is calculated as c=n2/4k+b. Further, the number of inversion of the polarity of a CS signal in an adjacent line writing time difference period is 2k.
The following explains a driving example designed for preventing shortage in charging of a pixel when inverting the polarity of a data signal in the driving example in
The driving example in
(How to Set Horizontal Scanning Period)
The following explains how to set a horizontal scanning period. In the example, the horizontal period as explained above is referred to as a horizontal scanning period. The horizontal scanning period corresponds to the sum of a horizontal display period and a horizontal blanking period.
First, an explanation is made as to a configuration where the polarity of a signal potential to be applied on one source line is inverted with respect to a plurality of data (a plurality of pixels), and one or more dummy scanning periods (corresponding to the dummy insertion period as explained above) are inserted right after inversion of the polarity. This configuration realizes block inversion driving (nh/1v inversion driving) in which the polarity of a signal potential is inverted at a border where blocks of pixels are adjacent to each other in a column direction (it should be noted that the polarity of a signal potential is inverted at a border where pixels are adjacent to each other in a row direction).
In this case, when video data corresponding to Nth gate line is referred to as N, video data to be inputted is lined as 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 and 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, and 21, 22, . . . . A circuit such as a dummy data insertion circuit in the display control circuit 200 brings these video data together into a set of 1, 2, 3, . . . , 8, 9, 10, a set of 11, 12, 13, . . . 18, 19, 20, and a set of 21, 22, . . . , and inserts dummy data at the front of each set. Consequently, as shown in
Desired data may be freely set as dummy data <D>. For example, the dummy data <D> may be equal to video data at a point right after insertion of the dummy data <D>, or data corresponding to a higher voltage than that of video data right after insertion of the dummy data <D> may be separately set as the dummy data <D> in order to increase a charging effect of a source line.
The waveform of a signal potential is rounded right after inversion of the polarity of the signal potential. In the present configuration, a dummy scanning period is provided here to supply a predetermined signal potential (signal potential corresponding to dummy data), allowing charging of a source line in this period. Consequently, it is possible to write a desired signal potential (potential corresponding to video data) in a pixel during a horizontal scanning period following the dummy scanning period. This allows preventing display unevenness with respect to every 10 rows due to the rounding of the signal potential waveform right after inversion of the polarity.
In the present liquid crystal display device, in order that a vertical display period of 1 frame does not change when dummy data is inserted one by one into individual sets each including 10 video data and a dummy scanning period is assigned to each dummy data as described above (i.e. in order that a vertical blanking period VblankX set to an input data sequence is equal to a vertical blanking period VblankY in actual output), 1 horizontal scanning period HtotalY in actual output is set to be shorter than 1 horizontal scanning period HtotalX set to an input data sequence.
As shown in
To be specific, as shown in
Output of a signal potential to a source line continues during the horizontal scanning period (HtotalY) including the horizontal blanking period (HblankY), and data is written to a pixel during a period in which a transistor of a pixel is made ON in accordance with the horizontal scanning period (during a period in which a gate-on pulse is supplied to a corresponding gate line). Further, output of a signal potential to a source line continues during the dummy scanning period (DtotalY) including the dummy blanking period (DblankY). In
In
This configuration allows the horizontal display period HdispX set to an input data sequence and the horizontal display period HdispY in actual output to be equal to each other. Consequently, it is possible to insert one dummy scanning period with respect to every 10 horizontal scanning periods while keeping a dot clock as it is, without increasing the vertical display period of a liquid crystal display device and without reducing the vertical blanking period of the liquid crystal display device (i.e. while keeping VdispX=VdispY, VblankX=VblankY).
Further, this configuration is advantageous in that since the dummy scanning period DtotalY is equal to the horizontal scanning period HtotalY (2000 dot), it is easy to perform signal processing or to design a configuration for signal processing.
A combination of the number of whole horizontal periods (number of video data) in one set, the number of whole dummy scanning periods (number of dummy data) in one set, horizontal scanning period HtotalY, and the dummy scanning period DtotalY is set by the display control circuit 200 (liquid crystal panel driving device), and the display control circuit 200 generates the above various signals (POL, LS, SSP, SCK, GCK, GSP, and GOE) etc. The display control circuit 200 also carries out insertion of dummy data into input video data.
In the above configuration, dummy data is inserted into sequentially input video data. Alternatively, one dummy scanning period may be provided by reducing a latch pulse by one without inserting dummy data (while keeping input of a data sequence). However, this alternative configuration is problematic in that the same data is output both during the dummy scanning period and during 1 horizontal scanning period following the dummy scanning period.
As shown in
To be specific, as shown in
Output of a signal potential to a source line continues during the horizontal scanning period (HtotalY) including the horizontal blanking period (HblankY), and data is written to a pixel during a period in which a transistor of the pixel is made ON in accordance with the horizontal scanning period (during a period in which a gate-on pulse is supplied to a corresponding gate line). Further, output of a signal potential to a source line continues during the dummy scanning period (DtotalY) including the dummy blanking period (DblankY). In
This configuration allows causing the horizontal display period HdispX set to an input data sequence to be equal to the horizontal display period HdispY in actual output. Consequently, it is possible to provide a dummy scanning period with respect to every 20 horizontal scanning periods while maintaining a dot clock as it is, without increasing a vertical display period of a liquid crystal display device, and without reducing a vertical blanking period of the liquid crystal display device (while maintaining VdispX=VdispY, VblankX=VblankY).
Further, the dummy scanning period DtotalY of 2080 dots and the horizontal scanning period HtotalY of 2096 dots ensure a longer horizontal scanning period, which is advantageous for charging a pixel.
In a case where dummy data is inserted one by one into each set including 20 video data and a dummy scanning period is assigned to each dummy data, as shown in
This configuration allows causing the horizontal display period HdispX set to an input data sequence to be equal to the horizontal display period HdispY in actual output. Consequently, it is possible to provide a dummy scanning period with respect to every 20 horizontal scanning periods while maintaining a dot clock as it is, without increasing a vertical display period of a liquid crystal display device, and without reducing a vertical blanking period of the liquid crystal display device (while maintaining VdispX=VdispY, VblankX=VblankY).
Further, in the configuration, the dummy scanning period DtotalY of 2120 dots and the horizontal scanning period HtotalY of 2094 dots ensure a longer dummy scanning period, which is advantageous for charging a source line in a case where a signal voltage waveform is greatly rounded after inversion of the polarity.
In a case where input is designed such that HtotalX=2200 (HdispX1920+HblankX280), inserting dummy data one by one into each set including 20 video data and assigning a dummy scanning period to each dummy data require that HtotalY (=HdispY+HblankY) and DtotalY (=DdispY+DblankY) have values of any combination in
It should be noted that the difference between a dummy scanning period and a horizontal scanning period is preferably small since the smaller difference allows simplifying adjustment of timing with other signal (e.g. facilitating setting of a potential waveform of a retention capacitor line when this configuration is applied to a later-mentioned pixel dividing method). Therefore, a combination in the hatched portion in
The following explains a configuration in which a plurality of video data (video data corresponding to one source line) are gathered into a set in the order of input, one dummy data is inserted at least at the top of each set, and in accordance with interlace scan of scanning signal lines (interlace scan of skipping every second gate line), in the order of alignment of data (video data, dummy data), signal potentials corresponding to the data are output, and 1 horizontal period is assigned to outputs of signal potentials corresponding to individual video data and a dummy scanning period is assigned to outputs of signal potentials corresponding to individual dummy data, and the polarity of a signal potential is inverted with respect to each set. The configuration allows dot inverse driving (1 h/1v inverse driving) in which the polarity of a signal potential is inverted at a border where blocks of pixels are adjacent to each other in a column direction (the polarity of a signal potential is inverted at a border where pixels are adjacent to each other in a row direction). In the configuration, the display control circuit 200 includes a data permutation circuit in which input data are permutated and dummy data is inserted (this will be explained later).
In this case, when video data corresponding to Nth gate line is referred to as N, video data to be inputted is lined as 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, . . . . A permutation circuit brings these video data together into a set of 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, a set of 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, and a set of 22, 24, . . . , and inserts dummy data at the top of each set. Consequently, when video data corresponding to Nth gate line is referred to as <N> and dummy data is referred to as <D>, data to be output (video data, dummy data) is lined as <D>, <2>, <4>, <6>, <8>, <10>, <12>, <14>, <16>, <18>, <20>, and <D>, <1>, <3>, <5>, <7>, <9>, <11, <13>, <15>, <17>, <19>, and <D>, <22>, <24>, . . . . Signal potentials with plus polarity corresponding to individual data <D>, <2>, <4>, . . . <20> are output to one source line in this order, and then signal potentials with minus polarity corresponding to individual data <D>, <I>, <3>, . . . <19> are output to one source line in this order, and then signal potentials with plus polarity corresponding to individual data <D>, <22>, <24>, . . . are output to one source line in this order.
Desired data may be freely set as dummy data <D>. For example, the dummy data <D> may be equal to video data at a point right after insertion of the dummy data <D>, or data corresponding to a higher voltage than that of video data right after insertion of the dummy data <D> may be separately set as the dummy data <D> in order to increase a charging effect of a source line.
The waveform of a signal potential is rounded right after inversion of the polarity of the signal potential. In the present configuration, a dummy scanning period is provided here to supply a predetermined signal potential (signal potential corresponding to dummy data), allowing charging a source line in this period. Consequently, it is possible to write a desired signal potential (potential corresponding to video data) in a pixel during a horizontal scanning period following the dummy scanning period. Further, by making the polarities of signal voltages applied to adjacent two source lines opposite to each other, the polarities of individual pixels appears to be inverted with respect to each dot, which is advantageous in terms of flickers.
In the present liquid crystal display device, in order that a vertical display period of 1 frame does not change when dummy data is inserted one by one into individual sets each including 10 video data and a dummy scanning period is assigned to each dummy data (i.e. in order that a vertical blanking period VblankX set to an input data sequence is equal to a vertical blanking period VblankY in actual output), 1 horizontal scanning period HtotalY in actual output is made shorter than 1 horizontal scanning period HtotalX set to an input data sequence.
To be specific, as shown in
In this case, too, as shown in
In this case, when video data corresponding to Nth gate line is referred to as N, video data to be inputted (not shown) is lined as 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, . . . 43, 44, 45, 46, 47, 48, 49. A permutation circuit brings these video data together into a set of 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, a set of 2, 4, 6, 8, 10, 11, 12, . . . , 36, 38, 40, a set of 21, 23, 25, . . . 45, 47, 49, and a set of 42, 44, 46, 48, . . . and inserts dummy data at the top of each set. Consequently, when video data corresponding to Nth gate line is referred to as <N> and dummy data is referred to as <D>, data to be output (video data, dummy data) is lined as <D>, <1>, <3>, <5>, <7>, <9>, <11>, <13>, <15>, <17>, <19>, and <D>, <2>, <4>, <6>, <8>, <10>, <12>, <36>, <38>, <40> and <D>, <21>, <23>, <25>, <27>, <45>, <47>, <49>, and <D>, <42>, <44>, . . . . Signal potentials with plus polarity corresponding to individual data <D>, <1>, <3>, <5>, . . . <17> and <19> are output to one source line in this order, and then signal potentials with minus polarity corresponding to individual data <D>, <2>, <4>, <6>, <36>, <38>, <40> are output to one source line in this order, and then signal potentials with plus polarity corresponding to individual data <D>, <21>, <23>, <25>, <47>, <49> are output to one source line in this order, and then signal potentials with minus polarity corresponding to individual data <D>, <42>, <44>, . . . are output to one source line in this order.
Desired data may be freely set as dummy data <D>. For example, the dummy data <D> may be equal to video data at a point right after insertion of the dummy data <D>, or data corresponding to a higher voltage than that of video data right after insertion of the dummy data <D> may be separately set as the dummy data <D> in order to increase a charging effect of a source line.
In this case, in the first set, a horizontal scanning period HtotalY in actual output is set to 2000 dots smaller than HtotalX, a dummy scanning period DtotalY is set to 2000 dots smaller than HtotalX, and in the second set and thereafter, a horizontal scanning period HtotalY in actual output is set to be 2094 dots smaller than HtotalX and a dummy scanning period DtotalY is set to 2120 dots smaller than HtotalX. This allows providing a dummy scanning period without changing a vertical display period in 1 frame.
The following explains how to permute data with reference to
The permutation control circuit 552 receives video data to be displayed, a vertical sync signal and a horizontal sync signal that are synchronized with video data, and a control signal for controlling display operation. The permutation control circuit 552 separates the video data thus received into video data for odd lines and video data for even lines and writes individual video data into the odd line permutation memory 554A and the even line permutation memory 554B. After carrying out this operation for a certain time, the permutation control circuit 552 sequentially reads out data from the odd line permutation memory 554A, and then reads out data from the even line permutation memory 554B.
In this process, the permutation control circuit 552 counts the number of video data in accordance with the number of lines in each set, reads out video data from the odd line permutation memory 554A and the even line permutation memory 554B, and inserts dummy data <D> at a predetermined position (e.g. at the top of each set). It should be noted that 1 horizontal scanning period during which video data is output and a dummy scanning period during which dummy data is output are set to be shorter than 1 horizontal scanning period set to input video data (input interval for each video data). Writing and reading of video data are carried out according to a predetermined order by using a look-up table that is prepared beforehand. This allows downsizing the permutation memories 554A and 554B without using a frame memory for storing video data corresponding to one image, and allows preventing temporal disparity between inputs and outputs of video data.
For example, as shown in
Specifically, the permutation control circuit 552 reads out first video data (video data corresponding to 1st gate line) as dummy data <D> from the odd line permutation memory, and then sequentially reads out video data corresponding to 10 gate lines (corresponding to 1st, 3rd, 5th, and 19th lines) and regards the 10 video data as a first set. Next, the permutation control circuit 552 reads out second video data (video data corresponding to 2nd gate line) as dummy data <D>, and then sequentially reads out video data corresponding to 10 gate lines (corresponding to 2nd, 4th, 6th, 20th lines), and then sequentially reads out video data corresponding to 10 lines (corresponding to 22nd, 24th, 26th, . . . , 40th lines) from the even line permutation memory, and regards the video data corresponding to 20 gate lines as a second set. Subsequently, from the odd line permutation memory again, the permutation control circuit 552 reads out 21st video data (video data corresponding to 21st gate line) as dummy data <D>, and then sequentially reads out video data corresponding to 10 gate lines (corresponding to 21st, 23rd, 25th, 39th lines) and regards the video data corresponding to 10 gate lines as a third set. The permutation control circuit 552 controls permutation so as to repeat these steps, and thus sequentially reads out all video data until reading out video data corresponding to the last line from the permutation memory.
In the present example, dummy data <d> at the top (which is identical with data corresponding to 1st line) is included in an effective display period VdispY. Alternatively, the dummy data <d> at the top may be positioned at the last of a vertical blanking period VblankY in a previous frame.
The following explains how to calculate the number a of dummy scanning periods to be provided for each set including M data and how to calculate a combination of the horizontal scanning period HtotalY and the dummy scanning period DtotalY in actual output in the above embodiments. The calculation may be carried out by the display control circuit 200 (liquid crystal panel driving device) as described above. In this case, the calculation may be carried out by a computer executing a predetermined program.
With the calculation, if M=10, the number of dummy scanning periods=1 and HtotalY=DtotalY=2000 dots, if M=30, the number of dummy scanning periods=3 and HtotalY=DtotalY=2000 dots, and if M=40, the number of dummy scanning periods=4 and HtotalY=DtotalY=2000 dots. Thus, it is possible to calculate a combination of HtotalY and DtotalY where HtotalY=DtotalY.
However, the calculation cannot be carried out if M=20. Therefore, the following calculation may be carried out as shown in
In S20, a combination of the number of dummy scanning periods=a, HtotalY=D, and DtotalY=D+F is stored, and the process goes back to S13. In S21, it is determined whether a stored combination exists or not, and if YES, the process goes to S22, and if NO, the process goes to S23 and carries out recalculation (mentioned later). In S22, one of stored combinations is selected and the process is finished.
In the recalculation in S23, α and β that meets the relation of HtotalX(2200)×M=M×α+C×β are calculated using C (the minimum number C of necessary dummy scanning periods that is obtained from the charging properties in M). Thus, the number of dummy scanning periods=C, HtotalY=α, and DtotalY=β.
The calculation in
(Example of Overshoot-driving a CS Signal).
The above explained a case of carrying out multi-pixel driving (MPD) in which a CS main line is shared by adjacent gate lines in block-divided interlace scan in which the polarity is inverted between even rows and odd rows. In this case, providing a dummy scanning period for preventing the influence of rounding of a waveform at the time of inversion of the polarity of a data signal as described above would require lengthening a wavelength of a CS signal by a period corresponding to the provided dummy scanning period when inverting the polarity of a data signal.
In this case, a period from rise or fall of a CS signal to a time of a gate-on pulse being off differs. In the example shown in
A point with a great gap from target luminance change is the point (4). That is, in the change of a voltage of a dark sub-pixel of the pixel P30 in
In order to solve the above problem, an overshoot pulse Poc with a predetermined width is generated with timing of rise or fall of a CS signal as shown in
Such CS signal allows improving rounding of a waveform at rise or fall of a pulse. In other words, even when a time from inversion of the polarity of a CS signal to gate-off timing is short, it is possible to increase a reaching ratio of a CS voltage at gate-off timing. This allows reducing a difference in a reaching ratio of a CS signal voltage which is caused by a difference in the period from rise or fall of a CS signal to gate-off timing. Further, even when the period from rise or fall of a CS signal to gate-off timing is short in one row and long in the other row, it is possible to prevent display unevenness due to a difference in a reaching ratio of a CS signal voltage. That is, it is possible to improve periodic display unevenness shown in
In the present example, the width of Poc is 1H. Alternatively, the width may be 2H. It should be noted that in order to stabilize a potential of a CS signal when a gate-on pulse gets off, it is desirable to make the width of Poc equal to or smaller than the period from rise or fall of a CS signal to gate-off timing.
On the other hand,
The magnitude of a voltage of a pulse Poc cannot be set to be larger than a breakdown voltage of the CS control circuit 90. Accordingly, when the horizontal period H is short, there is a case where a reaching ratio of a CS signal voltage remains insufficient even if a pulse Poc with the highest voltage is applied. In this case, the reaching ratio of a CS signal voltage differs depending on gate-off timing, and consequently the periodic display unevenness remains.
If the liquid crystal display device is configured such that a reaching ratio of a CS signal voltage in cases where a time from inversion of the polarity of a CS signal to gate-off timing is 4H or 5H is closer to a reaching ratio of a CS signal voltage in cases where the time is 6H or 7H, then it is possible to further reduce the display unevenness.
A reaching ratio of a CS signal voltage is higher in the period where a polarity inversion cycle is 7H than in the period where a polarity inversion cycle is 5H. Therefore, by setting the pulse width of the overshoot pulse Poc′ to be narrower than the pulse width of the overshoot pulse Poc, it is possible to make the reaching ratios of the CS signals in the two periods closer to each other. Further, also by changing application timing of the overshoot pulse Poc′, it is possible to make the reaching ratios of the CS signals in the two periods closer to each other. This allows further reducing the display unevenness.
In the example shown in
By changing at least one of a pulse width, application timing, and a voltage of an overshoot pulse according to the length of a polarity inversion cycle of a CS signal, it is possible to obtain the above effect.
(Example of Configuration for Reducing Display Unevenness Seen During Dummy Insertion Period)
In this case, to a polarity continuation period of a CS signal that exists at timing to insert a dummy insertion period is added a period to insert the dummy insertion period, i.e. 2H. That is, the polarity continuation period of a CS signal that exists at timing to insert a dummy insertion period is set to 8H and a polarity insertion period of other CS signal is set to 6H. Further, since the number a of scanning lines in one block is 24 that is an even number, providing 12 phases for a CS signal allows the CS signal to correspond to all CS lines.
In this type of block inversion driving, a blank is inserted at a part where the polarity is inverted and its vicinities. Consequently, a time from a moment when a gate-on pulse gets off to a moment of inversion of the polarity of a CS signal in 12th and 24th lines is greatly different from such time of other lines. For example, if a time t1 from a moment when a gate-on pulse of an upper sub-pixel of 12th line gets off to a moment of inversion of the polarity of a CS signal is compared with a time t2 from a moment when a gate-on pulse of a lower sub-pixel of 12th line gets off to a moment of inversion of the polarity of a CS signal, the comparison shows that t2 is longer by 3H than t1. Consequently, an average of a voltage variation per 1 frame of a pixel electrode due to a pushed-up/pulled-down voltage of a CS signal differs between a sub-pixel at a certain line and a sub-pixel at other lines. This may result in striped display unevenness.
The waveform of CS_N and the waveform of CS_O have opposite phases. Also in the case of the 24th line, a time from a moment when a gate-on pulse of a lower sub-pixel gets off to a moment when the polarity of a CS signal is inverted are equal to times of other lines, thereby reducing stripped display unevenness.
The above configuration is generalized as follows: In a driving method in which the number of scanning signal lines included in one block is α (α is a natural number) and a dummy insertion period is inserted at two or more points in scanning of one block, the retention capacitor lines should be driven in response to the retention capacitor signals with at least α/k (k is natural number: α and k are selected so that α/k is integer)+2 phases. In the example in
(Example of Configuration for Reducing Kinds of Phases of CS Signals)
In the example shown in the drawing, CS main lines A-H and J-M, i.e. 12 CS main lines in total, are used. A polarity continuation period of individual CS signals is 6H or 8H, and the polarity of a CS signal is inverted 4 times between application timings of gate-on pulses of an even line and an odd line adjacent to each other. This is because a polarity inversion cycle of a CS signal is shorter than an adjacent line writing time difference period.
In a case of a high driving frequency, when the polarity continuation period of a CS signal is short as described above, rounding of a waveform of a CS signal lowers a reaching ratio of a voltage of a CS signal to a target voltage at the time of gate off, which causes display unevenness. In order to improve the display unevenness, the polarity inversion cycle of a CS signal may be lengthened so as to reduce the influence of rounding of a CS signal. However, in order to lengthen the polarity inversion cycle of a CS signal, it is necessary to increase the number of kinds of phases of a CS signal, which requires increasing the number of CS main lines. This may increase the number of lines or complicate configuration of lines, which may require increasing the area of a substrate or may increase the possibility of short-circuit.
In this example, two CS lines with one CS line therebetween are connected with one CS main line. Specifically, CS lines 0, 2, 25, 27, 48, 50, 73, and 75 are connected with A of the CS main lines, and CS lines 1, 3, 24, 26, 49, 51, 72, and 74 are connected with B of the CS main lines. C, D, and thereafter of the CS main lines are connected with CS lines that are positioned by 4 lines away from the CS lines connected with A and B of the CS main lines. Further, the relation in connection between the CS main lines and the CS lines are repeated with respect to every 48 CS lines.
Further, in this driving example, a block including 48 scanning lines are subjected to interlace scan such that even rows are scanned and then odd rows are scanned (or vice versa), and a dummy scanning period of 2H is inserted when inverting the polarity of a data signal. Further, in order to correctly show brightness and darkness of a multi-pixel, a dummy scanning period of 2H is also inserted at a portion where the polarity is not inverted. A CS signal includes a signal whose polarity continuation period is 14H both in a L level period and a H level period, and a signal whose polarity continuation period is 12H both in a L level period and a H level period.
With the example shown in
The above example is further generalized as follows: m kinds of retention capacitor signals are generated, two retention capacitor lines with one retention capacitor line therebetween are driven with use of retention capacitor signals with a same phase, and one polarity continuation period is a (k×m) horizontal period, and a phase of a CS signal to be applied on (n+2(k+1))th CS line is delayed by (k+1) horizontal period with respect to a phase of a CS signal to be applied on nth retention capacitor line. In the above example, m=12 and k=1. With such driving, it is possible to secure a long polarity continuation period of a CS signal without increasing the number of phases of waveforms of CS signals.
Driving shown in
Polarity inversion timing of a CS signal and gate-on pulse timing in
(Example of Configuration for Removing Deviation in Polarity)
On the other hand, in a case of inserting a dummy horizontal period in block-divided interlace scan, it is necessary to lengthen a polarity continuation period of a CS signal in accordance with the length of a dummy horizontal period to be inserted. For example, in a case where a dummy horizontal period to be inserted is 2H, a polarity continuation period of 14H and a polarity continuation period of 12H coexists in the example in
(a) of
Here, attention is paid to the length of a period in which a CS signal is kept “H” (H level) in one frame period. A period in which a CS signal in (a) of
(c) of
In the examples shown in the drawings, the time indicated by hatching when a voltage is pushed up is 1H+12H+9H=22H in (c) and 12H+1H+9H=22H in (d), making the time when a voltage is pushed up equal both in (c) and (d). Consequently, an effective value of a voltage to be applied on liquid crystals is equal between a case of applying a gate-on pulse at (A) of (c) and a case of applying a gate-on pulse at (B) of (d).
Gate-on positions (1)-(14) in
Even if a period in which a CS signal is in H level and a period in which a CS signal is in L level are not completely equal to each other during a period for scanning one block, the difference in luminance can be substantially removed provided that a difference between the period in which a CS signal is in H level and the period in which a CS signal is in L level is 1H or less, preferably 0.5H or less. Further, it is desirable that a difference among retention capacitor lines in an absolute value of a difference between H level period and L level period of a retention capacitor signal in one frame is equal to or less than 1H, preferably 0.5H or less.
In the above example, the driving example in
Further, as shown in
(Configuration and Operation of Gate Driver)
The following details a configuration of the gate driver 400 used in the above Embodiments.
The gate driver IC41n includes a first shift register 42, a second shift register 43, a first AND gate 441, a second AND gate 442, and an output section 45. The first shift register 42 is a shift register for odd stages and the second shift register 43 is a shift register for even stages. The first AND gate 441 is provided so as to correspond to an output from the first shift register 42 and the second AND gate 442 is provided so as to correspond to an output from the second shift register 43. The output section 45 outputs scanning signals G1-Gp based on output signals g1-gp from the first AND gate 441 and the second AND gate 442.
The gate driver IC 41n receives start pulse signals SPia and SPib and clock signals CKa and CKb that are input to individual shift registers from the outside, and output control signals OEa and OEb. The start pulse signals SPia and Spib are input to input terminals of the first shift register 42 and the second shift register 43, respectively, and start pulse signals SPoa and SPob to be input to a subsequent gate driver IC are output from output terminals of the first shift register 42 and the second shift register 43.
The first AND gate 441 receives an even stage output signal Qk (k is an odd number) and a logic inversion signal of an output control signal OEa. On the other hand, the second AND gate 442 receives an odd stage output signal Qk (k is an even number) and a logic inversion signal of an output control signal OEb.
The gate driver 400 of the present configuration example is realized by cascade-connecting the plurality of (q) gate driver ICs 411-41q each having the above configuration. That is, in order that the first and second shift registers 42 and 43 in each of the gate driver ICs 411-41q constitute one shift register (shift register formed by cascade-connection in this manner is hereinafter referred to as “connection shift register”), output terminals of the first and second shift registers 42 and 43 in the gate driver IC 41n (output terminals for the start pulse signals SPoa and SPob) are connected with input terminals of the first and second shift registers 42 and 43 in the next gate driver IC (input terminals for the start pulse signals SPia and SPib).
It should be noted that gate start pulse signals GSPa and GSPb are input to input terminals of the first and second shift registers 42 and 43 in the gate driver IC 411 at the head and output terminals of the first and second shift registers 42 and 43 in the gate driver IC 41q at the end are not connected with the outside. Further, gate clock signals GCKa and GCKb and output control signals GOEa and GOEb from the display control circuit 200 are input as the clock signals CKa and CKb and the output control signals OEa and OEb to the gate driver IC 41n.
The following explains an operation of the gate driver 400 of the above configuration example with reference to a waveform chart of
When the gate start pulse signal GSP and the gate clock signal GCK (GCKa and GCKb) are input to the gate driver 400, output signals Q1 and Q2 are output from first stages of the first and second shift registers 42 and 43 in the gate driver IC 411 at the head. The output signals Q1 and Q2 include a pulse Pqw corresponding to the pixel data writing pulse Pw. Here, in order to generate the output signals Q1 and Q2 in the first stages, GCKa and GCKb in the first stages get H level with a distance of 2H.
Such pulse Pqw is sequentially transmitted through connection shift registers of the gate driver 400 in accordance with the gate clock signal GCK. Accordingly, output signals Qn whose signal waveform gets H level in accordance with rise of GCK and gets L level in accordance with next rise of GCK are output, sequentially and with a certain gap, from individual stages of the connection shift registers.
Further, as described above, the display control circuit 200 generates a gate driver output control signal GOE (GOEa and GOEb) to be supplied to the gate driver ICs 411-41q constituting the gate driver 400. A gate driver output control signal GOE to be supplied to nth gate driver IC 41n gets L level or H level due to adjustment of a pixel data writing pulse Pw during a period in which a pulse Pqw corresponding to the pixel data writing pulse Pw is output from any stage of the first and second shift registers 42 and 43 in the gate driver IC 41n. That is, GOE gets H level during the predetermined period, which will be hereinafter referred to as “writing period adjustment pulse”.
It should be noted that a pulse (writing period adjustment pulse) included in the gate driver output control signal GOE for the sake of adjustment of the pixel data writing pulse Pw can be appropriately adjusted in accordance with the pixel data writing pulse Pw required. Here, GOE is controlled in order that when the polarity (POL) of a data signal waveform is inverted, a signal potential right before inversion of the polarity is not written. Similarly, the width of a pulse Pw can be controlled in order that when the polarity (POL) of a data signal waveform is inverted, a signal potential right after polarity inversion is not written in response to a pulse Pw right before the polarity inversion. By adjusting the width controllable by GOE, it is possible to generate a pixel data writing pulse Pw corresponding to all of the above Embodiments when the polarity (POL) of a data signal waveform is inverted.
GCK consists of GCKa for controlling output of odd stages and GCKb for controlling output of even stages. These clock signals maintain H level in connection with inversion of the polarity POL of a data signal, and when a dummy insertion period (1H) has elapsed after one more inversion of the polarity of a data signal, the clock signals get L level, restarting basic operation of getting H level for a predetermined period with respect to 1H. In accordance with operation of the clock signals (GCKa and GCKb), the length of the waveform Pqw of the output signal Qk varies. Using this variation, a period during which a pixel data writing pulse Pw out of pulses Pqw should be output is controlled in response to the output control signals GOEa and GOEb (“writing period adjustment pulse”).
In the gate driver IC chips 41n (n ranges from 1 to q), in accordance with output signals Qk (k ranges from 1 to p) of individual stages of the shift registers, gate clock signals GCK, and gate driver output control signals GOE, the first and second AND gates 441 and 442 generate internal scanning signals g1 to gp, which are subjected to level conversion by the output section 45 and scanning signals G1 to Gp to be applied on the gate lines GL1 to GLm are output. Consequently, as shown in the waveform chart, pixel data writing pulses Pw are sequentially applied to the gate lines GL1 to GLm.
GCK consists of GCKa for controlling output of odd stages and GCKb for controlling output of even stages. These clock signals maintain L level in connection with inversion of the polarity POL of a data signal, and when a dummy horizontal period (1H) and a horizontal period (1H) for writing pixel data have elapsed after one more inversion of the polarity of a data signal, restarting basic operation of a clock signal getting H level for a predetermined period with respect to 1H.
In accordance with operation of the clock signals (GCKa and GCKb), the length of the waveform Pqw of the output signal Qk varies. Using this variation, a period during which a pixel data writing pulse Pw out of pulses Pqw should be output is controlled in response to the output control signals GOEa and GOEb (“writing period adjustment pulse”).
A pulse (writing period adjustment pulse) included in the gate driver output control signal GOE for the sake of adjustment of the pixel data writing pulse Pw can be appropriately adjusted in accordance with the pixel data writing pulse Pw required.
(Example of Double Pulse Driving)
In a case where a horizontal scanning period is required to be shorter in order to increase a scanning frequency, a pulse width of a gate-on pulse is also required to be shorter. This shortens a time for charging each pixel, resulting in insufficient charging. In order to avoid this problem, the present invention may be arranged such that charging of pixels may be carried out both during a main charging period in which a gate line is caused to be in a selected state so that source lines apply voltages on individual pixels and during a pre-charging period in which the same gate line is caused to be in a selected state with timing before the main charging period.
If driving in which a main charging period and a pre-charging period are provided is applied to the driving in
In this case, at a part where the polarity of a waveform of a data signal is inverted, the L period of the gate clock GCK is set to be longer in order to insert dummy data. This causes difference in waveform of a gate-on pulse between (i) a gate line in which a pre-charging period or a main charging period is set based on a long L period of the gate clock GCK and (ii) other gate lines. This causes different charging ratios among lines, resulting in difference in luminance.
Although the example in
As a countermeasure for this problem, the following explains a driving method in which the width of a gate-on pulse is set based not on the L period of GCK but on a combination of two signals: GCK and GOE. Initially, the width of a pulse Pqw on which a gate-on pulse Pw will be based is set to be a predetermined value (e.g. 2H) beforehand. Further, the length of a gate-on pulse may be slightly adjusted by masking the gate-on pulse with GOE. Further, by designing the present invention such that a gate-on pulse remains high even when a GOE pulse is generated (even in H level), it is possible to provide main charging periods that are common among all lines regardless of the GOE pulse. In this case, fixing GOE to H allows single pulse driving.
(Configuration and Operation of Gate Driver for Realizing Double Pulse (1))
Further, in an odd stage (Qk; stage with k being odd number out of 1 to p) of the shift register 46, the first AND gate 441 receives the output control signal OE and a logic inversion signal of the selection signal SEL, the second AND gate 442 receives the clock signal CK and the selection signal SEL, the first OR gate 444 receives outputs of the first AND gate 441 and the second AND gate 442, the third AND gate 443 receives a logic inversion signal of an output of the first OR gate 444 and an output signal Qk (k is odd number) from an odd stage of the shift register 46.
On the other hand, in an even stage (Qk; stage with k being even number out of 1 to p) of the shift register 46, the first AND gate 441 receives the output control signal OE and the selection signal SEL, the second AND gate 442 receives the clock signal CK and a logic inversion signal of the selection signal SEL, the first OR gate 444 receives outputs of the first AND gate 441 and the second AND gate 442, the third AND gate 443 receives a logic inversion signal of an output of the first OR gate 444 and an output signal Qk (k is even number) from an even stage of the shift register 46.
The gate driver 400 of the present configuration example is realized by cascade-connecting plural number of (q) gate driver ICs 411-41q. That is, an output terminal of the shift register 46 in the gate driver IC 41n is connected with an input terminal of the shift register 46 in the next gate driver IC 41n+1 so that the shift registers 46 in the gate driver ICs 411-41q form one shift register.
It should be noted that an input terminal of the shift register 46 in the gate driver IC 411 at the head receives a gate start pulse signal GSP from the display control circuit 200, and an output terminal of the shift register 46 in the gate driver IC chip 41q at the end is not connected with the outside. Further, a gate clock signal GCK, GOE, and SEL from the display control circuit 200 are supplied as a clock signal CK, an output control signal OE, and a selection signal SEL to each of the gate driver ICs 411-41q.
With reference to a waveform chart in
When the gate start pulse signal GSP and the gate clock signal GCK are input to the gate driver 400, an output signal Q1 is output from a first stage of the shift register 46 in the gate driver IC 411 at the head. The output signal Q1 includes a pulse Pqw corresponding to a pixel data writing pulse Pw in each frame period.
The pulse Pqw is sequentially transmitted through connection shift registers of the gate driver 400 in accordance with the gate clock signal GCK. Accordingly, output signals Qn whose signal waveform gets H level in accordance with rise of GCK and gets L level in accordance with two-posterior rise of GCK are output, sequentially and with a certain gap, from individual stages of the connection shift registers.
At timing when the polarity of a data signal is inverted after GCK gets H level, a distance between H level of GCK and next H level of GCK is 2H. The length of the waveform Pqw of the output signal Qk varies depending on the operation of the clock GCK.
Further, as described above, the display control circuit 200 generates the gate driver output control signal GOE and the selection signal SEL to be supplied to the gate driver ICs 411-41q that constitute the gate driver 400. One of GCK and GOE is selected in response to the selection signal SEL, the pulse width of the pulse Pqw is adjusted in response to the selected one, and the pixel data writing pulse Pw is set. In the drawing, “OE” and “CK” described in the pulse widths of Pqw and Pw indicate portions controlled in response to GOE and GCK, respectively.
In the gate driver IC chips 41n (n ranges from 1 to q), the first AND gate 441, the second AND gate 442, the first OR gate 444, and the third AND gate 443 generate internal scanning signals g1-gp based on the output signal Qk (k ranges from 1 to p) from individual stages of the shift register, the gate clock signal GCK, the gate driver output control signal GOE, and the selection signal SEL. The internal scanning signals g1-gp are subjected to level-conversion by the output section 45 and scanning signals G1-Gp to be applied on the gate lines GL1-GLm are output.
Consequently, pixel data writing pulses Pw having the same pulse width are sequentially applied to the gate lines GL1-GLm. Consequently, the length of a charging period is equal between a gate line at which the polarity of a data signal is inverted and other gate lines. This prevents the display unevenness.
As shown in
Gate-on pulses Pw at the time of polarity inversion of a data signal waveform shown in
An actual waveform of the data signal is rounded right after inversion of the polarity. That is, it takes time for the waveform of the data signal to reach a predetermined voltage after the inversion of the polarity. In order to deal with this problem, in the above driving example, a main charging period is not provided during 1 horizontal period right after the inversion of the polarity in order to provide a dummy horizontal period. Consequently, in a horizontal period next to the dummy insertion period, a data signal with the predetermined voltage is written in individual pixels.
Providing the dummy insertion period in this manner allows increasing a reaching ratio (charging ratio) of an actual voltage to an application voltage in the source lines SL1-SLn (data signal lines) when writing pixel data after the inversion of the polarity. This prevents display unevenness with respect to every 10 rows which is caused by rounding of the data signal waveform at the time of the inversion of the polarity.
Further, as shown in
With such driving, a gate-on pulse Pw is not applied at the time of inversion of the polarity. This allows preventing data signals with opposite polarities from being simultaneously applied to two adjacent gate lines to which gate-on pulses Pw are applied before and after inversion of the polarity, respectively. This allows preventing image display from being disturbed at the moment of polarity inversion.
Further, out of the gate-on pulses Pw applied after the moment of polarity inversion, the gate-on pulse Pw nearest to the moment of polarity inversion is gated on after a period longer than the first period has elapsed from the moment of polarity inversion. This prevents pre-charging of a pixel during a period where a data signal waveform is greatly rounded due to polarity inversion. This allows displaying an image with high quality that is free from display unevenness etc.
As described above, by setting the length of a dummy insertion period so as to include a time for an actual data signal to reach a predetermined voltage after inversion of the polarity, a data signal with the predetermined voltage is written in individual pixels. Providing the dummy insertion period in this manner allows increasing a reaching ratio of an actual voltage to an application voltage in the source lines SL1-SLn when writing pixel data after the inversion of the polarity. This prevents display unevenness with respect to every 10 rows which is caused by rounding of the data signal waveform at the time of the inversion of the polarity.
In the above examples, the dummy insertion period is 2H or 3H. Alternatively, the dummy insertion period may be set to 4H or more according to the degree of rounding of the data signal waveform after inversion of the polarity.
In the above driving, a gate-on pulse is applied such that a time from a moment of polarity inversion to a moment of an application start of a gate-on pulse Pw nearest to the moment of polarity inversion among gate-on pulses Pw applied after the moment of polarity inversion is equal to or longer than a horizontal display period obtained by subtracting a horizontal blanking period from a horizontal period.
As described above, a data signal applied on a source line is normally designed such that the data signal has a signal waveform that allows a pixel to be charged within one horizontal display period. Consequently, at a moment more than one horizontal display period after a moment of polarity inversion, the influence of rounding of a data signal waveform which is caused by the polarity inversion is prevented. This allows preventing a pixel from being charged during a period in which a data signal waveform is greatly rounded due to polarity inversion, allowing high-quality display with subdued display unevenness.
In the above configuration example, a gate-on pulse Pw as a double pulse is applied by appropriately selecting a gate clock GCK, a pulse width of a gate driver output control signal GOE, and a selection signal SEL. Alternatively, the configuration may, be arranged not to use a selection signal SEL.
As shown in the drawing, the gate driver unit includes a first flip-flop 461, a second flip-flop 462, a first output mask 463, a second output mask 464, and an OR gate 465. The first flip-flop 461 receives a gate start pulse signal GSP, operates in response to a gate clock signal GCK, and outputs an output signal QA. The first flip-flop 462 receives the output signal QA, operates in response to the gate clock signal GCK, and outputs an output signal QB.
The first output mask 463 masks the output signal QA with use of a gate driver output control signal GOE and outputs the masked signal. The second output mask 464 outputs the output signal QB only during a period in which the gate clock signal GCK is in L level. The OR gate 465 outputs, as a scanning signal G, the result of OR logic operation of a signal from the first output mask 463 and a signal from the second output mask 464. Although not shown in the drawing, the first flip-flop 461 outputs the output signal QA to a first flip-flop of a gate driver unit in a subsequent stage and this process is sequentially repeated. Thus, the gate driver units constitute a shift register and serves as a gate driver.
The following explains an operation of the gate driver 400 of the above configuration example with reference to the waveform chart in
When such gate start pulse signal GSP and such gate clock signal GCK are supplied to the gate driver 400, an output signal QA1 is output from the first flip-flop 461 in the gate driver unit at the head.
The gate start pulse GSP is sequentially transmitted through the gate driver units in accordance with the gate clock signal GCK. Accordingly, output signals QAk whose signal waveform gets H level in accordance with fall of GCK and gets L level in accordance with one-posterior fall of GCK are output, sequentially and with a certain gap, from individual stages of the connection shift registers.
Further, at timing when the polarity of a data signal is inverted after GCK gets H level, GCK is kept at H level for 1H. The pulse width of an output signal QAk varies according to the operation of the clock GCK.
In response to output of an output signal QAk from the first flip-flop 461, the second flip-flop 462 outputs an output signal QBk in accordance with GCK. That is, the output signal QBk is obtained by delaying the output signal QAk by 1H.
Further, as described above, the display control circuit 200 generates the gate driver output control signal GOE to be supplied to the gate driver ICs 411-41q that constitute the gate driver 400. This GOE is a signal that gets H level only during 1H period right before polarity inversion of a data signal and gets L level during other periods. By controlling a pulse width of GOE when keeping H level, masking by the first output mask 463 controls the length of a pre-charging period of a scanning signal Gk. In accordance with the output signal QBk and GCK, masking by the second output mask 464 sets a main charging period for the scanning signal Gk.
Consequently, pixel data writing pulses Pw with the same pulse width are sequentially applied to the gate lines GL1-GLm without using the selection signal SEL. This makes the length of a charging period equal between a gate line at which the polarity of a data signal is inverted and other gate line, allowing prevention of the display unevenness.
Further, the present invention may be arranged so that two series of gate driver units are provided for odd lines and even lines, and input signals GSPa, GSPb, GCKa, GCKb, GOEa, and GOEb for odd lines and even lines are supplied to the gate driver units for odd lines and the gate driver units for even lines, respectively, as in the later-mentioned configuration in
(Configuration and Operation of Gate Driver for Realizing Double Pulse (2))
The first shift register 42 is for odd lines and the second shift register 43 is for even lines. The logic circuit A is provided so as to correspond to an output from the first shift register 42 and the logic circuit B is provided so as to correspond to an output from the second shift register 43. The output section 45 outputs scanning signals G1-Gp based on output signals g1-gp from the logic circuits A and B.
The gate driver IC 41n receives start pulse signals SPia and SPib and clock signals CKa and CKb that are supplied from the outside to respective shift registers, output control signals OEa and OEb, and selection signals SELa and SELb. The start pulse signals SPia and SPib are supplied to input terminals of the first shift register 42 and the second shift register 43, respectively, and start pulse signals SPoa and SPob to be supplied to a subsequent gate driver IC are output from output terminals of the first shift register 42 and the second shift register 43, respectively.
Each of the logic circuits A and B includes a first AND gate 441, a second AND gate 442, a third AND gate 443, and a first OR gate 444.
In an odd stage (corresponding to Q(4k−3) (k=1, 2 . . . )) of the logic circuit A, the first AND gate 441 receives the output control signal OEa and a logic inversion signal of the selection signal SELa, the second AND gate 442 receives the clock signal CKa and the selection signal SELa, the first OR gate 444 receives outputs of the first AND gate 441 and the second AND gate 442, the third AND gate 443 receives a logic inversion signal of an output of the first OR gate 444 and an output signal Q(4k−3) from an odd stage of the shift register.
In an even stage (corresponding to Q(4k−1) (k=1, 2 . . . )) of the logic circuit A, the first AND gate 441 receives the output control signal OEa and the selection signal SELa, the second AND gate 442 receives the clock signal CKa and a logic inversion signal of the selection signal SELa, the first OR gate 444 receives outputs of the first AND gate 441 and the second AND gate 442, the third AND gate 443 receives a logic inversion signal of an output of the first OR gate 444 and an output signal Q(4k−1) from an odd stage of the shift register.
In an odd stage (corresponding to Q(4k−2) (k=1, 2 . . . )) of the logic circuit B, the first AND gate 441 receives the output control signal OEb and a logic inversion signal of the selection signal SELb, the second AND gate 442 receives the clock signal CKb and the selection signal SELb, the first OR gate 444 receives outputs of the first AND gate 441 and the second AND gate 442, the third AND gate 443 receives a logic inversion signal of an output of the first OR gate 444 and an output signal Q(4k−2) from an odd stage of the shift register 46.
In an even stage (corresponding to Q(4k) (k=1, 2 . . . )) of the logic circuit B, the first AND gate 441 receives the output control signal OEb and the selection signal SELb, the second AND gate 442 receives the clock signal CKb and a logic inversion signal of the selection signal SELb, the first OR gate 444 receives outputs of the first AND gate 441 and the second AND gate 442, the third AND gate 443 receives a logic inversion signal of an output of the first OR gate 444 and an output signal Q(4k) from an odd stage of the shift register.
The gate driver 400 of the present configuration example is realized by cascade-connecting plural number of (q) gate driver ICs 411-41q each having the above configuration. That is, output terminals of the first shift register 42 and the second shift register 43 in the gate driver IC 41n are connected with input terminals of the first shift register 42 and the second shift register 43 in the next gate driver IC so that the first shift registers 42 and the second shift registers 43 in the gate driver ICs 411-41q form one shift register.
It should be noted that input terminals of the first shift register 42 and the second shift register 43 in the gate driver IC 411 at the head receive gate start pulse signals GSPa and GSPb from the display control circuit 200, respectively, and output terminals of the first shift register 42 and the second shift register 43 in the gate driver IC 41q at the end are not connected with the outside. Further, gate clock signals GCKa and GCKb, output control signals GOEa and GOEb, and selection signals SELa and SELb from the display control circuit 200 are supplied as clock signals CKa and CKb, output control signals OEa and OEb, and selection signals SELa and SELb to each gate driver IC 41n.
With reference to waveform charts in
As shown in the waveform chart, the display control circuit 200 generates a gate start pulse signal GSP (GSPa for odd line and GSPb for even line) serving as a signal that gets H level only during a period Tspw corresponding to a pixel data writing pulse Pw, and generates a gate clock signal GCK (GCKa for odd line and GCKb for even line) that gets H level basically only for a predetermined period with respect to 1 horizontal scanning period (1H) except for a moment right after polarity inversion of a data signal.
When the gate start pulse signal GSP and the gate clock signal GCK (GCKa and GCKb) are input to the gate driver 400, output signals Q1 and Q2 are output from first stages of the first shift register 42 and the second shift register 43 in the gate driver IC 411 at the head. Each of the output signals Q1 and Q2 includes a pulse Pqw corresponding to a pixel data writing pulse Pw in each frame period.
The pulse Pqw is sequentially transmitted through connection shift registers of the gate driver 400 in accordance with the gate clock signal GCK. Accordingly, output signals Qn whose signal waveform gets H level in accordance with rise of GCK and gets L level in accordance with two-posterior rise of GCK are output, sequentially and with a certain gap, from individual stages of the connection shift registers.
GCK consists of GCKa for controlling output of odd stages and GCKb for controlling output of even stages. These clock signals maintain H level in connection with inversion of the polarity POL of a data signal, and when a dummy insertion period (1H) has elapsed after one more inversion of the polarity of a data signal, the clock signals get L level, restarting basic operation of getting H level for a predetermined period with respect to 1H. The length of the waveform Pqw of the output signal Qk varies depending on the operation of the clock (GCKa and GCKb).
Further, as described above, the display control circuit 200 generates the gate driver output control signal GOE (GOEa and GOEb) and the selection signals SELa and SELb to be supplied to the gate driver ICs 411-41q that constitute the gate driver 400. One of GCK and GOE is selected in response to the selection signal SEL, the pulse width of the pulse Pqw is adjusted in response to the selected one, and the pixel data writing pulse Pw is set. In the drawing, “OEa(b)” and “CKa(b)” described in the pulse widths of Pqw and Pw indicate portions controlled in response to GOEa(b) and GCKa(b), respectively.
In the gate driver IC chips 41n (n ranges from 1 to q), the first and second AND gates 441 and 442, the first OR gate 444, and the third AND gate 443 generate internal scanning signals g1 to gp in accordance with output signals Qk (k ranges from 1 to p) from individual stages of the shift registers, the gate clock signals GCK, the gate driver output control signals GOE, and the selection signals SEL. The internal scanning signals g1-gp are subjected to level conversion by the output section 45 and scanning signals G1 to Gp to be applied on the gate lines GL1 to GLm are output.
Consequently, pixel data writing pulses Pw with the same pulse width are sequentially applied to the gate lines GL1-GLm. This allows making the length of a charging period equal between a gate line at which the polarity of a data signal is inverted and other gate line, allowing prevention of the display unevenness.
The present invention may be arranged so that as shown in
[Configuration of Television Receiver]
Next, the following explains one example of configuration of applying the liquid crystal display device according to the present invention to a television receiver.
In the display device 800 of the aforementioned configuration, a complex color video signal Scv as a television signal is inputted from the outside to the Y/C separation circuit 80. In the Y/C separation circuit 80, the complex color video signal Scv is separated into a luminance signal and a color signal. The luminance signal and the color signal are converted to analog RGB signals corresponding to three fundamental colors of light in the video chroma circuit 81. Further, the analog RGB signals are converted to digital RGB signals by the A/D converter 82. The digital RGB signals are inputted to the liquid crystal controller 83. Moreover, in the Y/C separation circuit 80, horizontal and vertical sync signals are extracted from the complex color video signal Scv inputted from the outside. These sync signals are also inputted to the liquid crystal controller 83 via the microcomputer 87.
The liquid crystal controller 83 outputs data signals for drivers based on the digital RGB signals (corresponding to the aforementioned digital video signals Dv) from the A/D converter 82. Further, the liquid crystal controller 83 generates, based on the sync signals, timing control signals for causing the source driver and the gate driver in the liquid crystal panel 84 to operate as in the above Embodiments, and supplies the timing control signals to the source driver and the gate driver. Further, in the gradation circuit 88, gradation voltages of three fundamental colors R, G, and B of color display are generated, and these gradation voltages are also supplied to the liquid crystal panel 84.
In the liquid crystal panel 84, drive signals (e.g., data signals and scanning signals) are generated by the source and gate drivers inside the liquid crystal panel 84 in accordance with the data signals for drivers, the timing control signals, and the gradation voltages. A color image is displayed on a display section inside the liquid crystal panel 84 in accordance with the drive signals. It should be noted that for displaying an image by the liquid crystal panel 84, light needs to be irradiated from a rear of the liquid crystal panel 84. In the display device 800, the backlight drive circuit 85 drives the backlight 86 under control by the microcomputer 87 and thereby light is irradiated on a back side of the liquid crystal panel 84.
Control of the whole system, including the aforementioned processes is carried out by the microcomputer 87. As the video signal (complex color video signal) inputted from the outside, not only a video signal in accordance with television broadcast but also a video signal picked up by a camera or supplied via the Internet line is also usable. In the display device 800, image display in accordance with various video signals can be performed.
In displaying an image by the display device 800 in accordance with television broadcast, a tuner section 90 is connected to the display device 800, as shown in
The invention being thus described, it will be obvious that the same way may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
For convenience of explanation, data signal lines are provided so as to extend in a column direction and scanning signal lines are provided so as to extend in a row direction. It is needless to say that the present invention also encompasses a configuration in which the screen is rotated by 90 degrees.
The liquid crystal display device of the present invention is applicable to various display devices such as a monitor for a personal computer and a television receiver.
| Number | Date | Country | Kind |
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| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/055950 | 3/27/2008 | WO | 00 | 12/8/2009 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2008/152847 | 12/18/2008 | WO | A |
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