Patent Grant
10008173
This application claims priority to Taiwanese Patent Application No. 104131972 filed on Sep. 30, 2015, the contents of which are incorporated by reference herein.
The subject matter herein generally relates to a liquid crystal displays.
Metal-oxide thin film transistors which are used in liquid crystal display devices can include a channel layer made of metal-oxide semiconductor. A leakage current of the metal-oxide thin film transistor will cause afterimages.
Implementations of the present technology will now be described, by way of example only, with reference to the attached figures.
It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure.
The term “comprising” means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in a so-described combination, group, series, and the like.
The liquid display panel 110 includes a plurality of scan lines 102, a plurality of data lines 104 insulated from the scan lines 102, a plurality of thin film transistors (TFTs) 108, a plurality of pixel electrodes 111, a plurality of common electrodes 112, and a plurality of storage capacitors 116. The scan lines 102 and the date lines 104 cross each other and define a plurality of pixels 106. The TFTs 108 are located at intersections of the scan lines 102 and the data lines 104. The pixel electrodes 111 are located at intersections of the scan lines 102 and the data lines 104. A pixel electrode 111, a corresponding common electrode 112, and liquid crystal molecules therebetween (not shown) cooperate with each other to form a liquid crystal capacitor 114. The liquid crystal capacitor 114 is electrically connected with the storage capacitor 116 in parallel. A gate electrode (not labeled) of the TFT 108 is electrically connected to the a scan line 102, a source electrode (not labeled) of the TFT 108 is electrically connected to a data line 104, and a drain electrode (not labeled) of the TFT 108 is electrically connected to a pixel electrode 111. The common electrode 112 is electrically connected to the common voltage generating circuit 170 via a common electrode line 118.
The driving circuit 130 includes a time controller 132, a gate driver 134, a data driver 136, and a discharging circuit 138. The time controller 132 receives image data from an external circuit 115, and can generate time signals to the gate driver 134 and the data driver 136. The time controller 132 can also generate data signals to the data driver 136 based on the received image data. The gate driver 134 generates pulses to the scan lines 102 in response to the controller signals. The data driver 136 can transform the received data signals into grayscale voltages in response to a data signal and a time controller signal. The discharging control circuit 138 is electrically connected to the time controller 132, the gate driver 134, and the data driver 136. The discharging control circuit 138 can be controlled by the time controller signal generated by the time controller 132. The discharging control circuit 138 includes a detection unit 1381 and a control unit 1383. The detection unit 1381 can detect a decrease in the external voltage VCC. The control unit 1383 can generate different control signals to the gate driver 134, the data driver 136, the common voltage generating circuit 170, and the power chip 150 based on a detected decrease in voltage VCC. In at least one embodiment, the time controller 132 can output a clock signal CLK, a driving control signal DCC, and a gate driving control signal GDC. The time controller 132 outputs the clock signal CLK to the gate driver 132 and the data driver 136.
In a second time period P2 of the power-on process, the gate driver 134 outputs the turn-on signal VGH in a logic low signal and the turn-off signal VGL in a logic high signal based on the Gate ON signal. The TFTs 108 are all turned on simultaneously, which causes the pixel electrodes 111 to discharge. No voltage is generated by the common voltage generating circuit 170, and the common voltage generating circuit 170 itself discharges via the common electrode lines 118.
In a third time period P3 of the power-on process, the common voltage generating circuit 170 outputs the common voltage to the common electrode lines 118. The time controller 132 controls the liquid crystal display device 100 to display a black display.
In a fourth time period P4 of the power-on process, the time controller 132 receives the image data provided by the external circuit 115, and outputs the time controller signals and the data signals based on the image data, the data driver 136 outputting the data signals to the TFTs 108.
In the third time period P3 of the power-off process, the turn-off signal VGL is in a logic high signal, and the common voltage generating circuit 170 stops generating the common voltage Vcom. The discharging circuit 138 outputs the Source ON signal in a logic low signal, which causes the data driver 136 to stop outputting any data signal. The discharging circuit 138 outputs the Gate ON signal in a logic low signal. Thus, the liquid capacitor 114 fully discharges via the common electrode lines 118.
In the fourth time period P4 of the power-off process, the power signal Power of the power chip 150 becomes zero.
In a second time period TP2 of the cutoff process, the power signal of the power chip 150 keeps decreasing. The turn-off signal VGL generated by the gate driver 134 is in a logic high signal, and the turn-on signal VGH generated by the gate driver 134 decreases gradually. The common voltage generating circuit 170 stops outputting the common voltage Vcom. Thus, the liquid crystal capacitor 114 can fully discharge.
In the third time period TP3 of the cutoff process, the Source ON signal is switched to a logic low signal, and the power signal Power of the power chip 150 keeps decreasing.
In the fourth time period TP4 of the cutoff process, the power signal Power of the power chip 150 becomes zero, and the liquid crystal display device 100 is powered off.
The discharging circuit of the liquid crystal display device 100 enables the common electrode lines to be fully discharged by being grounded, and a display performance of the liquid crystal display device 100 is improved.
While various exemplary and preferred embodiments have been described, the disclosure is not limited thereto. On the contrary, various modifications and similar arrangements (as would be apparent to those skilled in the art) are intended to also be covered. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 104131972 A | Sep 2015 | TW | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20040130543 | Sun | Jul 2004 | A1 |
| 20050253832 | Chung | Nov 2005 | A1 |
| 20080165101 | Kim | Jul 2008 | A1 |
| 20080180429 | Park | Jul 2008 | A1 |
| 20130147697 | Sung | Jun 2013 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20170092218 A1 | Mar 2017 | US |
