Patent Application
20120274889
The present invention relates to a liquid crystal display device. More specifically, the present invention relates to a liquid crystal display device that adopts a driving method using a thin film transistor.
A liquid crystal display (LCD) device is a device which performs display in such a manner that the optical property of light emitted from a light source is controlled by using a liquid crystal layer, and the like, filled between a pair of substrates, and is widely used in various fields by taking advantage of its features, such as thin profile, light weight and low power consumption.
In the liquid crystal display device, an alignment state of liquid crystal molecules is changed by applying a voltage to the liquid crystal layer by using a pair of electrodes formed on the substrates, and thereby a polarization state of the light passing through the liquid crystal layer is changed. In the liquid crystal display device, color filters of a plurality of colors are formed to perform color display. The pair of substrates sandwiching the liquid crystal layer are held by spacers so as to have a uniform gap (cell gap) therebetween and are bonded to each other by a sealing material.
In the liquid crystal display device, subsidiary pixels of three colors of red (R), green (G) and blue (B) are usually formed. A color filter of each color is arranged for each of the subsidiary pixels, and color control is performed for each pixel by adjusting light passing through the color filter of each color.
In recent years, there has been made such a contrivance that, in addition to the RGB, a white (W) subsidiary pixel is arranged in order to increase luminance (see, for example, Patent Literature 1). Further, a method has also been investigated in which the areas of the RGBW subsidiary pixels are made different for each color so as to suitably adjust color balance (see, for example, Patent Literature 2).
In the liquid crystal display device, pixel electrodes are usually arranged in a matrix form, and each of the pixel electrodes is driven through a switch formed by a thin film transistor (TFT). The TFT is a three terminal field-effect transistor, and a drain electrode of each of the TFTs is connected to the pixel electrode corresponding to the TFT. A gate electrode of each of the TFTs is connected to a gate bus line of each row of the matrix. A source electrode of each of the TFTs is connected to a source bus line of each column of the matrix. A desired image can be obtained by applying an image signal to the source bus line and by sequentially scanning the gate bus line.
Some of the liquid crystal display devices have a multi-gap configuration in which a thickness (cell gap) of the liquid crystal layer is made different for the subsidiary pixel of each color. However, when a size of the cell gap is made different, a value of capacitance associated with the pixel electrode is changed. Therefore, in order to eliminate the difference in the pixel capacitance between the subsidiary pixels, it is necessary to make contrivances such as (a) making storage capacitance different for each of the pixels by equalizing pixel electrode areas or (b) equalizing the storage capacitance between the pixels by making the pixel electrode areas different from each other (see, for example, Patent Literature 3).
Further, in the liquid crystal display device, in order to solve a viewing angle dependency problem due to a difference in y characteristics between the time when the display is viewed in a front direction and the time when the display is viewed in an oblique direction, there is a case where a pixel is divided into a plurality of sub-pixels, and where the y characteristics of the respective sub-pixels are made close to each other (see, for example, Patent Literature 4) . The y characteristics mean gradation dependency of display luminance. That the y characteristics are different between the time when the display is viewed in the front direction and the time when the display is viewed in the oblique direction means that a gradation display state is changed according to the observation direction. The viewing angle dependency problem due to the y characteristics can be eliminated in such a manner that a state having different y characteristics is formed by applying a different voltage to the liquid crystal layer corresponding to each of the sub-pixels.
Further, as a method for forming a spacer, a method has also been tried in which, when color filters are formed in correspondence with RGB subsidiary pixels, the color filters are also similarly formed at a place where the spacer is to be formed, and are laminated to form the spacer (see, for example, Patent Literature 5) . In Patent Literature 5, in order to compensate a change in the capacitance of each pixel electrode due to the spacer formed in the subsidiary pixel, a method has been investigated which equalizes a capacitance ratio of each of the respective pixels by changing a size of storage capacitor line.
During the investigation of a liquid crystal display device including subsidiary pixels (hereinafter also referred to as picture elements) of a plurality of colors, the present inventors paid attention to a phenomenon in which, when thicknesses (cell gaps) of the liquid crystal layer are different between the picture elements, and when a white window screen is displayed on a halftone background for a long time and then a halftone solid screen is displayed, only the color in the portion corresponding to the white window is seen to be different from the color of the background portion.
The present inventors made various investigations about the cause of occurrence of such phenomenon and found out that the image sticking occurs in the display because the cell gaps of the picture elements are different from each other and thereby the voltages applied to the liquid crystal layer are made different from each other, so that the liquid crystal capacitance is made different for each of the picture elements.
When the liquid crystal capacitance is different for each picture element, the value of the electrostatic capacitance formed by the pixel electrode is also different for each of the picture elements.
The signal waveforms shown on a left side of
Further, according to the investigation of the present inventors, it was found that such variation in the optimum opposed voltage causes image sticking so as to affect the display.
The present invention has been made in view of the above described circumstances. An object of the present invention is to provide a liquid crystal display device which hardly causes image sticking even when the thicknesses of the liquid crystal layer for the picture elements are made different from each other.
In order to suppress the image sticking, the present inventors have investigated various methods for making the optimum opposed voltage equal between the picture elements, and paid attention to the fact that one of factors required to adjust the optimum opposed voltage is ΔVd described above. When the values of ΔVd of the picture elements are made close to each other, the optimum opposed voltages are also made equal to each other between the picture elements. The value of ΔVd can be expressed as ΔVd=α×Vgp-p. As shown in
As a result of an extensive investigation of means for effectively adjusting the value of α, the present inventors paid attention to a channel region of TFT and found out that the balance of suitable pixel capacitance can be effectively adjusted by making the channel region of TFT different for each of the picture elements. The channel region of TFT means a region in a semiconductor layer, which region forms a passage (channel) that enables current to flow between the source electrode and the drain electrode according to the charges supplied to the gate electrode.
The size of the channel region of TFT has a large influence on the characteristics of TFT. As the width of the channel region is increased, the current characteristic becomes better, and a change in the size of the channel region exerts an influence on all the capacitances Cgd, Csd, Ccs, and Clc which are components of Cpix.
The present inventors found out that the optimum opposed voltage can be easily made equal between the picture elements by connecting a TFT having a larger width of the channel region to a pixel electrode that overlaps a region having a smaller thickness of the liquid crystal layer, and thereby the generation of image sticking can be suppressed. As a result, the present inventors came up with an idea that, with such means, the above described problems can be effectively solved, and reached the present invention.
That is, the present invention is to provide a liquid crystal display device which includes a pair of substrates, and a liquid crystal layer sandwiched between the pair of substrates, and in which a pixel is formed by picture elements of a plurality of colors, the liquid crystal display device being featured in that one of the pair of substrates includes scanning lines, signal lines, and storage capacitor lines, a thin film transistor connected to each of the scanning line and the signal line, and a pixel electrode connected to the thin film transistor, in that the other of the pair of substrates includes an opposed electrode, in that the liquid crystal layer includes a region having a larger thickness and a region having a smaller thickness in one pixel, in that the pixel electrode is arranged for each of the picture elements, and in that the pixel electrode that overlaps a region having a smaller thickness of the liquid crystal layer among the plurality of pixel electrodes arranged in one pixel is connected to the thin film transistor having a larger channel width among the plurality of the thin film transistors arranged in the one pixel.
The liquid crystal display device of the present invention includes a pair of substrates, and a liquid crystal layer sandwiched between the pair of substrates, and is configured such that a pixel is formed by picture elements of a plurality of colors. For example, one of the pair of substrates can be used as an array substrate, and the other of the pair of substrates can be used as a color filter substrate. The picture elements of the plurality of colors can be realized by color filters respectively arranged in correspondence with picture elements, and various display colors can be expressed by adjusting the balance of the respective colors.
One of the pair of substrates includes scanning lines (hereinafter also referred to as gate bus lines), signal lines (hereinafter also referred to as source bus lines), storage capacitor lines (hereinafter also referred to as Cs bus lines), a thin film transistor (TFT) connected to each of the scanning lines and each of the signal lines, and a pixel electrode connected to the thin film transistor. The drain electrode of each of the TFTs is connected to the pixel electrode corresponding to the TFT. The gate electrode of each of the TFTs is connected to the gate bus line of each row. The source electrode of each of the TFTs is connected to the source bus line of each column. A desired image can be obtained by supplying an image signal to the source bus line and by applying a voltage to the gate bus line at a predetermined timing.
In the above-described configuration, it is necessary that the scanning line, the signal line, the storage capacitor line, the thin film transistor, and the pixel electrode are arranged respectively via insulating films, or the like, and at certain intervals so as to be electrically isolated from each other. Further, the pixel electrode and the opposed electrode are arranged to be separated from each other via the liquid crystal layer. Therefore, a certain amount of electrostatic capacitance is formed between each of the lines and each of the electrodes, and between the electrodes. Specifically, the scanning line and the pixel electrode form gate-drain capacitance (Cgd), the signal line and the pixel electrode form source-drain capacitance (Csd), the storage capacitor line and the pixel electrode form a storage capacitance (Ccs), and the pixel electrode and the opposed electrode form liquid crystal capacitance (Clc).
The other of the pair of substrates includes the opposed electrode. Since an electric field is formed between the pixel electrode and the opposed electrode, and since each of the pixel electrodes is individually controlled by the thin film transistor, the orientation of the liquid crystal can be controlled for each of the picture elements, and thereby the whole screen can be precisely controlled.
The liquid crystal layer has a region having a larger thickness and a region having a smaller thickness in one pixel. The light-control characteristics can be made different between the regions by making a thickness (cell gap) of the liquid crystal layer different for each region.
The pixel electrode is arranged for each of the picture elements, and the pixel electrode that overlaps a region having a smaller thickness of the liquid crystal layer among the plurality of pixel electrodes arranged in one pixel is connected to the thin film transistor having a larger channel width among the plurality of the thin film transistors arranged in the one pixel. The channel width does not mean the interval between the source electrode and the drain electrode (hereinafter also referred to as channel length) in plan view of a thin film transistor, but means the width of the region formed by the source electrode and the drain electrode which face each other. There is a correlation between the channel width and the value of pixel capacitance, and there is a correlation between the value of pixel capacitance and the value of cell gap. When a TFT having a larger channel width is connected to a pixel electrode that overlaps a region having a smaller thickness of the liquid crystal layer, and when a TFT having a smaller channel width is connected to a pixel electrode that overlaps a region having a larger thickness of the liquid crystal layer, the variation of the optimum opposed voltage between the picture elements can be suppressed on the basis of the characteristics of the TFTs.
The configuration of the liquid crystal display device of the present invention is not especially limited as long as it essentially includes such components. Preferable embodiments of the liquid crystal display device of the present invention are mentioned in more detail below.
It is preferred that the overlapping area of the scanning line and the pixel electrode that overlaps a region having a smaller thickness of the liquid crystal layer is different from the overlapping area of the scanning line and the pixel electrode that overlaps a region having a larger thickness of the liquid crystal layer. Thereby, the value of the gate-drain capacitance (Cgd) formed between the scanning line and the pixel electrode can be changed, and hence more suitable adjustment can be performed.
It is preferred that the overlapping area of the signal line and the pixel electrode that overlaps a region having a smaller thickness of the liquid crystal layer is different from the overlapping area of the signal line and the pixel electrode that overlaps a region having a larger thickness of the liquid crystal layer. Thereby, the value of the source-drain capacitance (Csd) formed between the signal line and the pixel electrode can be changed, and hence more suitable adjustment can be performed.
It is preferred that the overlapping area of the storage capacitor line and the pixel electrode that overlaps a region having a smaller thickness of the liquid crystal layer is different from the overlapping area of the storage capacitor line and the pixel electrode that overlaps a region having a larger thickness of the liquid crystal layer. Thereby, the value of the storage capacitance (Ccs) formed between the storage capacitor line and the pixel electrode can be changed, and hence more suitable adjustment can be performed.
It is preferred that the area of the pixel electrode that overlaps a region having a smaller thickness of the liquid crystal layer is different from the area of the pixel electrode that overlaps a region having a larger thickness of the liquid crystal layer. Thereby, the value of the electrostatic capacitance (Cpix) formed by the pixel electrode can be changed, and hence more suitable adjustment can be performed.
It is preferred that the scanning line and the pixel electrode form the gate-drain capacitance (Cgd), that the signal line and the pixel electrode form the source-drain capacitance (Csd), that the storage capacitor line and the pixel electrode form the storage capacitance (Ccs), that the pixel electrode and the opposed electrode form the liquid crystal capacitance (Clc), that the ratio of the gate-drain capacitance to the total of the gate-drain capacitance, the source-drain capacitance, the storage capacitance, and the liquid crystal capacitance (the value of this ratio of the gate-drain capacitance is hereinafter set as a) is different for each of the picture elements of the plurality of colors, and that, among the ratios of the gate-drain capacitance respectively obtained for the picture elements of the plurality of colors, the difference between the largest ratio of the gate-drain capacitance and the smallest ratio of the gate-drain capacitance is 10% or less of the smallest ratio of the gate-drain capacitance.
It is preferred that the values of α of the picture elements in this case are close to each other. Further, when the values of α are set in the above-described range, the difference between the optimum opposed voltages of the respective picture elements can be eliminated so that the image sticking can be sufficiently suppressed.
It is preferred that, in the one picture element, the value of the response coefficient (“Cpix(min)/Cpix(max)”) obtained by calculating a ratio of the maximum value of the total of the gate-drain capacitance, the source-drain capacitance, and the storage capacitance, and the liquid crystal capacitance, with respect to the minimum value of the total of the gate-drain capacitance, the source-drain capacitance, and the storage capacitance, and the liquid crystal capacitance is different for each of the picture elements of the plurality of colors, and that, among the response coefficients respectively obtained for the picture elements of the plurality of colors, the difference between the largest response coefficient and the smallest response coefficient is 5% or less of the smallest response coefficient.
It is preferred that the pixel electrode is configured by a plurality of sub-pixel electrodes divided from each other in one picture element, that the thin film transistors are connected to the sub-pixel electrodes respectively, that the storage capacitor lines overlap the sub-pixel electrodes respectively, and that the liquid crystal display device includes a driving circuit which inverts the polarity of the voltage of the storage capacitor line at regular time intervals. In the following, the method, in which one picture element is controlled by using a plurality of sub-pixel electrodes in this way, is also referred to as a multi-driving method. When a plurality of sub-pixel electrodes are arranged in the same picture element and are respectively driven by different effective voltages, a state where different y characteristics are mixed is formed, so that the visual angle dependency based on the y characteristics can be eliminated. Further, an increase in the number of extra lines can be prevented by driving the sub-pixel electrodes by the multi-driving method using the change in the voltage of the storage capacitor line.
It is preferred that the ratio of the storage capacitance with respect to the total of the gate-drain capacitance, the source-drain capacitance, and the storage capacitance, and the liquid crystal capacitance (the value of this ratio of the storage capacitance is hereinafter set as K) is different for each of the picture elements of the plurality of colors, and that, among the ratios of the storage capacitance respectively obtained for the picture elements of the plurality of colors, the difference between the largest ratio of the storage capacitance and the smallest ratio of the storage capacitance is 1.0% or less of the smallest ratio of the storage capacitance.
With the liquid crystal display device of the present invention, the variation in the optimum opposed voltage is adjusted between the picture elements, and hence the generation of image sticking can be suppressed.
The present invention will be mentioned in more detail referring to the drawings in the following embodiments, but is not limited to these embodiments.
A liquid crystal display device of Embodiment 1 includes gate bus lines 11 extending in the row direction (lateral direction), and source bus lines 12 extending in the column direction (longitudinal direction) . Further, the liquid crystal display device includes a TFT 14 connected to both of the gate bus line 11 and the source bus line 12. The TFT 14 is also connected to a pixel electrode 15. Further, the liquid crystal display device includes a Cs bus line 13 which overlaps at least a part of the pixel electrode 15. For example, as shown in
In Embodiment 1, a kind of color filter is arranged for one picture element. Examples of the kinds, the number and the arrangement order of colors of the picture elements configuring a pixel include, but are not limited in particular to, combinations, such as RGB, RGBY and RGBW. The color of a picture element is determined by a color filter. Examples of arrangement forms of color filters include a stripe arrangement, as shown in
A liquid crystal capacitance Clc is formed by the pixel electrode and the opposed electrode which are arranged to face each other via the liquid crystal layer. The value of Clc is dependent on an effective voltage (V) applied to the liquid crystal layer by the pair of electrodes. A storage capacitance Ccs is formed by the pixel electrode and the Cs bus line (storage capacitor line) which are arranged to face each other via an insulating layer. A gate-drain capacitance Cgd is formed by the pixel electrode and the gate bus line (scanning line) which are arranged to face each other via an insulating layer. A source-drain capacitance Csd is formed by the pixel electrode and the source bus line (signal line) which are arranged to face each other via an insulating layer.
The TFT (thin film transistor) includes a semiconductor layer made of silicon, and the like, and three electrodes of a gate electrode, a source electrode, and a drain electrode. The pixel electrode is connected to the drain electrode of the TFT. The gate electrode of the TFT is connected to the gate bus line, and the source electrode of the TFT is connected to the source bus line.
A scanning signal supplied to the gate bus line in a pulse-like manner at a predetermined timing is applied to each of the TFTs at a predetermined timing (by line-sequential writing, every other line writing, two-line simultaneous writing, or the like). Then, an image signal supplied from the source bus line is applied to the pixel electrode connected to the TFT which is turned on for a predetermined time period by the input of the scanning signal.
The image signal having a predetermined level, which is written in the liquid crystal layer for each of the picture elements, is held, for a predetermined time period, between the pixel electrode with the image signal applied thereto and the opposed electrode facing the pixel electrode. After the image signal is applied, the image signal held between the pixel electrode and the opposed electrode may leak, but in order to prevent this leakage, the storage capacitance Ccs is formed in parallel with the liquid crystal capacitance Clc formed between the pixel electrode and the opposed electrode.
Each of
As shown in
As shown in
In Example 1, a voltage applied to the inside of the liquid crystal layer 1 through the electrodes 41 and 42 of the pair of substrates is different for each picture element. This is because the thickness of the liquid crystal layer 1 corresponding to the blue picture element is set thinner than the thicknesses of the liquid crystal layer 1 corresponding to the other picture elements in Example 1. A liquid crystal capacitance formed in the blue picture element is larger than those formed in the other picture elements. Thus, in the case of forming a multi-gap configuration, an optimum opposed voltage is different for each picture element.
In Example 1, the balance between the values of α=Cgd/ (Cgd+Csd+Ccs+Clc) of the picture elements is adjusted using the channel width of the TFT. Specifically, a TFT having a smaller cell gap is arranged for the pixel electrode having a larger area. Therefore, the channel width of the TFT arranged for the blue picture element is larger than the channel width of the TFT arranged for the red picture element, and is larger the channel width of the TFT arranged for the green picture element.
Thereby, it is possible to easily adjust, for each of the picture elements, the balance of the gate-drain capacitance (Cgd) formed between the gate bus line and the pixel electrode, the source-drain capacitance (Csd) formed between the source bus line and the pixel electrode, the storage capacitance (Ccs) formed between the Cs bus line and the pixel electrode, and the liquid crystal capacitance (Clc) formed between the pixel electrode and the opposed electrode.
The drain electrode 23 is extended toward the center of the picture element, and is formed to have a certain spread. A contact hole 24 is formed through the insulating layer formed on a portion 23a having the fixed spread, and the drain electrode 23 and the pixel electrode are electrically connected to each other via the contact hole 24.
The portion 23a of the drain electrode 23, which portion has the certain spread, can form a storage capacitance together with the Cs bus line arranged under the portion 23a via the insulating layer.
The semiconductor layer provided in the TFT 14 overlaps both of the source electrode 22 and the drain electrode 23. The region of the semiconductor layer, which region overlaps the source electrode 22, is a source region, and the region of the semiconductor layer, which region overlaps the drain electrode 23, is a drain region. Further, the region of the semiconductor layer, which region does not overlap both of the source electrode 22 and the drain electrode 23, and which region is located between the source electrode 22 and the drain electrode 23 in plan view, is a channel region 21. Therefore, the semiconductor layer 21 has three regions of the source region, the channel region 21, and the drain region.
The channel region 21, which overlaps the gate bus line 11, enables an image signal to be supplied from the source electrode 22 to the drain electrode 23 only when a scanning signal is inputted into the gate bus line 11. Since the length (distance between the source electrode 22 and the drain electrode 23) of the channel region 21 is determined to be an appropriate value to some extent, it is not preferred to change the length of the channel region 21 for each of the picture elements, but the width d of the channel region 21 can be adjusted. When the width d of the channel region 21 with respect to the length of the channel region 21 is expanded, the conductivity of the TFT 14 can be further improved. Therefore, in Example 1, the channel width d in the blue picture element is formed to be larger than the channel width d in the red and green picture elements.
Thereby, the value of the gate-drain capacitance (Cgd) formed between the gate bus line and the pixel electrode is changed, and hence, by the use of this change, the values of the optimum opposed voltages in the picture elements are respectively adjusted so as to become close to each other.
In Example 1, it is preferred that the values of α of the picture elements are close to each other. Specifically, it is preferred that the ratio of the values of α of the picture elements, which ratio is expressed as: “(maximum value of a −minimum value of α)/(minimum of value of α),” is 10% or less. When the values of α of the picture elements are set close to each other, the variation in ΔVd which is the pull-in voltage is suppressed, and thereby the optimum opposed voltages between the picture elements are made close to each other. Thereby, the possibility of occurrence of image sticking can be greatly reduced. The value of α is obtained by the expression: α=Cgd/Cpix (Cgd+Csd+Ccs+Clc) . For this reason, the parameters included in the expression need to be adjusted, in order to adjust the balance between the values of α of the picture elements. The balance between the values of α of the picture elements can be effectively adjusted by adjusting the channel width.
The following will describe in detail a plurality of combination for making cell gaps different between picture elements referring to examples.
Each of
In the relationship between the cell gaps of the red and blue picture elements, a form is assumed in which one of the cell gaps of the red and blue picture elements is larger than the other. When the, cell gap of the red picture element is larger than the cell gap of the blue picture element, the color filters are configured as shown in
Each of
In the following, there will be described an example in which, in the liquid crystal display device of Example 1, the value of α is adjusted by actually adjusting the channel width.
As shown in
In the example shown in
The width of the drain electrode 23 is denoted by reference character c, and the interval between the drain electrode 23 and the source electrode 22 in the direction in parallel with the gate bus line 11 is denoted by reference character d. The distance between the drain electrode 23 and the source electrode 22 in the direction in parallel with the source bus line 12 is denoted by reference character e. The length of the portion of the source electrode 22, which portion faces the drain electrode 23 and which portion is in parallel with the gate bus line 11, is denoted by reference character a. The length obtained by subtracting the length of the portion of the source electrode 22 which portion is in parallel with the source bus line 12 from the length of the portion of the gate electrode 25, which portion is in parallel with the source bus line 12, is denoted by reference character b.
In the liquid crystal display device of Example 1, in the case where, in three color picture elements having multi-gap configuration, the cell gaps of the picture elements were set as “blue”>“red=green,” the deviation between the values of a of the picture elements could be suppressed to 0.81% by adjusting the values of a to e between the picture elements as shown in Table 1 described below. Further, ΔVd in the blue picture element was 1.619 V, and ΔVd in each of the red and green picture elements was 1.606 V. The difference between the maximum and minimum values of ΔVd was 13 mV. Therefore, according to the above-described design, it was possible to obtain a liquid crystal display device in which the generation of image sticking is suppressed by sufficiently adjusting the optimum opposed voltages between the picture elements. Note that the ratio of the cell gap of each of the picture elements was set as “blue”:“red”:“green”=1.1:1.0:1.0.
The following Table 2 is a table showing permissible ranges of the deviation of the value of α when the difference of the value of ΔVd is assumed to be less than 100 mV in the liquid crystal display device of the present invention. It is seen that, when the difference between the values of ΔVd is 100 mV or less, the image sticking can be easily improved, and that, when the difference between the values of ΔVd is 50 mV or less, the image sticking can be more surely improved.
As shown in Table 2 described above, the deviation of the value of α was 10.0% at the time when the value of ΔVd was set to 1.0 V, and when the difference between the values of ΔVd was set to 100 mV. The deviation of the value of α was 6.7% at the time when the value of ΔVd was set to 1.5 V, and when the difference between the values of ΔVd was set to 100 mV. The deviation of the value of α was 5.0% at the time when the value of ΔVd was set to 2.0 V, and when the difference between the values of ΔVd was set to 100 mV. The deviation of the value of a was 3.3% at the time when the value of ΔVd was set to 3.0 V, and when the difference between the values of ΔVd was set to 100 mV.
It was found to be preferred that, in a normal liquid crystal display device, the value of ΔVd is set in the range of 1.5 to 3.0 V, and that, under this condition, the deviation of the value of α is set in the range of 7.0% or less. Further, it is conceivable that the value of ΔVd may be set as ΔVd=1 V or less in future, and it was found to be preferred that, in this case, the deviation of the value of α is set in the range of 10.0% or less.
Note that, in the case where a normal liquid crystal display device, in which the cell gap and the channel width of each of picture elements were set to be the same, was investigated as a comparison example, the deviation of the value of a was 8.0% (between picture elements R), and ΔVd was 183 mV (between picture elements R).
Further, when a relationship between the channel size and the cell thickness ratio in the liquid crystal display device of the present invention was investigated, data as shown in Table 3 and
The variation of the value of α is suppressed between the picture elements by changing the values of a to e of the TFT channel according to Table 3 and along the straight line shown in
Further, the difference in the lengths of the source electrode and the drain electrode between the TFTs shown in
As described above, in Embodiment 1, the balance between the values of α=Cgd/(Cgd+Csd+Ccs+Clc) of the picture elements is adjusted. As can be seen from the above-described expression, it is effective to adjust the gate-drain capacitance Cgd in order to adjust the balance between the values of α of the picture elements.
Actually, the difference in the overlapping area of the drain electrode and the gate bus line in the TFT also influences the gate-drain capacitance (Cgd) formed between the gate bus line and the drain electrode. Since, as the overlapping area of the gate bus line and the drain electrode is increased, the value of the gate-drain capacitance (Cgd) is increased, the balance between the values of α of the picture elements can be adjusted also by adjusting the overlapping area of the gate bus line and the drain electrode.
Each of
Each of
The gate-drain capacitance (Cgd) formed between the gate bus line and the drain electrode is also formed in the region in which the gate bus line and the pixel electrode directly overlap each other. Since, as the overlapping area of the gate bus line and the pixel electrode is increased, the value of the gate-drain capacitance (Cgd) is increased, the balance between the values of α of the picture elements can be adjusted also by adjusting the overlapping area of the gate bus line and the pixel electrode.
Each of
In this way, when the overlapping area of the drain electrode and the gate bus line, and the overlapping area of the pixel electrode and the gate bus line are adjusted, the value of each electrostatic capacitance formed in association with the pixel electrode can be adjusted for each of the picture elements, and thereby the value of the opposed voltage can be more optimized for each of the picture elements.
In Embodiment 1, it is preferred that the value of “Cpix(min)/Cpix(max)” (hereinafter also referred to as response coefficient) is set to be the same between the picture elements. Reference character Cpix(min) denotes pixel capacitance at the time of black display, and reference character Cpix(max) denotes pixel capacitance at the time of white display. The response coefficient denoted as “Cpix(min)/Cpix(max)” is one of the indicators of the response characteristics of liquid crystal. When the values of the response coefficient are different between the picture elements, the response characteristic becomes different for each of the colors, and hence desired chromaticness may not be obtained.
The response coefficient “Cpix(min)/Cpix(max)” can be adjusted by performing, as described above, the adjustment of the TFT channel width, the adjustment of the overlapping area of the gate bus line and the drain electrode, the adjustment of the overlapping area of the pixel electrode and the gate bus line, the adjustment of the overlapping area of the pixel electrode and the Cs bus line, and the like.
To cope with this, the change in the chromaticness can be suppressed by making the values of response coefficients of the picture elements close to each other.
The liquid crystal display device of Embodiment 2 includes the gate bus line 11 extended in the row direction (lateral direction), and the source bus line 12 extended in the column direction (longitudinal direction). Further, the liquid crystal display device includes a first TFT 14a and a second TFT 14b each of which are connected to both the gate bus line 11 and the source bus line 12. The first TFT 14a is connected to a first sub-pixel electrode 15a, and the second TFT 14b is connected to a second sub-pixel electrode 15b. Further, the liquid crystal display device of Embodiment 2 includes a first Cs bus line 13a which overlaps at least a part of the first sub-pixel electrode 15a, and a second Cs bus line 13b which overlaps at least a part of the second sub-pixel electrode 15b. As shown in
In Embodiment 2, a kind of color filter is arranged for one picture element. Examples of the kinds, the number and the arrangement order of colors of the picture elements configuring a pixel include, but are not limited in particular to, combinations, such as RGB, RGBY and RGBW. The color of a picture element is determined by a color filter. Examples of arrangement forms of color filters include a stripe arrangement, as shown in
In Embodiment 2, each of the two sub-pixel electrodes forms sub-pixel capacitance having a different capacitance value. Examples of the method for making the sub-pixel capacitance different for each of the sub-pixel electrodes include (1) a method of supplying a signal voltage from each of different source bus lines, and (2) a method of adjusting the signal voltage by changing the voltage of the Cs bus line. The TFTs are connected to the sub-pixel electrodes respectively. Each of the TFTs is connected to the same gate bus line, and hence the two sub-pixels are simultaneously controlled at the timing at which a scanning signal is supplied to the gate bus line.
The liquid crystal capacitance Clc is formed by the pixel electrode and the opposed electrode which are arranged to face each other via the liquid crystal layer. The value of Clc is dependent on the effective voltage (V) applied to the liquid crystal layer by the pair of electrodes. The storage capacitance Ccs is formed by the pixel electrode and the Cs bus line (storage capacitor line) which are arranged to face each other via an insulating layer. The gate-drain capacitance Cgd is formed by the pixel electrode and the gate bus line (scanning line) which are arranged to face each other via an insulating layer. The source-drain capacitance Csd is formed by the pixel electrode and the source bus line (signal line) which are arranged to face each other via an insulating layer.
The method for driving each of the sub-pixel electrodes by using the TFTs, and the basic configuration in Embodiment 2 are the same as those in Embodiment 1.
In the following, a method for performing the multi-pixel drive by changing the voltage of the Cs bus line will be described in detail.
When a voltage Vg is changed from VgL to VgH at the time of T1, the first TFT 14a and the second TFT 14b are simultaneously switched to conductive state (on-state), so that a voltage Vs is transmitted to each of the first and second sub-pixel electrodes 15a and 15b from the source bus line 12, and is charged to the first and second sub-pixel electrodes 15a and 15b. Similarly, the first and second Cs bus lines 13a and 13b respectively overlapping the first and second sub-pixel electrodes 15a and 15b are also charged by the voltage supplied from the source bus line 12.
Next, when the voltage Vg of the gate bus line 11 is changed from VgH to VgL at the time of T2, the first TFT 14a and the second TFT 14b are simultaneously switched to non-conductive state (off-state), the first and second sub-pixel electrodes 15a and 15b, and the first and second Cs bus lines 13a and 13b are all electrically insulated from the source bus line 12.
Note that, immediately after this change, each of the voltages Vlc1 and Vlc2 of the first and second sub-pixel electrodes 15a and 15b is reduced by substantially a same voltage ΔVd as follows, due to the pull-in phenomenon caused by the influence of the parasitic capacitance, and the like, associated with the first TFT 14a and the second TFT 14b.
Vlc1=Vs−ΔVd
Vlc2=Vs−ΔVd
Further, at this time, the voltage Vcs1 and Vcs2 of the first and second Cs bus lines 13a and 13b become as follows.
Vcs1=Vcom−Vad
Vcs2=Vcom+Vad
At the time of T3, the voltage Vcs1 of the first Cs bus line 13a is changed from Vcom−Vad to Vcom+Vad, and the voltage Vcs2 of the second Cs bus line 13b is changed from Vcom+Vad to Vcom−Vad. According to these voltage changes in the first Cs bus line 13a and the second Cs bus line 13b, the voltages Vlc1 and Vlc2 of the first and second sub-pixel electrodes 15a and 15b are changed as follows.
Vlc1=Vs−ΔVd+2×Vad×Ccs1/(Clc1+Ccs1)
Vlc2=Vs−ΔVd−2×Vad×Ccs2/(Clc2+Ccs2)
At the time of T4, Vcs1 is changed from Vcom+Vad to Vcom−Vad, and Vcs2 is changed from Vcom−Vad to Vcom+Vad. Before the time T4, the voltages Vlc1 and Vlc2 are respectively expressed as follows.
Vlc1=Vs−ΔVd+2×Vad×Ccs1/(Clc1+Ccs1)
Vlc2=Vs−ΔVd−2×Vad×Ccs2/(Clc2+Ccs2)
At the time of T4, also, the voltages Vlc1 and Vlc2 are respectively changed to the voltages expressed as follows.
Vlc1=Vs−ΔVd
Vlc2=Vs−ΔVd
At the time of T5, Vcs1 is changed from Vcom−Vad to Vcom +Vad, and Vcs2 is changed from Vcom+Vad to Vcom−Vad. Before the time of T5, the voltages Vlc1 and Vlc2 expressed as follows.
Vlc1=Vs−ΔVd
Vlc2=Vs−ΔVd
At the time of T5, also, the voltages Vlc1 and Vlc2 are respectively changed to the voltages expressed as follows
Vlc1=Vs−ΔVd+2×Vad×Ccs1/(Clc1+Ccs1)
Vlc2=Vs−ΔVd−2×Vad×Ccs2/(Clc2+Ccs2)
For each interval of an integer multiple of horizontal writing time 1H, the voltages Vcs1, Vcs2, Vlc1, and Vlc2 respectively repeat the changes caused at the time of T4 and T5. Whether the repeating interval of the changes caused at the time of T4 and T5 is set to be equal to the horizontal writing time 1H, or set to twice, 3 times, or more of the horizontal writing time 1H, may be suitably determined in view of the driving method (for example, polarity inversion drive) and displaying conditions (flickering, roughness of display, and the like) of the liquid crystal display device. This repetition is continued until the time equivalent to T1 is subsequently reached. Therefore, the effective values of voltages Vlca and Vlcb of the sub-pixel electrodes become as follows, respectively.
Vlca=Vs−ΔVd+Vad×Ccs1/(Clc1+Ccs1)
Vlcb=Vs−ΔVd−Vad×Ccs2/(Clc2+Ccs2)
Therefore, the effective voltages V1 and V2, which are respectively applied to the liquid crystal layer by the first and second sub-pixel electrodes 15a and 15b, are set to values different from each other and expressed as follows.
V1=Vlc1−Vcom
V2=Vlc2−Vcom
That is, the effective voltages V1 and V2 are expressed as follows.
V1=Vs−ΔVd+Vad×Ccs1/(Clc1+Ccs1)−Vcom
V2=Vs−ΔVd−Vad×Ccs2/(Clc2+Ccs2)−Vcom
Under the above-described premises, the adjustment of the optimum opposed voltages between the respective picture elements in Embodiment 2 will be described in detail below.
In Embodiment 2, similarly to Embodiment 1, the balance between the values of α=Cgd/(Cgd+Csd+Ccs+Clc) of the picture elements is adjusted by using the channel width of TFT. Further, the balance between the values of α=Cgd/(Cgd+Csd +Ccs+Clc) of the picture elements is also supplementarily adjusted by using the gate-drain overlapping area. As the methods for adjusting the balance between the values of α in Embodiment 2, methods similar to the methods described in Embodiment 1 can be used.
In Embodiment 2, it is preferred that K-values are set to be equal to each other between the sub-pixels. When the K-values are set to be equal to each other, the values of the electrostatic capacitance formed by the respective sub-pixel electrodes are made uniform, and the adjustment between the sub-pixels is more suitably performed. Thereby, it is possible to further reduce the possibility that the value of α is varied between the picture elements. The K-value is expressed as K=Ccs/Cpix (Cgd+Csd+Ccs+Clc). Therefore, the adjustment of Ccs is effective to adjust the balance between the K-values of the picture elements.
The longitudinal length and the lateral length of the expanded portion 23a of the drain electrode 23 are denoted by reference characters of d and f, respectively. Further, the longitudinal length and the lateral length of the expanded portion of the Cs bus line 13 are denoted by reference characters of e and g, respectively.
On the same one side of the expanded portions, the distance between the longitudinal side of the expanded portion of the Cs bus line 13 and the longitudinal side of the expanded portion 23a of the drain electrode 23 is set to a. That is, the expanded portion 23a of the drain electrode 23 is formed on the laterally inner side of the expanded portion of the Cs bus line 13 by the distance a from each of the longitudinal sides of the expanded portion of the Cs bus line 13. Therefore, the expression g=f+2a is established.
On the same one side of the expanded portions, the distance between the lateral side of the expanded portion of the Cs bus line 13 and the lateral side of the expanded portion of the drain electrode 23 is set to b. That is, the expanded portion of the drain electrode 23 is formed on the longitudinally inner side of the expanded portion of the Cs bus line 13 by the distance b from each of the lateral sides of the expanded portion of the Cs bus line 13. Therefore, the expression e=d+2b is established.
In such case, when, in the four color picture elements having different cell gaps, the pitch widths were set as “red =blue”<“green=yellow,” the deviation between the K-values (maximum value−minimum value) of the picture elements could be suppressed to 0.10% by respectively adjusting the values of a to g between the picture elements as shown in Table 4 described below. Note that the ratio of the cell gaps of the respective picture elements was set as “red” : “blue”: “green”: “yellow”=1:1:1.4:1.4.
Each of
The values of the storage capacitance Ccs between the sub-pixels are made close to each other by performing these adjustments between the sub-pixels, so that the K-values within a suitable range can be obtained.
Table 5 described below is a table showing a permissible range of deviation of the value of K when the value of ΔVcs is assumed to be 10 mV or less. In the conventional liquid crystal display device in which the areas of the picture elements are not made different from each other, the value of K is set in the range of 0.43 to 0.54, and hence the investigation was performed on the basis of this range.
As shown in Table 5 described above, when the value of K was set to 0.54 and when the deviation of the value of K was set to 0.74%, the deviation of the value of ΔVcs could be suppressed to 7.7 mV. Further, when the value of K was set to 0.43 and when the deviation of the value of K was set to 0.93%, the deviation of the value of ΔVcs could be suppressed to 9.6 mV. Therefore, the target range of the value of K is 1.0% or less.
Each of
In Embodiment 3, three color picture elements of red, green and blue, or four color picture elements of red, green, blue and yellow are used, and one pixel is configured by a combination of these picture elements. In Embodiment 3, the areas of the picture elements are different from each other.
In Embodiment 3, the optimum opposed voltage is adjusted between the picture elements by using the channel width of the TFT, and the optimum opposed voltage is further adjusted by adjusting the picture element area between the picture elements. Thereby, it is possible to obtain a liquid crystal display device in which the variation of the value of α is further suppressed between the picture elements and thereby the image sticking is reduced.
The present application claims priority to Patent Application No. 2010-019563 filed in Japan on Jan. 29, 2010 under the Paris Convention and provisions of national law in a designated State, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-019563 | Jan 2010 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2010/069003 | 10/26/2010 | WO | 00 | 7/5/2012 |
