This application relates to a liquid crystal display device, and more particularly, to a technology of horizontally dividing a screen into a plurality of display regions and vertically scanning the plurality of display regions in parallel.
Liquid crystal display devices are used in products such as a flat panel TV, a personal computer, a tablet terminal, and a smartphone. Particularly in applications of large-sized panels as represented by the flat panel TV, in order to achieve high-definition image display and three-dimensional display and in order to improve a moving image quality, there are demands for increase in the number of pixels, such as 4K resolution (4K2K), and drive at a higher frame rate, such as double-speed or quad-speed drive. Those demands may shorten a data writing time that is assigned to each horizontal scanning line in vertical scanning of a screen, and may cause a problem that data written to a pixel is insufficient when a general drive method is employed. As one solution to this problem, there is known a divisional-drive method involving dividing the screen into a plurality of display regions and writing data into the respective display regions in parallel.
However, in a divisional drive involving horizontally dividing the screen into two regions, upper and lower display regions, the following problem arises: an unintended brightness change appears at a boundary between the display regions in a display image of the liquid crystal display device, and a joint of the display regions is visible on the image. A solution to the problem has been discussed in Japanese Patent Application Laid-open Nos. 2000-321552, 2008-70406, and Hei 11-102172.
Regarding the above-mentioned problem that the joint of the display regions is visible, there are causes that are not discussed in the above-mentioned patent literatures.
The signals VSU and VSD are each set to a reference voltage VBLK, which corresponds to a pixel value representing black, during a blanking period TBLK of the vertical scanning. On the other hand, during the effective scanning period TEFF, the signal VSU and VSD are respectively set to signal voltages Vk and Vn+k, which represent pixel values Dk and Dn+k of pixels in k-th and (n+k)th rows, in synchronization with the scanning pulse Pk. In this case, for simplifying the description, it is assumed that the pixel values D1 to D2n of 2n pixels arrayed in a direction along the source line (column direction) are the same. In correspondence to this, in
The insufficient writing to pixels in the head row in the vertical scanning occurs even in the head row in a general drive method that does not horizontally divide the screen. However, brightness reduction due to the insufficient writing to pixels occurs in the row at the end of the screen, and hence the brightness reduction is less obvious. As compared thereto, the brightness change in a region other than that at the end of the screen is visually recognizable as in the above-mentioned display region AD.
This application has been made to solve the above-mentioned problem, and has an object to provide a liquid crystal display device configured to perform a horizontal divisional drive, in which, in a case where one of a plurality of display regions obtained by dividing a screen starts vertical scanning from a row that is adjacent to another display region, an unintended brightness change appears less at a boundary between the display regions.
According to one embodiment of this application, there is provided a liquid crystal display device, including: video lines, which are provided in each of a plurality of display regions obtained by horizontally dividing a screen including a plurality of pixels arranged in matrix, so as to correspond to respective columns of the plurality of pixels; a scanning line drive circuit configured to sequentially supply a selection signal to a plurality of scanning lines, which are provided in each of the plurality of display regions so as to correspond to respective rows of the plurality of pixels, to thereby perform vertical scanning of the plurality of display regions in parallel; and a video line drive circuit configured to: apply, during a blanking period of the vertical scanning, a predetermined reference voltage to the video lines; and apply, during an effective scanning period of the vertical scanning, a signal voltage corresponding to a pixel value via one of the video lines to corresponding one of the plurality of pixels in a selected row that is supplied with the selection signal via one of the plurality of scanning lines, the liquid crystal display device being configured to divisionally drive the screen, in which the scanning line drive circuit starts the vertical scanning for a specific scanning display region predetermined out of the plurality of display regions from a pixel row that is adjacent to another of the plurality of display regions, and in which the video line drive circuit sets, in at least the specific scanning display region out of the plurality of display regions, an application start timing of the signal voltage related to a supply start timing of a selection signal to be earlier in a selected row at a head of the effective scanning period than in a selected row subsequent thereto.
According to another embodiment of this application, there is provided a liquid crystal display device, including: video lines, which are provided in each of a plurality of display regions obtained by horizontally dividing a screen including a plurality of pixels arranged in matrix, so as to correspond to respective columns of the plurality of pixels; a scanning line drive circuit configured to sequentially supply a selection signal to a plurality of scanning lines, which are provided in each of the plurality of display regions so as to correspond to respective rows of the plurality of pixels, to thereby perform vertical scanning of the plurality of display regions in parallel; and a video line drive circuit configured to: apply, during a blanking period of the vertical scanning, a predetermined reference voltage to the video lines; and apply, during an effective scanning period of the vertical scanning, a signal voltage corresponding to a pixel value via one of the video lines to corresponding one of the plurality of pixels in a selected row that is supplied with the selection signal via one of the plurality of scanning lines, the liquid crystal display device being configured to divisionally drive the screen, in which the scanning line drive circuit starts the vertical scanning for a specific scanning display region predetermined out of the plurality of display regions from a pixel row that is adjacent to another of the plurality of display regions, and in which the video line drive circuit applies, in at least the specific scanning display region out of the plurality of display regions, instead of the predetermined reference voltage, a preset voltage corresponding to the pixel value of an intermediate grayscale during a transition period of a predetermined length at an end of the blanking period prior to a start of application of the signal voltage during the effective scanning period.
According to still another embodiment of this application, there is provided a liquid crystal display device, including: video lines, which are provided in each of a plurality of display regions obtained by horizontally dividing a screen including a plurality of pixels arranged in matrix, so as to correspond to respective columns of the plurality of pixels; scanning lines provided so as to correspond to respective rows of the plurality of pixels; a switching element that is provided in each of the plurality of pixels and is configured to control conduction between a pixel electrode and corresponding one of the video lines based on a voltage applied to corresponding one of the scanning lines; a scanning line drive circuit configured to sequentially apply a selection voltage for passing electricity through the switching element to a plurality of the scanning lines provided in each of the plurality of display regions, to thereby perform vertical scanning of the plurality of display regions in parallel; and a video line drive circuit configured to: apply, during a blanking period of the vertical scanning, a predetermined reference voltage to the video lines; and apply, during an effective scanning period of the vertical scanning, a signal voltage corresponding to a pixel value via one of the video lines to corresponding one of the plurality of pixels in a selected row that is applied with the selection voltage via one of the scanning lines, the liquid crystal display device being configured to divisionally drive the screen, in which the scanning line drive circuit is configured to: start the vertical scanning for a specific scanning display region predetermined out of the plurality of display regions from a pixel row that is adjacent to another of the plurality of display regions; and control, in at least the specific scanning display region out of the plurality of display regions, the selection voltage so that the switching element in a selected row at a head of the effective scanning period enters a conductive state with a resistance lower than a resistance of a selected row subsequent thereto.
According to still another embodiment of this application, there is provided a liquid crystal display device, including: video lines, which are provided in each of a plurality of display regions obtained by horizontally dividing a screen including a plurality of pixels arranged in matrix, so as to correspond to respective columns of the plurality of pixels; a scanning line drive circuit configured to sequentially supply a selection signal to a plurality of scanning lines, which are provided in each of the plurality of display regions so as to correspond to respective rows of the plurality of pixels, to thereby perform vertical scanning of the plurality of display regions in parallel; and a video line drive circuit configured to: apply, during a blanking period of the vertical scanning, a predetermined reference voltage to the video lines; and apply, during an effective scanning period of the vertical scanning, a signal voltage corresponding to a pixel value via one of the video lines to corresponding one of the plurality of pixels in a selected row that is supplied with the selection signal via one of the plurality of scanning lines, the liquid crystal display device being configured to divisionally drive the screen, in which the scanning line drive circuit starts the vertical scanning for a specific scanning display region predetermined out of the plurality of display regions from a pixel row that is adjacent to another of the plurality of display regions, and in which the video line drive circuit sets, in at least the specific scanning display region out of the plurality of display regions, during at least a part of a period of applying the signal voltage corresponding to a pixel value in a selected row at a head of the effective scanning period, the signal voltage to be larger than a signal voltage that is applied to another selected row for the pixel value.
According to this application, in the liquid crystal display device configured to perform the horizontal divisional drive, in the case where one of the plurality of display regions obtained by dividing the screen starts the vertical scanning from the row that is adjacent to another display region, the unintended brightness change can be made less likely to appear at the boundary between the display regions, and an image quality can be enhanced.
Now, modes for carrying out this application (hereinafter referred to as “embodiments”) are described with reference to the drawings.
The liquid crystal display device 10 employs, for example, an in-plane switching (IPS) method and an active matrix drive method. The liquid crystal panel 20 includes a color filter substrate and a TFT substrate that are arranged so as to oppose each other with a gap provided therebetween. Liquid crystal is filled into the gap provided therebetween. Polarizing films are bonded to outer side surfaces of respective glass substrates that form the color filter substrate and the TFT substrate. The TFT substrate is located on the back surface side of the liquid crystal panel 20, and the backlight unit is arranged behind it. On the other hand, the color filter substrate is located on the display surface side of the liquid crystal panel 20.
On a surface of the TFT substrate on the liquid crystal side, TFTs, pixel electrodes, a common electrode, wiring therefor, and the like are formed. Specifically, the pixel electrodes and the TFTs are arranged in matrix so as to correspond to a pixel arrangement. In each of the pixels, the common electrode made of a transparent electrode material as well as the pixel electrode is arranged. As the wiring, a plurality of source lines 30, a plurality of gate lines 32, and common electrode wiring are formed. The plurality of source lines 30 and the plurality of gate lines 32 are arranged so as to be substantially orthogonal to each other. Each of the gate lines 32 is provided for each row (line in the horizontal direction) of the TFTs, and is connected in common to gate electrodes of the plurality of TFTs in the corresponding row. Each of the source lines 30 is provided for each column (line in the vertical direction) of the TFTs, and is connected in common to sources of the plurality of TFTs in the corresponding column. Further, to a drain of each TFT, the pixel electrode corresponding to the TFT is connected.
Conductive states of each TFTs in a row are controlled as a whole based on a scanning pulse applied to the gate line 32. The pixel electrode is connected to the source line 30 via the TFT in the on state, and a signal voltage (pixel voltage) corresponding to a pixel value is applied to the pixel electrode from the source line 30. A predetermined common potential is applied to the common electrode via the common electrode wiring. The liquid crystal has its orientation controlled for each pixel by an electric field generated based on the potential difference between the pixel electrode and the common electrode. Thus, the transmittance of light entering from the backlight unit is changed, to thereby form an image on the display surface.
The liquid crystal display device 10 employs a divisional-drive method involving horizontally dividing the screen into two regions, upper and lower display regions. In this case, the total number of pixel rows forming the screen is 2n (n is a natural number), and the screen is equally divided into two regions, upper and lower regions, so that a display region AU corresponding to the upper half of the screen and a display region AD corresponding to the lower half of the screen are vertically scanned in parallel.
In order to perform the divisional drive, each of the source lines 30 is divided at a boundary between the regions AU and AD into a source line 30u arranged in the region AU and a source line 30d arranged in the region AD. The video line drive circuit 24u is connected to the source lines 30u, and the video line drive circuit 24d is connected to the source lines 30d. The first to n-th gate lines 32 from the top of the screen are arranged in the display region AU, and those gate lines 32 are connected to the scanning line drive circuit 22u. Further, the (n+1)th to 2n-th gate lines 32 arranged in the display region AD are connected to the scanning line drive circuit 22d.
A video signal received by a tuner or an antenna (not shown) or a video signal generated by another device such as a video reproduction device is input to the control device 26. The control device 26 includes a central processing unit (CPU) and a memory such as a read only memory (ROM) and a random access memory (RAM).
The control device 26 performs various image signal processing such as color adjustment with respect to the input video signal, and generates pixel data representing a grayscale value of each pixel. For example, the control device 26 holds, in the RAM, pixel data for one frame obtained from line-sequentially input video signals, and reads the pixel data in a desired order for each row, to thereby output the pixel data to the video line drive circuits 24u and 24d. Further, the control device 26 generates, based on the input video signals, timing signals for the scanning line drive circuits 22u and 22d, the video line drive circuits 24u and 24d, and the backlight drive circuit to synchronize with each other, and outputs the timing signals toward the respective drive circuits.
Each of the scanning line drive circuits 22u and 22d sequentially selects the gate line 32 based on the timing signal input from the control device 26, and starts an operation of outputting the scanning pulse to the selected gate line 32. In this embodiment, the scanning line drive circuit 22u sequentially selects the gate lines 32 from the first row to the n-th row, and in parallel thereto, the scanning line drive circuit 22d sequentially selects the gate lines 32 from the (n+1)th row to the 2n-th row.
The pixel data of the selected row is input to the video line drive circuits 24u and 24d from the control device 26 in synchronization with the selection of the gate line 32 by each of the scanning line drive circuits 22u and 22d, respectively, and the video line drive circuits 24u and 24d generates a voltage corresponding to the pixel data of the selected row. Then, this voltage is output as a pixel voltage to the source lines 30u and 30d. With this, in each of the display regions AU and AD, the pixel voltage is applied to the pixel electrode corresponding to the selected gate line 32. By the way, this operation corresponds to horizontal scanning of raster graphics, in which a row is selected in each of display regions AU and AD for each horizontal scanning cycle during the effective scanning period, and a pixel voltage is written to pixels in the corresponding row. For example, a vertical scanning cycle (1V), an effective scanning period TEFF, and a blanking period TBLK in the liquid crystal display device 10 are set to be equivalent to an effective display period and a blanking period of vertical scanning of the video signal. Further, a horizontal scanning cycle (1 H) can be set based on a horizontal synchronizing signal of the video signal.
Each of the video line drive circuits 24u and 24d outputs a pixel voltage corresponding to the selected row to the source line 30 basically for each period of 1 H during the effective scanning period TEFF. In the writing operation for each row, the potential of the pixel electrode at the time when the TFT is turned off is basically held until the writing to a pixel in the selected row is started in the next frame. During this period, each pixel in the selected row is controlled to have a transmittance corresponding to the potential. Note that, in this embodiment, the polarity of the pixel voltage is inverted for each frame due to the frame inversion drive. During the blanking period TBLK, the video line drive circuits 24u and 24d basically output a predetermined reference voltage VBLK to each of the source lines 30. In this case, deterioration of the image quality occurs when an unnecessary DC potential is applied to the pixel electrode due to a leak current of the TFT or the like. In order to prevent this, it is preferred to basically set the reference voltage VBLK to a potential corresponding to a pixel value representing black.
Now, description is given of an operation of writing the pixel voltage to a pixel in a head row during each effective scanning period TEFF, which is a feature of this application. As described above, this application has an object of eliminating the insufficient writing to pixels in the head row in a case where vertical scanning of a display region set through horizontal division is started from a pixel row that is adjacent to another display region. Now, a display region whose vertical scanning is started from a pixel row that is adjacent to another display region is referred to as “specific display region”. In this embodiment, the lower display region AD is the specific display region.
In this embodiment, the video line drive circuit sets, in at least the specific scanning display region out of the plurality of display regions, an application start timing of the pixel voltage based on a timing of a scanning pulse for each selected row to be earlier in a selected row at the head of the effective scanning period TEFF (head row) than in a selected row subsequent thereto (non-head row).
The scanning line drive circuit 22d starts an operation of a shift register based on the trigger signal from the control device 26. The output of each stage of the shift register is sequentially connected to the gate lines 32 in the (n+1) th to 2n-th rows, and the scanning pulse is sequentially output to the gate lines 32 from the head stage in synchronization with the clock signal CPV. For example, the shift register causes the scanning pulse to rise for a certain row in synchronization with the rising of the clock signal CPV, and causes the scanning pulse to fall in synchronization with the rising of the clock signal CPV 1 H later.
As described above, a phase difference between a period in which the video line drive circuit 24d outputs the signal voltage Vn+k corresponding to the pixel value Dn+k to the source line 30 and a period in which the scanning line drive circuit 22d applies the scanning pulse Pk to the gate line 32 is set so as to achieve a preferred efficiency of writing the signal voltage Vn+k to the pixel electrode. When the period corresponding to the phase difference is represented by τ, in this embodiment, application of the signal voltage Vn+α to the (n+α)th row (2≦α≦n) that is a non-head row is started from a time point tα which is after the rising timing of the scanning pulse Pα by period τ.
In contrast, application of the signal voltage Vn+1 to the head row is started from a time point t0 that is prior to a time point t1 that is after the rising of the scanning pulse P1 by τ. The time point t0 is preferred to be set before the rising timing of the scanning pulse P1. With this, simultaneously with the turning-on of the TFT in the head row, the signal voltage Vn+1 is applied to the pixel electrode, and the potential VP rapidly rises. Therefore, the insufficiency in writing of the pixel voltage to a pixel as compared to other rows is eliminated or reduced. In this manner, it is possible to prevent deterioration of the image quality, which is caused because a row other than that at the end of the screen is unnecessarily displayed dark.
Starting the application of the signal voltage Vn+1 earlier substantially corresponds to applying a voltage different from the reference voltage VBLK to the source line 30 at an end part of the vertical blanking period TBLK. In this case, considering that, as described above, it is preferred to basically set the potential of the source line 30 in the vertical blanking period TBLK to the reference voltage VBLK corresponding to black, the time point t0 should not be set earlier excessively, and the time point t0 can be basically set to match with the rising timing of the scanning pulse P1. In an actual case, considering a time constant of the signal VSD or the like during transition from the reference potential VBLK to the signal voltage Vn+1, the time point t0 is set prior to the rising timing of the scanning pulse P1, and can be set to a time point prior to the time point t1 by a period of 1 H, for example.
Note that, also in the upper display region AU in which the head row of the vertical scanning is located at the screen end, similarly to the lower display region AD described above, a configuration and an operation for compensating for the insufficient writing of the pixel voltage to a pixel in the head row may be adopted, to thereby prevent the row at the screen end from being displayed dark.
A schematic configuration of a liquid crystal display device according to a second embodiment of this application is basically the same as that in the liquid crystal display device 10 of the above-mentioned embodiment illustrated in
In this embodiment, the video line drive circuit applies, in at least the specific scanning display region out of the plurality of display regions, instead of the reference voltage VBLK, a preset voltage corresponding to the pixel value of an intermediate grayscale during a transition period having a predetermined length at the end of the blanking period TBLK prior to the start of application of the signal voltage during the effective scanning period TEFF.
In this embodiment, application of the signal voltage Vn+k for each row including the head row, that is, the (n+k)th row (1≦k≦n) is started from a time point tk which is after the rising timing of the scanning pulse Pk by the period τ.
The transition period is provided prior to the time point t1, which is the time to start application of the signal voltage Vn+1 for the head row. The time point t0 at which the transition period starts is preferred to be set before the rising timing of the scanning pulse P1, and is set to a time point prior to the time point t1 by a period of 1 H, for example. At the time point t0 during the blanking period TBLK, the control device 26 outputs predetermined pixel data of an intermediate grayscale to the video line drive circuit 24d, and the video line drive circuit 24d applies a voltage VMID corresponding to the pixel data to the source line 30 during a period from the time point t0 to the time point t1. The pixel data of the intermediate grayscale can be set to be a half of the grayscale levels of the pixel data, for example. Further, an average value from a standard image can be obtained in advance by an experiment or the like, and this value can be set as pixel data of the intermediate grayscale.
In this configuration, the voltage VMID, which is expected to be closer to the signal voltage Vn+1 than the reference potential VBLK is, is applied to the pixel electrode at the rising of the scanning pulse P1. With this, the rising of the potential VP in the head row is assisted, and hence the insufficiency in writing of the signal voltage to the pixel electrode as compared to other rows is eliminated or reduced. In this manner, it is possible to prevent a deterioration of the image quality, which is caused because a row other than that at the end of the screen is unnecessarily displayed dark. Further, the pixel data of the intermediate grayscale during the transition period is fixed in each frame, and thus the circuit configuration can be simplified.
A schematic configuration of a liquid crystal display device according to a third embodiment of this application is basically the same as that in the liquid crystal display device 10 of the above-mentioned embodiment illustrated in
In this embodiment, the scanning line drive circuit controls, in at least the specific scanning display region out of the plurality of display regions, the voltage of the scanning pulse for selecting each row (selection voltage) so that a TFT (switching element) in the selected row at the head of the effective scanning period TEFF enters a conductive state with a resistance lower than that of the selected row subsequent thereto.
In this embodiment, a TFT has an n-channel, and is turned on when a gate voltage is higher than an on-voltage. The scanning line drive circuit 22d sets the voltage of the scanning pulse P1 for the (n+1)th row that is the head row to be higher than the voltage of the scanning pulse Pα for the (n+α)th row (2≦α≦n) that is a non-head row. With this, the TFT in the head row is set to have a conductance higher than that of the TFT in the non-head rows, and thus a state with a lower resistance is achieved.
In this configuration, the rising of the potential VP of the pixel electrode after the start of application of the signal voltage Vn+1 in the head row is faster than in other rows, and hence the insufficiency in writing of the signal voltage to the pixel electrode as compared to other rows is eliminated or reduced. In this manner, it is possible to prevent a deterioration of the image quality, which is caused because a row other than that at the end of the screen is unnecessarily displayed dark.
For example, the scanning line drive circuit 22d is configured that a stage of the shift register corresponding to the (n+1)th row outputs a pulse with a voltage higher than those in other stages thereof.
A schematic configuration of a liquid crystal display device according to a fourth embodiment of this application is basically the same as that in the liquid crystal display device 10 of the above-mentioned embodiment illustrated in
In this embodiment, the video line drive circuit sets, for at least the specific scanning display region out of the plurality of display regions, during at least a part of a period for applying the signal voltage corresponding to the pixel value in the selected row at the head of the effective scanning period TEFF, the signal voltage to be larger than a signal voltage that is applied to other selected rows for the same pixel value.
Application of the signal voltage Vn+1 for the head row is started at the time point t1, and is maintained for a period of 1 H. Time point t1 occurs when the period τ has elapsed since the rising of the scanning pulse P1. During a part of the period of 1 H, the signal voltage Vn+1 to be applied to the source line 30 is controlled to be higher than that in the remaining period of the period of 1 H. With this, in the head row, the rising of the potential VP of the pixel electrode during a period after the time point t1 in the period for applying the scanning pulse is promoted. Thus, the insufficiency in writing of the pixel voltage to a pixel, which is due to an application of the reference potential VBLK before the time point t1, is eliminated or reduced. In this manner, it is possible to prevent deterioration of the image quality, which is caused because a row other than that at the end of the screen is unnecessarily displayed dark.
The period in which the signal voltage Vn+1 is increased is set within a period in which the TFT in the head row is turned on, and can be set to the head of the period of 1 H in which the signal voltage Vn+1 is applied, that is, a predetermined period T+ starting from the time point t1 on, for example.
This operation can be achieved by, for example, configuring the control device 26 so as to output a value obtained by increasing the original pixel value by a certain rate as the pixel data to the video line drive circuit 24d during the period T+ and to output the original pixel value as the pixel data during the remaining period. Further, the video line drive circuit 24d may be configured to cause an overshoot on the signal voltage waveform to be applied to the source line 30 only in the head row.
Further, the control device 26 may increase the signal voltage by a certain rate through the entire period for applying the signal voltage for the head row.
In the above-mentioned respective embodiments, the specific display region is the lower display region AD, and the upper display region AU is not the specific display region. However, conversely, even in a configuration in which AU is set to be the specific display region, and AD is not set to be the specific display region (that is, a configuration in which AU performs vertical scanning from the n-th row toward the first row, and AD performs vertical scanning from the 2n-th row toward the (n+1)th row), or in a configuration in which both of AU and AD are set to be the specific display regions (that is, a configuration in which AU performs vertical scanning from the n-th row toward the first row, and AD performs vertical scanning from the (n+1) th row toward the 2n-th row), one can have a configuration and an operation for compensating for the insufficient writing of the pixel voltage to a pixel in the head row.
Further, in the above-mentioned respective embodiments, the screen includes an even number of pixel rows, and the screen is equally divided into two regions, upper and lower regions, to set the display regions AU and AD. However, the screen may include an odd number of pixel rows, and the numbers of pixel rows forming the respective upper and lower display regions may differ from each other. For example, in the screen including an odd number of pixel rows, the number of pixel rows of one of the display regions AU and AD can be set larger by one than that of the other display region.
Further, this application is also applicable to a horizontal divisional drive involving providing three or more display regions.
While the foregoing has described what are considered to be the best mode and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that they may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all modifications and variations that fall within the true scope of the present teachings.
Number | Date | Country | Kind |
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2012-031220 | Feb 2012 | JP | national |
This application is Bypass Continuation of international patent application PCT/JP2013/000501, filed: Jan. 30, 2013 designating the United States of America, the entire disclosure of which is incorporated herein by reference. Priority is claimed based on Japanese patent application JP2012-031220, filed: Feb. 16, 2012. The entire disclosure of Japanese patent application JP2012-031220 is incorporated herein by reference in its entirety.
Number | Date | Country | |
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Parent | PCT/JP2013/000501 | Jan 2013 | US |
Child | 14449922 | US |