LIQUID CRYSTAL DISPLAY DEVICE

Abstract

A liquid crystal display device with multiple pixels provided therein is disclosed comprising: a first sub-pixel provided for each of said pixels and including, a first liquid crystal capacitance formed with a liquid crystal sandwiched between a common electrode and a first pixel electrode, and a first auxiliary capacitance formed with a solid dielectric material sandwiched between said first pixel electrode and a first auxiliary capacitance electrode; a second sub-pixel disposed adjacent to said first sub-pixel for each of said pixels and including, a second liquid crystal capacitance formed with a liquid crystal sandwiched between said common electrode and a second pixel electrode, a second auxiliary capacitance formed with a solid dielectric material sandwiched between said second pixel electrode and a second auxiliary capacitance electrode, and a step-down capacitance formed with a solid dielectric material sandwiched between said second pixel electrode and a step-down capacitance electrode; a first voltage application means for applying a common first voltage to said common electrode, said first auxiliary capacitance electrode, and said second auxiliary capacitance electrode; and a second voltage application means for applying a second voltage, which is different from said first voltage, to said step-down capacitance electrode.

Description

This application claims the benefit of Japanese Application No. JP 2008-094421 filed, in Japan on Mar. 31, 2008, which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display device having pixels equipped with first sub-pixels and second sub-pixels whose pixel electrodes are separated from each other.

2. Description of the Related Art

With conventional liquid crystal display devices, a voltage is applied to a liquid crystal through switching devices such as thin film transistors (TFT) and others disposed in pixels.

FIG. 20 is a view schematically showing a pixel 300 of a conventional liquid crystal display device. A pixel electrode (Pix) 301 is charged to a source potential via a transistor 302. A common voltage (Vcom) is applied to a common electrode (COM) 303, and the potential difference between the common electrode 303 and the pixel electrode 301 is applied to the liquid crystal as a voltage (Vlc). In this case, the liquid crystal sandwiched by the common electrode 303 and the pixel electrode 301 forms a liquid crystal capacitance Clc, whereas a solid dielectric material sandwiched by the pixel electrode 301 and an auxiliary capacitance line 305 forms an auxiliary capacitance Ccs.

The auxiliary capacitance Ccs is formed in parallel with the liquid crystal capacitance Clc. At the same time, since the auxiliary capacitance line 305 is connected in a way that allows the same potential as the common electrode 303 to be applied, the potential fluctuation that occur at the pixel electrode 301 due to a gate potential fluctuation or the leak current at off state of the transistor 302 is reduced. To prevent an image burn-in and electrolysis of the liquid crystal, the liquid crystal display device is ac-driven that the polarity of the voltage is applied to the liquid crystal to be switched at specified intervals.

There is a well-known technique, for example, that a pixel of a liquid crystal device is divided into multiple regions and different voltages are applied to each region to decrease the dependence of display status on viewing angles, as disclosed by Japanese Patent Laid Open Applications, JP H7-028091A (1995) and JP H8-015723A (1996).

Specifically, JP H7-028091A discloses a liquid crystal display device that a TFT is connected to any one of the divided pixel electrodes, and effective voltages at various levels are applied to multiple regions within the pixels of the liquid crystal by applying the voltage to the pixel electrode connected to the TFT to other pixel electrodes via a capacitance formed between the relevant pixel electrode.

JP H8-015723A discloses an active matrix liquid crystal display that its common electrode is disposed opposite to a pixel electrode connected to a TFT and is divided into multiple regions. By applying different voltages to each region, effective voltages at various levels are applied to the liquid crystal of a plural region in a pixel.

However, in the liquid crystal display device disclosed by JP H7-028091A, if the capacitances formed between the pixel electrode connected to the TFT and other pixel electrodes vary due to the difference in thickness of dielectric material (insulation film) for example, a problem arises that the viewing-angle dependences varie among plural liquid crystal display devicefrom device.

On the other hand, in the active matrix liquid crystal display disclosed by JP H8-015723A, since electrode patterning on the pixel size level must be performed on both substrates constituting a liquid crystal panel, it increases the number of manufacturing processes. Furthermore, since high laminating accuracy is required in laminating two substrates, thus inducing a problem that the yielding was lowered.

SUMMARY OF THE INVENTION

Accordigly, an object of the present invention is directed to provide a liquid crystal display device whose viewing-angle dependence, which varies from device to device, can be corrected easily without increasing the number of manufacturing processes, and even after liquid crystal panels have been manufactured, thus solving the problems of conventional liquid crystal display devices.

One of the preferable embodiments of the present invention provides a liquid crystal display device with multiple pixels provided therein, comprising: a first sub-pixel provided for each of said pixels and including, a first liquid crystal capacitance formed with a liquid crystal sandwiched between a common electrode and a first pixel electrode, and a first auxiliary capacitance formed with a solid dielectric material sandwiched between said first pixel electrode and a first auxiliary capacitance electrode; a second sub-pixel disposed adjacent to said first sub-pixel for each of said pixels and including, a second liquid crystal capacitance formed with a liquid crystal sandwiched between said common electrode and a second pixel electrode, a second auxiliary capacitance formed with a solid dielectric material sandwiched between said second pixel electrode and a second auxiliary capacitance electrode, and a step-down capacitance formed with a solid dielectric material sandwiched between said second pixel electrode and a step-down capacitance electrode; a first voltage application means for applying a common first voltage to said common electrode, said first auxiliary capacitance electrode, and said second auxiliary capacitance electrode; and a second voltage application means for applying a second voltage, which is different from said first voltage, to said step-down capacitance electrode.

In another aspect, the present invention provides a liquid crystal display device with multiple pixels provided therein, comprising: a first sub-pixel disposed for each of said pixel and including, a first pixel electrode disposed opposite to a common electrode via a liquid crystal layer, and a first auxiliary capacitance electrode disposed opposite to the first pixel electrode via an insulating layer; a second sub-pixel disposed adjacent to said first sub-pixel for each of said pixels and including, a second pixel electrode disposed opposite to said common electrode via a liquid crystal layer, a second auxiliary capacitance electrode disposed opposite to said second pixel electrode, and a step-down capacitance electrode, a first voltage application means for applying a common first voltage to said common electrode, said first auxiliary capacitance electrode, and said second auxiliary capacitance electrode; and a second voltage application means for applying a second voltage, which is different from said first voltage, to said step-down capacitance electrode.

BRIEF DESCRIPTION OF DRAWINGS

In the drawings:

FIG. 1 is a block diagram illustrating a strucure of a liquid crystal display device according to an embodiment of the present invention;

FIG. 2 is a drawing illustrating a cross-sectional area of a liquid crystal display device according to an embodiment of the present invention;

FIG. 3 is a drawing illustrating an equivalent circuit of a pixel;

FIG. 4 is a magnified plan view of a pixel;

FIG. 5A is a cross-sectional view of the pixel in FIG. 4 taken along a line X-X′;

FIG. 5B is a cross-sectional view of the pixel in FIG. 4 taken along a line Y-Y′;

FIG. 6 is a chart illustrating scanning signals and a common voltage;

FIG. 7 is a block diagram illustrating a configuration of a scanning signal line drive circuit;

FIG. 8 is a block diagram illustrating a configuration of a holding circuit;

FIG. 9 is a block diagram illustrating a configuration of a data signal line drive circuit;

FIG. 10 is a block diagram illustrating a configuration of a display signal voltage generation circuit;

FIG. 11 is a drawing illustrating a voltage to be applied to the liquid crystal at a first sub-pixel;

FIG. 12 is a drawing illustrating a voltage to be applied to the liquid crystal at a second sub-pixel;

FIG. 13 is a drawing illustrating the relationship between display signal voltage and transmission intensity in each pixel;

FIG. 14A is a drawing illustrating the relationship between display signal voltage and transmission intensity in each pixel, with the step-down voltage oscillated in a way that allows the potential difference from the common voltage to be decreased;

FIG. 14B is a drawing illustrating the relationship between display signal voltage and transmission intensity in each pixel, with the step-down voltage oscillated in a way that allows the potential difference from the common voltage to be increased;

FIG. 15A is a drawing illustrating the relationship between common voltage and step-down voltage, with the step-down voltage oscillated in a way that allows the potential difference from the common voltage to be decreased;

FIG. 15B is a drawing illustrating the relationship between the common voltage and step-down voltage, with the step-down voltage oscillated in a way that allows the potential difference from the common voltage to be increased;

FIG. 16 is a partially magnified plan view illustrating a first example of the layout of first and second sub-pixels in a pixel;

FIG. 17 is a partially magnified plan view illustrating a second example of the layout of first and second sub-pixels in a pixel;

FIG. 18 is a partially magnified plan view illustrating a part of a third example of the layout of first and second sub-pixels in a pixel;

FIG. 19 is a partially magnified plan vie illustrating a part of a fourth example of the layout of first and second sub-pixels in a pixel; and

FIG. 20 is a drawing schematically illustrating a strucure of a pixel of a conventional liquid crystal display device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, various embodiments of the present invention will be described in detail with reference to the figures in which like reference characters are used to designate like or corresponding components.

As shown in FIG. 1, a liquid crystal display device 1 according to the present invention comprises, for example, an image memory 10 for temporarily storing image data input from outside, a display panel 11 for displaying an image based on the image data stored in the image memory 10, a scanning signal line drive circuit 12 for scanning signal lines of the display panel 11, a data signal line drive circuit 13 for providing a display signal voltage to the data signal lines of the display panel 11 based on an image data, a common voltage generation circuit 14 for applying a specified voltage to a common electrode and auxiliary capacitance lines of the display panel 11, a step-down voltage generation circuit 15 for applying voltage for decreasing pixel voltage to step-down capacitance lines of the display panel 11, an inherent information storage unit 16 in which a value of the voltage to be applied by the step-down voltage generation circuit 15 has been stored, and a control unit 17 that outputs various control signals to synchronize each drive unit, whose operation will be described in detail later.

As shown in FIG. 2, the display panel 11 is comprised of a pair of substrates 112 and 113 which are disposed opposite to each other and adhered with a sealing agent 111, and a liquid crystal LC is sanwitched between the substrates 112 and 113. One of the substrates 112 comprises multiple scanning signal lines extending in the horizontal direction (“n” scanning signal lines, for example), multiple auxiliary capacitance lines also extending in the horizontal direction (“n×2” auxiliary capacitance lines, for example), step-down capacitance lines also extending in the horizontal direction (“n” step-down capacitance lines, for example), and multiple data signal lines extending in the vertical direction (“m” data signal lines, for example) and a pixel P (i, j) as shown in FIGS. 3 and 4 is disposed on the substrate 112 adjacent at each intersections of a scanning signal line G (j) and a data signal line S (i) (i=1, 2, 3, . . . m, and j=1, 2, 3, . . . n). A common electrode 115 having a common electric potential at each pixel P (i, j) is disposed on the substrate 112 that faces substrate 112. For example, a transparent electrode is disposed on a surface of the substrate 113 opposing to substrate 112 to cover the entire surface.

At each pixel P (i, j), a first sub-pixel P1 (i, j) and a second sub-pixel P2 (i, j) are disposed.

At the first sub-pixel P1 (i, j), a first pixel electrode E1 (i, j) and a TFT1 (i, j) as a first switching device, etc. are disposed. The first pixel electrode E1 (i, j) is connected to a drain electrode of TFT1 (i, j), the data signal line S (i) is connected to a source electrode of TFT1 (i, j), and a scanning signal line G (j) is connected to a gate electrode of TFT1 (i, j). A first liquid crystal capacitance Clc1 (i, j) is formed by the common electrode 115, the first pixel electrode E1 (i, j), and the liquid crystal filled between them. An auxiliary capacitance line C1 (j) is disposed on the lower side of a first pixel electrode E1 (i, j) via a solid dielectric material so that a first auxiliary capacitance Ccs1 (i, j) is formed by the first pixel electrode E1 (i, j), the dielectric material, and the auxiliary capacitance line C1 (j).

Meanwhile, in the second sub-pixel P2 (i, j), a second pixel electrode E2 (i, j) separated from the first pixel electrode E1 (i, j), TFT2 (i, j) as a second switching device etc. are disposed. The second pixel electrode E2 (i, j) is connected to a drain electrode of TFT2 (i, j), the data signal line S (i) is connected to the source electrode of TFT2 (i, j), and the scanning signal line G (j) is connected to a gate electrode of TFT2 (i, j). A second liquid crystal capacitance Clc2 (i, j) is formed by the common electrode 115, the second pixel electrode E2 (i, j), and the liquid crystal filled between them. An auxiliary capacitance line C2 (j) and a step-down capacitance line D (j) are disposed on the lower side of the second pixel electrode E2 (i, j) via a solid dielectric material. A second auxiliary capacitance Ccs2 (i, j) is formed by the second pixel electrode E2 (i, j), the dielectric material, and the auxiliary capacitance line C2 (j). Also, a step-down capacitance Cd (i, j) is formed by the second pixel electrode E2 (i, j), the dielectric material, and the step-down capacitance line D (j).

Each pixel P (i, j) is configured to allow display status to be controlled by changing the orientation of the liquid crystal disposed between the pixel electrode and the common electrode 115 of each sub-pixel, P1 (i, j) and P2 (i, j), based on the potential difference between the pixel electrode and the common electrode 115.

The common electrode 115 and the auxiliary capacitance lines C1 (j) and C2 (j) are electrically connected outside the display area 114, which allows an appliyning a common voltage Vc. A step-down voltage Vd, which is different from the common voltage Vc, is applied to the step-down capacitance lines D (j).

Hereinafter, specific configuration of the cross-sectional area of each pixel P (i, j) will be described by referring to FIGS. 5A and 5B. The scanning signal line G (j) including a gate electrode 51 is disposed on one of the substrates 112. The auxiliary capacitance lines C1 (j) and C2 (j) and step-down capacitance line D (j) are disposed on the same layer as the scanning signal line G (j). In other words, the scanning signal line G (j), auxiliary capacitance lines C1 (j) and C2 (j), and step-down capacitance line D (j) are formed at a same time. A gate insulating film 52 is disposed on the whole surfaces of these lines. An intrinsic amorphous silicon semiconducting thin film 53 is disposed on the gate insulating film 52. A channel protective film 54 is disposed on the upper surface of approximatory center of semiconducting thin film 53. An n-type amorphous silicon contact layers 55 and 56 are disposed on both sides of the channel protective film 54 and the semiconducting film 53 covering the upper face of the channel protective film 54 on both sides.

A drain electrode 57 is disposed on an upper face of one of the contact layers 55. The data signal line S (i) including a source electrode 58 is disposed on an upper face of the other contact layer 56 and an upper face of the gate insulating film 52.

Thus, the TFT1 (i, j) is included by the gate electrode 51, the gate insulating film 52, the semiconducting thin film 53, the channel protective film 54, the contact layers 55 and 56, the drain electrode 57, and the source electrode 58. TFT2 (i, j) is configured as same as the TFT1 (i, j).

A planarizing film 59 made of an insulating material is disposed over the entire surface of the gate insulating film 52 including TFT1 (i, j), TFT2 (i, j), etc. A contact hole 60 is formed in the specified portion of the planarizing film 59 corresponding to the drain electrode 57. The pixel electrodes E1 (i, j) and E2 (i, j) both of which are consisting of ITO are disposed on the specified portions of the planarizing film 59. The pixel electrodes E1 (i, j) and E2 (i, j) are connected to the drain electrodes 57 of the relevant TFT via the contact hole 60.

A portion of the auxiliary capacitance line C1 (j) that overlaps with the first pixel electrode E1 (i, j) serves as an auxiliary capacitance electrode. This overlapping portion forms the first auxiliary capacitance Ccs1 (i, j) as described previously. Meanwhile, a portion of the auxiliary capacitance line C2 (j) that overlaps with the second pixel electrode E2 (i, j) serves as an auxiliary capacitance electrode. As described previously, this overlapping area forms the second auxiliary capacitance Ccs2 (i, j). Furthermore, a portion of the step-down capacitance line D (j) that overlaps with the second pixel electrode E2 (i, j) serves as a step-down capacitance electrode. This overlapping portion forms a step-down capacitance Cd (i, j) as described previously. Each pixel P (i, j) is configured to ensure that a size of the first auxiliary capacitance Ccs1 (i, j) is eual to that of the second auxiliary capacitance Ccs2 (i, j).

As shown in FIG. 6, the scanning signal line drive circuit 12 outputs scanning signals to each scanning signal line G (j) according to vertical synchronizing signal Vs output from a control unit 17 and horizontal synchronizing signal Hs based on a first gate clock signals GCK1 and a second gate clock signals GCK2. The first gate clock signals GCK1 and the second gate clock signals GCK2 are rectangular signals having an opposite phase to each other.

As shown in FIG. 7, the main part of the scanning signal line drive circuit 12 is roughly configured with holding circuits 121, 122, 123, 124, . . . connected in series of the number equivalent to the number of the scanning signal lines (“n” stages). Each holding circuit 121, etc. comprise: an input terminal IN, an output terminal OUT, a reset terminal RST, a clock signal input terminal CK, a high potential power input terminal Th, and a low potential power input terminal Tl. The vertical synchronizing signal Vs is supplied to the input terminal IN of the holding circuit 121 as the first stage input signal. The output signals from the holding circuit in the previous stage are supplied to the input terminal IN of the holding circuit in the second and subsequent stages. The output signals from the holding circuit in the next stage are supplied to the reset terminal RST of each holding circuit. Here, separate reset signals END or the output signals from the holding circuit 121 in the first stage may be supplied to the reset terminal RST of the holding circuit in the final stage (not shown, “y”th stage, for example).

Furthermore, the first gate clock signal GCK1 is supplied to clock signal input terminals CK of the holding circuit in the odd-numbered stages. The second gate clock signal GCK2 having opposite phase to the first gate clock signal GCK1 is supplied to the clock signal input terminals CK of the holding circuit in the even-numbered stages. A predetermined high voltage Vgh is supplied to the high-potential power input terminal Th of each holding circuits, whereas a predetermined low voltage Vgl is supplied to the low-potential power input terminal Tl of each holding circuits.

As shown in FIG. 8, each holding circuit 121, 122, 123, 124, . . . is provided with six MOS type Field Effect Transistors (hereinafter referred to as MOS transistors) T11 to T16 and a capacitance C.

As shown in FIG. 6, such scanning signal line drive circuit 12 starts scanning in the relevant frame in response to the vertical synchronizing signal Vs, and performs voltage output, which is based on the first gate clock signals GCK1 and the second gate clock signals GCK2, from a low-level voltage Vgl to a high-level voltage Vgh for a specified period of time starting from the scanning signal line in each of the first stage G (1) up to final stage G (n).

Specifically, the scanning signal line drive circuit 12 sequentially sets TFT1 (i, j) and TFT2 (i, j) corresponding to the relevant scanning signal line G (j) to ON, and writes the display signal voltage that is output to the data signal line S (i) at that time to the first sub-pixel P1 (i, j) and the second sub-pixel P2 (i, j).

The data signal line drive circuit 13 outputs display signal voltage corresponding to each data signal line S (i) disposed on the display panel 11 at predetermined timing according to the horizontal synchronizing signal Hs, the vertical synchronizing signal Vs, the image data Data, a reference clock signal CLK, and a polarity reversal signal Pol among of which output from the control unit 17.

As shown in FIG. 9, the functional block of the data signal line drive circuit 13 comprises sampling memories 131, data latch units 132, D/A conversion circuits (DAC) 133, and a display signal voltage generation circuit 134.

The sampling memories 131 have data storage areas as many as the number of data signal lines S (i). In synchronization with the horizontal synchronizing signal Hs output from the control unit 17 and the reference clock signal CLK, the sampling memory 131 fetches image data corresponding to each pixel from the image memory 10 sequentially, starting from the data corresponding to the scanning signal line in the previous stage, in units of image data corresponding to the pixel for one scanning signal line (image data for one horizontal period). Specifically, each sampling memory 131 fetches image data corresponding to the relevant scanning signal line, and stores each of the image data fetched in the data storage area corresponding to the relevant scanning signal line S (i). In this case, the image data includes gradation levels to be displayed in each pixel. This gradation levels are displayed by each pixel as 8-bit digital data, for example. This 8-bit digital data is stored in each data storage area.

The image data of one horizontal period fetched by the sampling memory 131 is transferred from the sampling memory 131 to the data latch unit 132 in response to a request from the data latch unit 132 in the subsequent stage. After a completion of transfering the image data to the data latch unit 132, the sampling memory 131 starts to fetch the image data corresponding to the scanning signal line of the next row for the next horizontal period. This is perfoprmed in synchronization with horizontal synchronizing signal Hs.

The data latch units 132 obtain image data for one horizontal period collectively from the sampling memories 131 according to horizontal synchronizing signal Hs, and output the obtained image data to the D/A conversion circuits 133 in the subsequent stage.

The D/A conversion circuit 133 comprises multiple DAC units 241 and output amplification circuits 242. The display signal voltage supplied from the display signal voltage generation circuit 134 is selected by the DAC units 241, which allows each image data output from the data latch units 132 to be converted into display signal voltages as corresponding analog signals, and then output to the data signal lines S (i) via the output amplification circuits 242.

At this time, the D/A conversion circuits 133 convert digital image data output from the data latch units 132 into an analog display signal voltage, in response to the polarity reversal signals Pol output from the control unit 17. Specifically, when the polarity reversal signal Pol is in high state Vsh, the D/A conversion circuits 133 perform D/A conversion to allow the image data output from the data latch units 132 to become display signal voltage having positive polarity. On the contrary, when the polarity reversal signal Pol is in low state Vsl, the D/A conversion circuits 133 perform D/A conversion to allow the image data output from the data latch units 132 to become display signal voltage having negative polarity. In other words, the D/A conversion circuits 133 perform D/A conversion to allow the voltage applied to the liquid crystal to have positive polarity when the polarity reversal signal Pol is in high state Vsh, and allow the voltage applied to the liquid crystal to have negative polarity when the polarity reversal signal Pol is in low state Vsl.

As shown in FIG. 10, the display signal voltage generation circuit 134 comprises: a pair of ladder resistors 31 and 32, multiple switches SY0, SY1, . . . , SY255, and switches SYa and SYb etc.. Each pair of ladder resistors 31 and 32 divides the voltage between terminal 255 (voltage VH) and terminal 256 (voltage VL) using multiple resistors suitable for the bit count p of the image data (8 bits in the embodiment of the present invention). The multiple switches SY0, SY1, . . . , SY255 serves for selecting a desired ladder resistor of the pair. The switches SYa and SYb serve for switching the polarity of the voltage to be applied to the ladder resistors in response to the ladder resistor selected. The display signal voltage generation circuit 134 selects desired ladder resistors by the operation of each switch SY0, SY1, . . . , SY255 based on the polarity reversal signal Pol output from the control unit 17. At the same time, the display signal voltage generation circuit 134 switches the polarity of the voltage to be applied to the ladder resistors by the operation of the switches SYa and SYb, and applies each voltage divided by the ladder resistors to the voltage application lines V0, V1, . . . , V255 as display signal voltage at a corresponding gradation level.

Specifically, when the polarity reversal signal Pol from the control unit 17 is at high level Vsh, the ladder resistor 31 is selected by the operation of each switch SY0, SY1, . . . , SY255. In addition, when the terminal 255a (voltage VH) and the terminal 256b (voltage VL) are selected by the operation of the switches SYa and SYb, the voltage between the terminals 255a (voltage VH) and 256b (voltage VL) is divided by multiple resistors RA1, RA2, . . . , RA254 suitable for the bit count of the image data (8 bits in the embodiment of the present invention). Each voltage is applied to the voltage application lines V0, V1, . . . , V255 as display signal voltage that allows a voltage having positive polarity to be applied to the liquid crystal, for example.

When the polarity reversal signal Pol from the control unit 17 is at low level Vsl, the ladder resistor 32 is selected by the operation of each switch SY0, SY1, . . . , SY255. In addition, when the terminals 256a (voltage VL) and 255b (voltage VH) are selected by the operation of the switches SYa and SYb, the voltage between the terminals 256a (voltage VL) and the terminal 255b (voltage VH) is divided by multiple resistors RB1, RB2, . . . , RB254 suitable for the bit count of the image data (8 bits in the embodiment of the present invention), and each voltage is applied to voltage application lines V0, V1, . . . , V255 as display signal voltage that allows a voltage having negative polarity to be applied to the liquid crystal, for example.

Each DAC unit 241 comprises: a decoder 243 and, selector switches SW0, SW1, . . . , SW255 which are connected to voltage application lines V0, V1, . . . , V255. In the decoder 243, input the image data output from the data latch units 132 are decoded and output data signals that satisfy the number of gradation levels (i.e. bit count). Each selector switch SW0, SW1, . . . , SW255 is set to ON/OFF according to the data signals output from the decoder 243. The selected voltage application lines V0, V1, . . . , V255 and a voltage output line SL are connected, and the display signal voltage which is applied to the selected voltage application lines V0, V1, . . . , V255 is supplied to the voltage output line SL. The display signal voltage applied to the voltage output line SL is then supplied to the data signal lines S (i) via the output amplification circuit 242.

The common voltage generation circuit 14 applies identical common voltage Vc to the common electrode 115 and each auxiliary capacitance line C1 (j) and C2 (j) according to the polarity reversal signal Pol output from the control unit 17. When the polarity reversal signal Pol is at a high level Vsh, the first common voltage Vcl is applied so as to allow a voltage having positive polarity to be applied to the liquid crystal. When the polarity reversal signal Pol is at a low level Vsl, the second common voltage Vch is applied so as to allow a voltage having negative polarity to be applied to the liquid crystal. In other words, the common voltage generation circuit 14 applies rectangular AC voltage to the common electrode 115 and each auxiliary capacitance line C1 (j) and C2 (j).

The control unit 17 outputs the polarity reversal signal Pol to allow the voltage to be applied to the liquid crystal to have opposite polarities between adjacent pixels (pixels adjacent to each other in the pixel row direction), and furthermore to allow the voltage to be applied to the liquid crystal to have opposite polarities by each frame.

Thus, the voltage Vlc1 as shown in FIG. 11 is applied to the liquid crystal in the first sub-pixel P1 (i, j) of each pixel P (i, j) over an approximately entire period in one flame. In FIG. 11, ΔV shows a pull-in voltage that is generated when write of display signal voltage into a pixel is completed due to the effect of parasitic capacitance between scanning signal lines and pixel electrodes. It is desirable that a center of amplitude of the common voltage Vc is set to a value shifting the center of amplitude of the display signal voltage by ΔV in the direction of generation of ΔV.

The step-down voltage generation circuit 15 applies a step-down voltage Vd to the step-down capacitance lines D (j) based on the polarity reversal signal Pol output from the control unit 17 and the inherent information Inf stored in the inherent information storage unit 16. A step-down voltage Vd may be a center voltage of the common voltage Vc, i.e. Vcl+(Vch−Vcl)/2. A step-down voltage Vd may be a center voltage of the common voltage Vc, i.e. Vcl+(Vch−Vcl)/2, and this voltage value changes in synchronization with the polarity reversal signal Pol.

Specifically, the step-down voltage generation circuit 15 applies voltage to the step-down capacitance lines D (j) so that a potential fluctuation at the second pixel electrode E2 (i, j) is reduced to be smaller than a potential fluctuation at the common electrode 115 by step-down capacitance Cd (i, j) which is formed between the second pixel electrode E2 (i, j) and the step-down capacitance line D (j).

Therefore, this allows that voltage Vlc1 and Vlc2 as shown in FIG. 12 are applied to the liquid crystal at the second sub-pixel P2 (i, j) of each pixel P (i, j), thus ensuring that the mean voltage, i.e. (Vlc1+Vlc2)/2, applied to the liquid crystal during one frame is smaller than the voltage Vlc1 applied to the liquid crystal at the first sub-pixel P1 (i, j).

In other words, during the period T1, in which the potential of the common electrode 115 is equivalent to the potential of the relevant common electrode 115 at the time when display signal voltage is written into the second pixel electrode E2 (i, j) via TFT2 (i, j), the voltage applied to the liquid crystal at the second sub-pixel P2 (i, j) is equal to the voltage Vlc1 applied to the liquid crystal at the first sub-pixel P1 (i, j). Meanwhile, during the period T2, in which the potential of the common electrode 115 is not equivalent to the potential of the relevant common electrode 115 at the time when display signal voltage is written into the second pixel electrode E2 (i, j) via TFT 2 (i, j), the voltage, expressed as Vlc2, applied to the liquid crystal at the second sub-pixel P2 (i, j) is smaller than the voltage Vlc1 applied to the liquid crystal at the first sub-pixel P1 (i, j).

Consequently, as shown in FIG. 13, a curve VT2, which represents a relationship between a display signal voltage and a transmission intensity at the second sub-pixels P2 (i, j) can be shifted to with respect to a curve VT1, which represents a relationship between a display signal voltage and a transmission intensity at the first sub-pixels P1 (i, j). Therefore, multiple relationships between display signal voltage and transmission intensity at each display pixel P (i, j) can be obtaied, and thus the degree of dependence on viewing angles in the liquid crystal display device 1 can be improved.

The difference ΔVlc between voltages Vlc1 and Vlc2 can be found for example by using the following equations (1) to (4)

ΔVlc=(A−B)/R   (1)

A={Clc2(i, j)+Ccs2(i, j)}×Vcl   (2)

B={Clc2(i, j)+Ccs2(i, j)}×Vch   (3)

R=Clc2(i, j)+Ccs2(i, j)+Cd.   (4)

To bring the curve VT2, which represents the relationship between the display signal voltage and transmission intensity at the second sub-pixels P2 (i, j), relatively close to VT1, which represents the relationship between the display signal voltage and transmission intensity at the first sub-pixels P1 (i, j), the step-down voltage Vd as shown in FIG. 14A may be oscillated as shown in FIG. 15A to be in phase with the common voltage Vc output from the common voltage generation circuit 14, thus minimizing the potential difference from the common voltage Vc.

On the contrary, to bring the curve VT2, which represents the relationship between the display signal voltage and transmission intensity at the second sub-pixels P2 (i, j), relatively away from VT1, which represents the relationship between the display signal voltage and transmission intensity at the first sub-pixels P1 (i, j), the step-down voltage Vd as shown in FIG. 15B may be oscillated to be in opposite phase with the common voltage Vc output from the common voltage generation circuit 14, thus maximizing the potential difference from the common voltage Vc.

According to the the present embodiment, since the relationship between the display signal voltage and transmission intensity can be shifted easily by adjusting the step-down voltage Vd applied to the step-down capacitance lines D (j), the viewing-angle dependence of the liquid crystal display can be improved by simple circuit configuration. Furthermore, the degree of viewing-angle dependence of it can be adjusted.

For exaple, after a display panel 11 has been manufactured, differences of viewing-angle dependence among a plural display panel 11 can be minimized by followings configurations. The inherent information storage unit 16 is made to store the value of step-down voltage Vd which can be controlled to the similar extent as the control of viewing-angle dependence of other display panels 11 as the inherent information Inf. And a step-down voltage generation circuit 15 is configured to apply step-down voltage Vd having an amplitude based on the inherent information Inf stored in the relevant inherent information storage unit 16 to the step-down capacitance line D (j).

In addition, since the step-down voltage generation circuit 15 needs to adjust the amplitude of step-down voltage Vd only, a simple step-down voltage generation circuit 15 can be configured. If sub-pixels have different data signal lines, and different display signal voltages are applied to each sub-pixel via corresponding data signal lines and TFTs, for example, multiple display signal voltage generation circuits relatively large in size are required to apply different display signal voltages to each sub-pixel as described above. However, accoding to the embodiment of the present invention, it does not need complex configuration, and the viewing-angle dependence can be adjusted with a simpler circuit configuration compared with configuration mentioned above. Moreover, since the common electrode 115 need not be separated for each region within a display pixel, the number of manufacturing processes does not increase.

In addition, since display signal voltage is applied directly to the pixel electrodes of each sub-pixel via corresponding TFTs in the present embodiment, the voltage is applied to the liquid crystal more stably compared with the one in which voltage is applied to the pixel electrodes only via capacitances.

Meanwhile, an EEPROM (Electrically Erasable Programmable Read Only Memory), which is one of nonvolatile memories, can be used for an inherent information storage unit 16. The EEPROM has the state that no information has been written in it i.e. “white” state at the start of manufacturing of a display device 1. After the completion of manufacturing of liquid crystal display device 1, predetermined informations can be stored in the inherent information storage unit 16 by connecting a system device for writing in an EEPROM to a signal terminal for writing 161 in accordance with the finishing state of the relevant liquid crystal display device 1.

It is preferable to set the writing voltage Vpp into the inherent information storage unit 16 at a level higher than the reference supply voltage Vcc to be input to the power control circuit for the relevant liquid crystal display device 1 so that the information stored in the inherent information storage unit 16 can be prevented to be erased carelessly by the influence of the reference supply voltage Vcc.

The above embodiment explains a case that the shape and the area of the first pixel electrodes E1 (i, j) in the first sub-pixels P1 (i, j) are the same as those of the second pixel electrodes E2 (i, j) of the second sub-pixels P2 (i, j). Hereinafter, a typical modification of the layout of the first sub-pixels P1 (i, j) and the second sub-pixels P2 (i, j) in display pixels P (i, j) will be described.

FIG. 16 is a partially magnified plan view showing the first example of the layout of first and second sub-pixels in pixels P (i, j). As shown in FIG. 16, a shape and an area of a first pixel electrode E1 (i, j) and a second pixel electrode E2 (i, j) may differ. In this case, however, the size and shape of each of the first sub-pixels P1 (i, j) are identical, and the size and shape of each of the second sub-pixels P2 (i, j) are also identical. Consequently, two sub-pixels, the first sub-pixel P1 (i, j) disposed on the side of the previous row of the scanning line G (j), namely on the side of the j−1 row, and the second sub-pixel P2 (i, j) disposed on the side of the following row of the scanning line G (j), namely on the side of the j+1 row, constitute a pixel pattern. This pixel pattern is disposed on all of the intersections between each row and column. The region enclosed in the broken line represents pixels for one row and three columns. The first sub-pixels P1 (i, j) are disposed on the upper side of the scanning line G (j) via the first switching devices TFT1 (i, j). The second sub-pixels P2 (i, j) are disposed on the lower side of the scanning line G (j) via the second switching devices TFT2 (i, j).

In FIG. 16, each of the first sub-pixels P1 (i, j) is disposed adjacent to the second sub-pixels P2 (i, j), which are disposed on the lower side of the scanning line G (j−1) of the pixels P (i, j) in the previous row. Each of the second sub-pixels P2 (i, j) is disposed adjacent to the first sub-pixels P1 (i, j), which are disposed on the upper side of the scanning line G (j+1) of the pixels P (i, j) in the following row, namely on the upper side of the scanning line G (j+1) of the following row.

The auxiliary capacitance line C1 (j) for the first sub-pixel P1 (i, j) is disposed on the upper side of the scanning line G (j) in parallel to the scanning line G (j).

The auxiliary capacitance line C2 (j) for the second sub-pixel P2 (i, j) is disposed on the lower side of the scanning line G (j) in parallel to the scanning line G (j). The step-down capacitance line D (j) of the second sub-pixel P2 (i, j) is disposed on the upper side of the auxiliary capacitance line C2 (j) in parallel to the scanning line G (j).

The above embodiment is a case that the step-down capacitance line D (j) is disposed on the upper side of the auxiliary capacitance line C2 (j) in the second sub-pixels P2 (i, j) closer to the scanning line G (j). Unlike the embodiment in FIG. 16, the auxiliary capacitance line C2 (j) may be disposed on the upper side of the step-down capacitance line D (j) closer to the scanning line G (j).

The above embodiment is a case that the layout of the first sub-pixels P1 (i, j) and the second sub-pixels P2 (i, j) is identical between the pixels adjacent to each other in the direction of the length of the scanning signal lines G (j) and step-down capacitance lines D (j). However, as shown in FIGS. 17 and 18 later, the layout of the first sub-pixels P1 (i, j) and the second sub-pixels P2 (i, j) may be reversed between the pixels adjacent to each other in the direction of the length of the scanning signal lines G (j) and step-down capacitance lines D (j).

FIG. 17 is a partially magnified plan view showing the second example of the layout of first and second sub-pixels in pixels P (i, j). As shown in FIG. 17, a pixel P (i, j) comprises a first sub-pixel P1 (i, j), which has smaller area, and a second sub-pixel P2 (i, j), which has larger area. The layout of the pixels in the same column as the pixel P (i, j), the layout of P (i, j−1) and P (i, j+1) for example, is identical to that of the pixel P (i, j). Meanwhile, the layout of the pixels in the same row as the pixel P (i, j), the layout of P (i−1, j) and P (i+1, j) for example, is reversed from that of the pixel P (i, j). Specifically, in P (i−1, j) and P (i+1, j), the second sub-pixels P2 (i−1, j) are disposed on the upper side of the scanning line G (j) via the second switching device TFT2 (i−1, j). While, the first sub-pixels P1 (i−1, j) are disposed on the lower side of the scanning lien G (j) via the first switching device TFT1 (i−1, j).

The auxiliary capacitance line C1 (j) for the first sub-pixel P1 (i, j) and the auxiliary capacitance line C2 (j) for the second sub-pixels P2 (i−1, j) and P2 (i+1, j), which are disposed on other columns that are adjacent to column j, are formed to be a common line, and this common line is arraneged in parallel to the scanning line G (j).

The auxiliary capacitance line C2 (j) for the second sub-pixel P2 (i, j) and the auxiliary capacitance lines C1 (j) for the first sub-pixels P1 (i−1, j) and P1 (i+1, j) disposed on other columns that are adjacent to column j are formed to be a common line, and this common line is arraneged in parallel to the scanning line G (j).

The step-down capacitance line D (j) for the second sub-pixel P2 (i, j) and the step-down capacitance lines D (j) for the second sub-pixel P2 (i−1, j) and P2 (i+1, j) disposed on other columns that are adjacent to column j are formed to be a common line, and this common line is arraneged in parallel to the scanning line G (j).

FIG. 18 is a partially magnified plan view showing the third example of the layout of first and second sub-pixels in pixels P (i, j). As shown in FIG. 18, the pixel layout is the same as that shown in FIG. 17, except that an area of the first sub-pixels P1 (i, j) and that of the second sub-pixels P2 (i, j) are approximately the same, and that the interconnection wiring of the step-down capacitance line D (j) is different in the second sub-pixel P2 (i, j).

The step-down capacitance line D (j) for the second sub-pixel P2 (i, j) includes the step-down capacitance line D (j+1), which is in the columns at left and right (columns i−1 and i+1) and in the following row as well as the interconnection wiring portion for the following row of the scanning line G (j). In FIG. 18, the interconnection wiring portion is in the shape of a staggered clamp. Consequently, the step-down capacitance line D (j) of the second sub-pixel P2 (i, j) extends along the second sub-pixel P2 (i, j) of the relevant row and the second sub-pixel P2 (i, j+1) of the following row alternately in the shape of polygonal line in the direction of the scanning line 21 and in the shape of waves by column.

The above embodiment is a case that two auxiliary capacitance lines are disposed for each pixel P (i, j). However, as shown in FIG. 19 later, an auxiliary capacitance line can be shared by sub-pixels.

FIG. 19 is a partially magnified plan view showing the fourth example of the layout of first and second sub-pixels in pixels P (i, j). The pixel 15 in FIG. 19 differs from the pixel 15 in FIG. 16 in that the auxiliary capacitance line C1 (j) for the first sub-pixel P1 (i, j) and the auxiliary capacitance line C2 (j−1) for the second sub-pixel P2 (i, j−1) disposed on the side of the scanning line G (j−1) of the previous row are formed to be a common line.

Similarly, the auxiliary capacitance line C2 (j) for the second sub-pixel P2 (i, j) disposed on the subsequent row of the scanning line G (j) and the auxiliary capacitance line C1 (j+1) for the first sub-pixel P1 (i, j+1) disposed on the side of the subsequent row of the scanning line G (j), namely scanning line G (j+1), are formed to be a common interconnetion wiring, and this cmmon common interconnetion wiringg is disposed in parallel to the scanning line G (j).

The electrode and interconnetion wiring structures described above simplifies mask patterns for fabrication of auxiliary capacitance lines C1 and C2, thus reducing cost.

According to the pixel layouts as shown in FIGS. 16, 17, 18, and 19, it is preferable that two regions having different relationships between display signal voltage and transmission intensity can be disposed so as to realize a higher uniformity.

The present invention allows the difference in viewing-angle dependence between liquid crystal panels to be corrected easily without increasing the number of manufacturing processes even after the manufacturing is completed.

Various modifications and variations can be made in the present invention within the scope of the appended claims, not limited to the above embodiments, and it is not without saying that those variations are also included in the scope of the present invention.

Claims

1. A liquid crystal display device with multiple pixels provided therein, comprising: a first sub-pixel provided for each of said pixels and including,a first liquid crystal capacitance formed with a liquid crystal sandwiched between a common electrode and a first pixel electrode, anda first auxiliary capacitance formed with a solid dielectric material sandwiched between said first pixel electrode and a first auxiliary capacitance electrode;a second sub-pixel disposed adjacent to said first sub-pixel for each of said pixels and including,a second liquid crystal capacitance formed with a liquid crystal sandwiched between said common electrode and a second pixel electrode,a second auxiliary capacitance formed with a solid dielectric material sandwiched between said second pixel electrode and a second auxiliary capacitance electrode, anda step-down capacitance formed with a solid dielectric material sandwiched between said second pixel electrode and a step-down capacitance electrode;a first voltage application means for applying a common first voltage to said common electrode, said first auxiliary capacitance electrode, and said second auxiliary capacitance electrode; anda second voltage application means for applying a second voltage, which is different from said first voltage, to said step-down capacitance electrode.

2. The liquid crystal display device as set forth in claim 1, wherein said first voltage is a rectangular AC voltage that oscillates at specified amplitude and said second voltage is a rectangular AC voltage whose amplitude is smaller than that of said rectangular AC voltage.

3. The liquid crystal display device as set forth in claim 2, wherein said rectangular AC voltage as said first voltage is in phase with said rectangular AC voltage as said second voltage.

4. The liquid crystal display device as set forth in claim 2, wherein said rectangular AC voltage as said first voltage is in opposite phase with respect to said rectangular AC voltage as said second voltage.

5. The liquid crystal display device as set forth in claim 1, wherein said first voltage is a rectangular AC voltage having specified frequency, and said second voltage is a DC voltage whose voltage level remains constant.

6. The liquid crystal display device as set forth in claim 5, wherein said second voltage is a DC voltage that is identical to the value at an center of amplitude of said rectangular AC voltage that oscillates at specified amplitude.

7. The liquid crystal display device as set forth in claim 1, wherein said first sub-pixel has a first switching device that is connected to said first pixel electrode, said second sub-pixel has a second switching device that is connected to said second pixel electrode, and said first and said second switching devices are connected to the same data signal lines and scanning signal lines.

8. The liquid crystal display device as set forth in claim 7, wherein said step-down capacitance electrode is disposed on the same layer as said scanning signal lines.

9. The liquid crystal display device as set forth in claim 7, wherein said first pixel electrode and said second pixel electrode are disposed in different directions with respect to said scanning signal lines.

10. The liquid crystal display device as set forth in claim 1, wherein an area of said first pixel electrode is identical to an area of said second pixel electrode.

11. The liquid crystal display device as set forth in claim 1, wherein an area of said first pixel electrode is identical to an area of said second pixel electrode.

12. The liquid crystal display device as set forth in claim 1, wherein said first auxiliary capacitance electrode, said second auxiliary capacitance electrode, and said step-down capacitance electrode are disposed on the same layer.

13. A liquid crystal display device with multiple pixels provided therein, comprising: a first sub-pixel provided for each of said pixel and including,a first pixel electrode disposed opposite to a common electrode via a liquid crystal layer, anda first auxiliary capacitance electrode disposed opposite to the first pixel electrode via an insulating layer;a second sub-pixel disposed adjacent to said first sub-pixel for each of said pixels and including,a second pixel electrode disposed opposite to said common electrode via a liquid crystal layer,a second auxiliary capacitance electrode disposed opposite to said second pixel electrode, and a step-down capacitance electrode,a first voltage application means for applying a common first voltage to said common electrode, said first auxiliary capacitance electrode, and said second auxiliary capacitance electrode; anda second voltage application means for applying a second voltage, which is different from said first voltage, to said step-down capacitance electrode.

14. The liquid crystal display device as set forth in claim 13, wherein said first voltage is a rectangular AC voltage that oscillates at a specified amplitude, and said second voltage is a rectangular AC voltage whose amplitude is smaller than that of said rectangular AC voltage as said first voltage.

15. The liquid crystal display device as set forth in claim 14, wherein said rectangular AC voltage as said first voltage is in phase with said rectangular AC voltage as said second voltage.

16. The liquid crystal display device as set forth in claim 14, wherein said rectangular AC voltage as said first voltage is in opposite phase with said rectangular AC voltage as said second voltage.

17. The liquid crystal display device as set forth in claim 13, wherein said first voltage is a rectangular AC voltage having specified frequency, and said second voltage is a DC voltage whose voltage level remains constant.

18. The liquid crystal display device as set forth in claim 17, wherein said second voltage is a DC voltage that is identical to the value at an center of amplitude of said rectangular AC voltage that oscillates at specified amplitude.

19. The liquid crystal display device as set forth in claim 13, wherein said first sub-pixel has a first switching device connected to said first pixel electrode, said second sub-pixel has a second switching device connected to said second pixel electrode, and said first and said second switching devices are connected to the same data signal lines and scanning signal lines.

20. The liquid crystal display device as set forth in claim 19, wherein said step-down capacitance electrode is formed on the same layer as the scanning signal lines.