This application claims benefit of priority under 35 USC §119 to Japanese Patent Application No. 2003-195992, filed on Jul. 11, 2003, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a liquid crystal display having display elements formed in vicinity of cross points of signal lines and scanning lines on an insulation substrate.
2. Related Art
When a voltage is always applied to in the same direction with respect to liquid crystal, baking of liquid crystal occurs. Ordinarily, polarity reversal drive is performed in a liquid crystal display. In the polarity reversal drive, polarity of the applied voltage is switched at a constant period. There are a dot reversal drive for switching polarity for each pixel, a line reversal drive for switching polarity for each line, a frame reversal drive for switching polarity for each frame and the like.
In the case of performing the polarity reversal drive, voltage polarities of a signal line voltage and an auxiliary capacitor power supply line connected to an auxiliary capacitor have to be periodically changed. Because of this, there is a case of providing a plurality of reference power supplies for setting a voltage of the auxiliary capacitor power supply line (see Japanese Patent Publication Laid-Open No. 255851/2001).
However, when the power supply is on, the reference voltage that the auxiliary capacitor power supply line is connected becomes unstable. As a result, the voltage applied to the liquid crystal layer changes for each auxiliary capacitor power supply line, and there is a problem in which an undesirable bright line in a horizontal direction emerges.
In order to solve the above-described problem, an object of the present invention is to provide a liquid crystal display in which an undesirable bright line in a horizontal direction does not emerge.
A liquid crystal display according to one embodiment of the present invention, comprising:
signal lines and scanning lines arranged in first and second directions on an insulation substrate;
display elements formed in vicinity of cross points of the signal lines and scanning lines;
liquid crystal capacitors and auxiliary capacitors which accumulate electric charge in accordance with voltages of the signal lines via said display elements;
a signal line drive circuit which drives the signal lines;
a scanning line drive circuit which drives the scanning lines;
auxiliary capacitor power supply lines arranged in the first direction, to which one ends of said auxiliary capacitors arranged in the second direction are commonly connected; and
auxiliary capacitor power supply line voltage control circuits which control voltages of said auxiliary capacitor power supply lines in sync with a cycle which drives said liquid crystal capacitors and said auxiliary capacitors by polarity reverse,
wherein said auxiliary capacitor power supply line voltage control circuit supplies a first reference voltage to all of said auxiliary capacitor power supply lines during a predetermine period after power-on.
Furthermore, a liquid crystal display according to one embodiment of the present invention, comprising;
signal lines and scanning lines arranged in first and second directions on an insulation substrate;
pixel switching elements formed in vicinity of cross points of the signal lines and the scanning lines;
a signal line drive circuit which drives the signal lines; and
a scanning line drive circuit which drives the scanning lines,
wherein said scanning line drive circuit drives the scanning lines to turn on all of said pixel switching elements before a predetermined period to shut down power supply; and
said signal line drive circuit applies a predetermined voltage to all the signal lines before a predetermined period to shut down the power supply.
Furthermore, a liquid crystal display according to one embodiment of the present invention, comprising:
signal lines and scanning lines arranged in first and second directions on an insulation substrate;
pixel switching elements formed in vicinity of cross points of the signal lines and the scanning lines;
a signal line drive circuit which drives the signal lines;
a scanning line drive circuit which drives the scanning lines;
liquid crystal capacitors and auxiliary capacitors which are provided corresponding to said pixel switching elements, respectively, and accumulate electric charge in accordance with voltages of the signal lines; and
pixel electrodes to which one ends of said pixel switching elements, said liquid crystal capacitors and said auxiliary capacitors are connected,
wherein said signal line drive circuit applies the same voltage as that of said opposite electrode to all the signal lines when a control signal supplied from outside of said insulation substrate is in a first logic; and
said scanning line drive circuit turns on all the pixel switching elements when said control signal is in the first logic.
Hereafter, a liquid crystal display according one embodiment of the present invention will be described more specifically with reference to the drawings.
(First Embodiment)
The auxiliary capacitor power supply lines CS1-CSn are provided for the number of pixels in the first direction. The auxiliary capacitor power supply selection circuits 6 are provided corresponding to the auxiliary capacitor power supply lines CS1-CSn.
The AND gate 10 operates a logical product between a power-on power supply control signal s1 for controlling voltages on the auxiliary capacitor power supply lines CS1-CSn at power on time and a polarity reversal power supply control signal s2 for controlling the voltages on the auxiliary capacitor power supply lines CS1-CSn at polarity reverse time, and switches on/off of the transistors 8 and 9 based on the calculation result.
Hereinafter, with reference to
At time “A” in
According to the present embodiment, the power-on power supply control signal s1 is set to be low level (0V) during a predetermined period after power-on, i.e. for time “A”-“B”. Therefore, the outputs of the AND gates 10 in the auxiliary capacitor power supply selection circuits 6 in
Because the first reference voltage VcsH is higher than the second reference voltage VcsL, the voltages on all the auxiliary capacitor power supply lines CS1-CSn become high for a predetermined period after power-on. When the voltages on the auxiliary capacitor power supply lines CS1-CSn become high, the voltages of the pixel electrodes 2 also become high relatively, thereby lowering the voltages at both ends of the liquid crystal C2 (a difference voltage between the voltage of the opposite electrode 3 and the voltages of the pixel electrodes 2). Therefore, for example, in the case of the liquid crystal display of normally white operation (white display at time of applying the signals), display near to white display is obtained at power on, and the undesirable bright line does not emerge.
After then, at time “B”, the auxiliary capacitor power supply control circuits 6 in
Therefore, the voltages on the auxiliary capacitor power supply lines CS1-CSn become the first reference voltage VcsH or the second reference voltage VcsL in sync with the cycle of the polarity reversal drive.
As described above, according to the first embodiment, all the auxiliary capacitor power supply lines CS1-CSn are set to the power supply voltages equal to each other (first reference voltage) for a predetermine period after power-on. Therefore, the voltage levels on the auxiliary power supply lines CS1-CSn does not fluctuate, and the undesirable bright line in horizontal line direction does not appear.
Furthermore, according to the first embodiment, the voltage difference between the voltages on the auxiliary capacitor power supply lines CS1-CSn and the voltage of the opposite electrode 3 becomes small. Because of this, in the case of normally white operation, display near to white display is obtained for a predetermined period after power-on, and the undesirable bright line does not emerge.
(Second Embodiment)
A second embodiment has a feature in that it is possible to prevent display of a undesirable bright line horizontal line direction at power shutdown time.
The liquid crystal display of
The number of the signal lines selected by the signal selection switches 12 is not necessarily limited to three, but may be two or more than three.
The display area section 11 has signal lines and scanning lines arranged in vertical and horizontal directions, pixel TFTs 1 formed in vicinity of cross points of the signal lines and the scanning lines, and auxiliary capacitors C1 and liquid crystal capacitors C2 connected to the pixel TFTs 1. One ends of the auxiliary capacitors C1 are connected to the pixel TFTs 1, and the other ends are connected to the auxiliary capacitor line CS1.
The source driver 5 is implemented on the glass substrate 20 by COG (Chip On Glass). Actually, as shown in
The scanning line drive circuit 4 drives the scanning lines in sequence. A buffer circuit 13 at last stage in the scanning line drive circuit 4 becomes high level forcedly when the scanning line control signal supplied from the source driver 5 becomes low level. Therefore, all the pixel TFTs 1 turn on.
The source driver 5 sets the scanning line control signal to be low level at power shutdown time. Therefore, at power shutdown time, all the pixel TFTs turn on just before the power supply voltage lowers.
All the signal selection switches 12 turn on once at power shutdown time. At this time, the source driver 5 sets all the output terminals to a common voltage. The common voltage is a voltage equal to a voltage on the opposite electrode (hereinafter, this common voltage is called opposite electrode voltage). Because the signal selection switches 12 and the pixel TFTs 1 are turned on, one end voltages of the liquid crystal capacitors C2 become the opposite electrode voltage.
A partial circuit in the scanning line drive circuit 4 including the buffer circuit 13 is supplied with a power supply voltage different from a power supply voltage supplied to the other circuits in the scanning line drive circuit 4. The power supply voltage for the partial circuit in the scanning line drive circuit 4 including the buffer circuit 13 is generated by delaying the power supply voltage for the other circuit with the power supply control circuit 14 of
The present embodiment performs CC (Capacitively Coupled) driving. In CC driving, at a state of turning on the pixel TFTs, the signal voltage is supplied to the signal lines. The voltage on the auxiliary capacitor line CS1 is changed in sync with a cycle of polarity reverse, and therefore, the voltage at both ends of the liquid crystal layer is set. More specifically, in the case of positive polarity, the auxiliary capacitor line CS1 is set to be high level. In the case of negative polarity, the auxiliary capacitor line CS1 is set to be low level. The opposite electrode is fixed on a predetermined DC voltage. The CC driving has a feature in that response is good. Especially, image quality in the case of displaying moving image is improved. In order to perform the CC driving, there is provided a CC driving circuit 15 for controlling the voltage on the auxiliary capacitor lines CS.
Furthermore, the scanning line control signal supplied to the scanning line drive circuit 4 from the source driver 5 becomes high. Therefore, the buffer circuit 13 at last stage in the scanning line drive circuit 4 becomes high level. Accordingly, all the scanning lines become high level, and all the pixel TFTs 1 turn on. At this time, because all the signal lines are supplied with the opposite electrode voltage, the voltages at both ends of the liquid crystal capacitors C2 become equal to each other, and the voltage applied to the liquid crystal layer becomes 0V.
After then, at time t2, the power supply voltages in the circuits except for the buffer circuit 13 at last stage in the scanning line drive circuit 4 begins lowering. Accordingly, the voltages of the opposite electrode and the auxiliary capacitor lines also lower, and the electric charges accumulated in the liquid crystal capacitors C2 and the auxiliary capacitors C1 are discharged.
After then, at time t3, the power supply voltages of the buffer circuits 13 at last stage in the scanning line drive circuit 4 begin lowering. At time t4, all the circuits stop operation.
As described above, according to the second embodiment, at power shutdown time, all the signal lines are once supplied with the opposite electrode voltage, and the voltage applied to the liquid crystal layer is set to 0V, thereby preventing display irregularity due to line noise in horizontal direction. According to the second embodiment, after accumulated electric charge of the liquid crystal capacitors C2 and the auxiliary capacitors C1 is discharged, the pixel TFTs are turned off. Because of this, it is possible to reduce display irregularity due to remaining electric charge.
(Third Embodiment)
A third embodiment performs display irregularity preventing control at power-on time and power shutdown time based on a control signal supplied from outside of a glass substrate.
The liquid crystal display of
The scanning line drive circuit 4 is supplied with a control signal FDON from the external drive circuit 7. With the control signal FDON, it is possible to reduce display irregularity at power-on time and power shutdown time.
The control signal FDON is supplied to all the NAND circuits 22 in the scanning line drive circuit 4. Because of this, when the control signal FDON is in low level, all the pixel TFTs 1 in the display area section 11 are turned on.
The external drive circuit 7 sets the control signal FDON to be low level only for a predetermined period at power-on time and power shutdown time. During this period, all the pixel TFTs 1 are turned on.
The signal line voltage control circuit 21 has a plurality of PMOS transistors connected to the signal lines, respectively. Gates of the PMOS transistors are supplied with the control signal FDON. Drains of the PMOS transistors are supplied with the same voltage as that of the opposite electrode (opposite electrode voltage).
When the control signal FDON becomes low level, all the PMOS transistors in the signal line voltage control circuit 21 turns on, and the signal lines are supplied with the opposite electrode voltage. The opposite electrode voltage applied to the PMOS transistors are supplied via a metal wiring 26 for light shielding arranged along a rim area of the display area section 11. Because the opposite electrode voltage is applied to the PMOS transistors by using the light shielding area 25 provided originally, it is unnecessary to provide a wiring area for the opposite electrode voltage.
During time A-C, display updating for one or a few flames is performed. After then, at time C, the control signal FDON becomes high level. The scanning line drive circuit 4 drives the scanning lines in sequence. The source driver 5 supplies the signal line voltage to the signal lines, in order to perform ordinary display operation.
Power supply control of the scanning line drive circuit 4 and the source driver 5 are performed by the power supply control circuit 27 of
After then, at time E, the power supply voltage of the scanning line drive circuit 4 and the source drive 5 begins lowering. Therefore, the opposite electrode voltage and the pixel electrode voltage also lower in the same way, and the voltage applied to the liquid crystal does not change at 0V. Accordingly, after time E, the bright line noise in horizontal direction does not emerge.
As described above, according to the second embodiment, with the control signal FDON supplied from outside of the glass substrate 20, it is possible to control display irregularity at power-on time and power shutdown time. Accordingly, it is possible to control display irregularity if necessary without complicating the circuits.
Furthermore, according to the present embodiment, the opposite electrode voltage line for setting the signal lines to the opposite electrode voltage is arranged in a light shielding area provided originally. Because of this, it is unnecessary to provide a new area for the opposite electrode voltage line, thereby reducing the rim area of a display panel.
Number | Date | Country | Kind |
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2003-195992 | Jul 2003 | JP | national |
Number | Name | Date | Kind |
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5132819 | Noriyama et al. | Jul 1992 | A |
5808706 | Bae | Sep 1998 | A |
20020158993 | Murai | Oct 2002 | A1 |
Number | Date | Country |
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2001-255851 | Sep 2001 | JP |
Number | Date | Country | |
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20050036078 A1 | Feb 2005 | US |