Patent Application
20080129722
The present invention relates to liquid crystal displays (LCDs), and particularly to an LCD having a delay control circuit for delay gradation voltages.
A typical LCD has the advantages of portability, low power consumption, and low radiation. LCDs have been widely used in various portable information products, such as notebooks, personal digital assistants (PDAs), video cameras and the like. Furthermore, the LCD is considered by many to have the potential to completely replace CRT (cathode ray tube) monitors and televisions.
The first substrate includes a number of gate lines 112 that are parallel to each other and that each extend along a first direction, and a number of data lines 114 that are parallel to each other and that each extend along a second direction orthogonal to the first direction. The intersecting gate lines 112 and data lines 114 define a number of pixel units 120 therebetween. The first substrate also includes a number of thin film transistors (TFTs) 116 that function as switching elements, and a number of pixel electrodes 118. Each TFT 116 is provided in a respective pixel unit 120, in the vicinity of a respective point of intersection of the gate lines 112 and the data lines 114.
The second substrate includes a number of common electrodes 119 generally opposite to the pixel electrodes 118. In particular, the common electrodes 119 are formed on a surface of the second substrate nearest to the first substrate, and are made from a transparent material such as ITO (Indium-Tin Oxide) and the like.
When the LCD 100 works, in each pixel unit 120, a scanning signal generated by a corresponding one of the gate driving circuits 150 is provided to the gate electrode 1162 of the TFT 116. Thus the TFT 116 is switched on. At the same time, gradation voltage generated by a corresponding one of the data driving circuits 130 is provided to the pixel electrode 118 via the corresponding data line 114 and the activated TFT 116 in series.
Because the essential resistance “R” of the data line 114 and the parasitic capacitor Csd form a resistance-capacitance (RC) delay circuit (not labeled), the gradation voltage transmitted on the data line 114 is delayed and reduced by the RC delay circuit, as shown in
It is desired to provide an LCD which can overcome the above-described deficiencies.
In one preferred embodiment, an LCD includes an LCD panel including a plurality of display regions arranged consecutively in a line; a plurality of gate driving circuits respectively connected to the plurality of display regions and configured for providing scanning signals to scan the display regions; at least one data driving circuit configured for generating gradation voltages and providing the gradation voltages to a corresponding display region when the display region is being scanned; and a delay control circuit connected between the at least one data driving circuit and the display regions and configured for delaying the gradation voltages provided to each display region. A first delay value of the gradation voltages is generated by the delay control circuit when the gradation voltages are applied to one of the display regions. A second delay value of the same gradation voltages is generated when the gradation voltages are transmitted from the gate driving circuit to the same one of the display regions. A sum of the first delay value and the second delay value of the gradation voltages is finally provided to the same one of the display regions. The sum of the first delay value and the second delay value for each of the display regions is approximately constant for all of the display regions.
Other novel features and advantages will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
Reference will now be made to the drawings to describe various embodiments of the present invention in detail.
Referring to
The first substrate includes a number of gate lines 212 that are parallel to each other and that each extend along a first direction, and a number of data lines 214 that are parallel to each other and that each extend along a second direction orthogonal to the first direction. The intersecting gate lines 212 and data lines 214 define a number of pixel units (not labeled) therebetween. The first substrate also includes a number of thin film transistors (TFTs) 216 that function as switching elements, and a number of pixel electrodes 218. Each TFT 216 is provided in a respective pixel unit, in the vicinity of a respective point of intersection of the gate lines 212 and the data lines 214.
The second substrate includes a number of common electrodes 219 generally opposite to the pixel electrodes 218. In particular, the common electrodes 219 are formed on a surface of the second substrate nearest to the first substrate, and are made from a transparent material such as ITO (Indium-Tin Oxide) and the like.
Each gate driving circuit 250 includes a number of output terminals (not labeled) respectively connected to the gate lines 212, and a trigger signal output terminal 251. Each region of the LCD panel 210 corresponding to the gate lines 212 that are connected to one same gate driving circuit 250 is defined as a display region 240. Thus a number n (where n is a natural number) of display regions are defined sequentially starting from adjacent to the data driving circuits 230 and progressing farther and farther away from the data driving circuits 230.
The delay control circuit 260 includes a control circuit 290, a number of delay transistors 270, and a number of control signal inputs (not labeled) connected to the trigger signal output terminals 251. Each delay transistor 270 includes a gate electrode (not labeled) connected to the control circuit 290, a drain electrode (not labeled) connected to the corresponding data line 214, and a souce electrode (not labeled).
Each data driving circuit 230 includes a number of output terminals respectively connected to the source electrodes of corresponding of the delay transistors 270. Thus each output terminal of the data driving circuits 230 is connected to the corresponding data line 212 via one of the delay transistors 270. The data driving circuits 230 generate a number of gradation voltages, and sequentially provide the gradation voltages to the number n of display regions 240 when the number n of display regions 240 is sequentially scanned by the gate driving circuits 250.
When the LCD 200 works, an external circuit (not shown) provides a start signal to the number 1 gate driving circuit 250 and the control circuit 290 of the delay control circuit 260. The number 1 gate driving circuit 250 generates a number of scanning signals, and sequentially provides the scanning signals to the gate lines 212 of the number 1 display region 240 for switching on the corresponding TFTs 216. At the same time, the control circuit 290 of the delay control circuit 260 generates a first control voltage V1 and transmits the first control voltage to the delay transistors 270 of the delay control circuit 260. The data driving circuits 230 generate a number of gradation voltages, and sequentially provide the gradation voltages to the corresponding pixel electrodes 218 of the number 1 display region 240 via the delay transistors 270, the data lines 214, and the activated TFTs 216 in series.
After all the gradation voltages corresponding to the number 1 display region are completely provided to the pixel units of the number 1 display region, the number 1 gate driving circuit 250 applies a control signal to the number 2 gate driving circuit 250 and the control circuit 290 of the delay control circuit 260. The number 2 gate driving circuit 250 generates a number of scanning signals, and sequentially provides the scanning signals to the gate lines 212 of the number 2 display region 240 for switching on the corresponding TFTs 216. At the same time, the control circuit 290 of the delay control circuit 260 generates a second control voltage V2 (V2>V1) and transmits the second control voltage to the delay transistors 270 of the delay control circuit 260 in response to the control signal generated by the number 1 gate driving circuit 250. The data driving circuits 230 generate a number of gradation voltages, and sequentially provide the gradation voltages to the corresponding pixel electrodes 218 of the number 2 display region 240 via the delay transistors 270, the data lines 214, and the activated TFTs 216 in series.
After all gradation voltages corresponding to the number n-1 display region are completely provided to the pixel units of the number n-1 display region, the number n-1 gate driving circuit 250 applies a control signal to the number n gate driving circuit 250 and the control circuit 290 of the delay control circuit 260. The number n gate driving circuit 250 generates a number of scanning signals, and sequentially provides the scanning signals to the gate lines 212 of the number n display region 240 for switching on the corresponding TFTs 216. At the same time, the control circuit 290 of the delay control circuit 260 generates a number n control voltage Vn(Vn>Vn-1) and transmits the number n control voltage to the delay transistors 270 of the delay control circuit 260 in response to the control signal generated by the number n-1 gate driving circuit 250. The data driving circuits 230 generate a number of gradation voltages, and sequentially provide the gradation voltages to the corresponding pixel electrodes 218 of the number n display region 240 via the delay transistors 270, the data lines 214, and the activated TFTs 216 in series.
To summarize operation, when the gate driving circuits 250 from number 1 to number n work sequentially, the control circuit 290 of the delay control circuit 260 provides gradually increased control voltages V1. . . Vn to the delay transistors 270 for delaying the gradation voltages sequentially provided to the corresponding display regions 240. As a distance of the display region 240 to the data driving circuits 230 is increased, a delayed value of the gradation voltage provided to the corresponding display region 240 is gradually reduced.
Because the LCD 200 includes the delay control circuit 260, the gradation voltages sequentially provided to the corresponding display regions 240 can be delayed according to the distances of the display regions 240 relative to the data driving circuits 230. The delayed value ΔV1 of the gradation voltages generated by the delay control circuit 260 is gradually reduced with increasing distance of the corresponding display region 240 from the data driving circuits 230. At the same time, an essential resistance of each data line 214 and a parasitic capacitor connected to the data line 214 form an RC delay circuit (not labeled). The gradation voltage transmitted on the data line 214 is delayed and reduced by the RC delay circuit. A delayed value ΔV2 of the gradation voltage generated by the RC delay circuit is gradually increases with increasing distance of the corresponding display region 240 from the data driving circuits 230. Thus, the gradation voltages provided to each display region 240 includes a first delay value ΔV1 and a second delay value ΔV2. The amount of the first delay value ΔV1 and the second delay value ΔV2 is approximately equal to a constant. Thus, the brightness of a display region 240 of the LCD 200 far from the data driving circuits 230 is approximately equal to that of a display region 240 of the LCD 200 near the data driving circuits 230. Therefore, the brightness of LCD 200 can be uniform.
In an alternative embodiment of the present invention, the data driving circuits 230 can be replaced by a single data driving circuit.
It is to be understood, however, that even though numerous characteristics and advantages of preferred and exemplary embodiments have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only; and that changes may be made in detail, especially in matters of arrangement of parts within the principles of present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 95144735 | Dec 2006 | TW | national |
