BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic cross-sectional view of a liquid crystal display panel according to an embodiment of the present invention.
FIG. 2 is a schematic circuit diagram of an active device array substrate according to an embodiment of the present invention.
FIG. 3 is a schematic view of a ditch according to an embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view of a ditch according to another embodiment of the present invention.
FIGS. 5A to 5E are schematic views of patterns of various ditches according to the present invention.
DESCRIPTION OF EMBODIMENTS
First Embodiment
FIG. 1 is a schematic cross-sectional view of a liquid crystal display panel according to an embodiment of the present invention, and FIG. 2 is a schematic circuit diagram of an active device array substrate according to an embodiment of the present invention. Referring to both FIGS. 1 and 2, the liquid crystal display panel 200 of the present invention includes an active device array substrate 210, a liquid crystal layer 260 and an opposite substrate 270, wherein the liquid crystal layer 260 is located between the active device array substrate 210 and the opposite substrate 270. Particularly, the active device array substrate 210 of the present invention has a display area A and includes a substrate 211, a plurality of scan lines 212, a plurality of data lines 214, a plurality of active devices 220, a patterned passivation layer 230, a plurality of pixel electrodes 240 and a sealant layer S. The scan lines 212 and the data lines 214 are used to divide positions for the active devices 220 in the display area A.
As shown in FIG. 2, the active devices 220 of the present invention are arranged in an array within the display area A, and each active device 220 is electrically connected to the scan line 212 and the data line 214 correspondingly. Additionally, the active devices 220 are electrically connected to the corresponding pixel electrodes 240. Particularly, the active devices 220 is turned on through a switch signal transmitted via the scan lines 212, and after the active devices 220 has been turned on, a display signal is transmitted to the pixel electrodes 240 via the data lines 214. While the active device 220 shown in FIG. 1 is a bottom gate structure, it is not particularly limited herein as such. Rather, the active devices 220 may also be a top gate structure.
For example, the active device 220 includes a gate 222, a gate insulation layer 223, a channel layer 224, an ohmic contact layer 225, a source 226 and a drain 227. The gate 222 is disposed on the substrate 211, and is covered by the gate insulation layer 223. Moreover, the channel layer 224 is disposed on the gate insulation layer 223 above the gate 222. Generally, the channel layer 224 is made of a semiconductor material, and the source 226 and the drain 227 are made of metals. In practice, in order to reduce the contact impedance between the metal material and the semiconductor material, an ohmic contact layer 225 is respectively formed between the source 226 and the channel layer 224 and between the drain 227 and the channel layer 224.
Particularly, the scan line 212 is electrically connected to the gate 222 of the active device 220, and the data line 214 is electrically connected to the source 226 of the active device 220. In addition, the patterned passivation layer 230 covers the active device 220, the scan line 212 and the data line 214, and the material of the patterned passivation layer 230 is generally selected from a group consisting of an organic material, silicon nitride, silicon oxide or silicon oxynitride, or any combination thereof. In practice, the drain 227 of the active device 220 is electrically connected to the pixel electrode 240 via a contact hole (not shown) in the patterned passivation layer 230. The pixel electrodes 240 are arranged in array on the patterned passivation layer 230 in the display area A. The active device array substrate 210 further includes a first alignment film layer 250 for aligning the liquid crystals and covering the pixel electrodes 240 and a part of the patterned passivation layer 230.
FIG. 3 is a schematic view of a ditch according to an embodiment of the present invention. Referring to both FIGS. 1 and 3, it should be noted that the patterned passivation layer 230 of the present invention has a plurality of ditches D, and that the first alignment film layer 250 is filled into the ditches D and thereby being congruent with the ditches D. Moreover, the sealant layer S is located surrounding the display area A, a buffer area B is located between the sealant layer S and the display area A, and the ditches D are communicated to the buffer area B. The ditches D may be integrally formed on the patterned passivation layer 230 through one photolithography process, and thus the fabrication of the ditches D of the present invention does not require any additional process.
As shown in FIG. 3, the active device array substrate 210 further includes a plurality of barriers R, which are located surrounding the boundary of the display area A, so as to form a buffer area B between the display area A and the sealant layer S. It should be noted that gaps C with a suitable size exist between the barriers R, and therefore the ditches D communicate with the buffer area B via the gaps C. In an embodiment of the present invention, the height of the barrier R is smaller than the cell gap between the active device array substrate 210 and the opposite substrate 270, such that the ditches D communicate with the buffer area B via the cell gap (not shown) between the barrier R and the opposite substrate 270.
In practice, the barrier R of the present invention may be selectively formed on the active device array substrate 210 or on the opposite substrate 270. Alternatively, the barrier R may also be formed to partially overlap the active device array substrate 210 and the opposite substrate 270, which is not particularly limited herein as such.
When performing the ODF process, liquid crystal drops are first dropped in the display area A (on the first alignment film layer 250) of the active device array substrate 210. Then, the active device array substrate 210 and the opposite substrate 270 are aligned and assembled together in a substantially vacuum environment. At this time, the liquid crystals are diffused more uniformly with the ditches D. In order to further enhance the diffusion efficiency of the liquid crystals, a thermal rotation process is selectively performed to the liquid crystal display panel 200, which reduces the viscosity of the liquid crystals by raising the temperature, and further enhances the diffusion efficiency of the liquid crystals by spinning the liquid crystal display panel 200. Therefore, the liquid crystals are uniformly distributed on the liquid crystal display panel 200.
Referring to FIG. 1 again, the position of the ditch D corresponds to the gap between the pixel electrodes 240, and the width of the bottom part of the ditch D is smaller than that of its opening, and of course, the width of the bottom part of the ditch D may be the same as that of its opening (as shown in FIG. 4), which may be adjusted appropriately depending upon actual requirements. In addition, in FIG. 3, one part of the ditches D extends in the direction of the scan lines 212, and the other part of the ditch D extends in the direction of the data lines 214. Of course, the ditches D may selectively extend in the direction of the scan lines 212, or only extend in the direction of the data lines 214, which is not specifically limited herein as such.
Particularly, during the ODF process, if the dropping amount of the liquid crystals is excessively large, the redundant liquid crystals flow towards the buffer area B after the active device array substrate 210 and the opposite substrate 270 of the present invention have been assembled together, thereby maintaining an adequate amount of liquid crystals between the two substrates. Thus, the active device array substrate 210 and the opposite substrate 270 of the present invention can effectively reduce the possibility of the adverse influence caused due to the excessive filling of liquid crystals, thereby maintain a desired cell gap between the two substrates. On the other hand, the liquid crystal display panel 200 of the present invention may also effectively avoid the mura phenomenon caused due to the vertical flow of redundant liquid crystals.
It should be noted that, as the gaps C are very small, the liquid crystals do not easily pass there through under a normal circumstance, but only under the circumstance that excessive liquid crystals have been dropped. The redundant liquid crystals flow towards the buffer area B under the pressure generated when the active device array substrate 210 and the opposite substrate 270 are assembled together. However, once the liquid crystals flow to the buffer area B, it is not easy for them to flow back.
FIGS. 5A to 5E are schematic views of patterns of various ditches according to the present invention. Referring to FIGS. 5A to 5E, in order to further enhance the diffusion efficiency of the liquid crystals, the pattern of the ditches D may be changed appropriately, which is not specifically limited herein as such. The various patterns of ditches D shown in FIGS. 5A to 5E may be achieved by adjusting the mask patterns employed in patterned process.
Referring to FIG. 1 again, the opposite substrate 270 of the present invention includes a substrate 271, a black matrix 272, a plurality of color filter films 273, a common electrode 274, and a second alignment film layer 275. The black matrix 272 is disposed over the substrate 271, and it has a plurality of lattice points L. The color filter films 273 are disposed over the substrate 271 and respectively located in the lattice points L. Particularly, the color filter films 273 include red resin, green resin and blue resin, and the liquid crystal display panel 200 of the present invention may achieve the full color display with the color filter films 273. Moreover, the common electrode 274 covers the black matrix 272 and the color filter films 273, and the second alignment film layer 275 for aligning the liquid crystals is disposed on the common electrode 274. Generally, the common electrode 274 is coupled to a reference voltage source, and the common electrode 274 may form an electric field with the pixel electrode 240, so as to drive the liquid crystals.
The ditches D and/or active devices 220 are disposed below the black matrix 272, as shown in FIG. 1. Therefore, the black matrix 272 effectively shields the light leakage phenomenon caused by the electric field interference of the active devices 220, thereby further maintaining the display quality of the liquid crystal display panel 200.
According to the present invention, the patterned passivation layer on the active device array substrate has ditches, which are capable of uniformly diffusing liquid crystal molecules, such that redundant liquid crystal molecules may be diffused towards the buffer area via the ditches. Thus, a desired cell gap is maintained between the upper and lower substrates, thereby enhancing the display quality of the liquid crystal display panel.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure/process of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations thereof, provided they fall within the scope of the appended claims.
Patent Application
20080018818
