Patent Application
20190004357
The present invention relates to a liquid crystal display panel.
An active matrix liquid crystal display panel typically includes an active matrix substrate, a counter substrate disposed facing the active matrix substrate, and a liquid crystal layer provided between the two substrates. The active matrix substrate includes a switching element, e.g. a thin film transistor (TFT), for each pixel. A display region of the liquid crystal display panel is defined by a plurality of pixels in the active matrix substrate. Drive circuits and the like are mounted or formed monolithically in a non-display region (also called a “frame region”) in the periphery of the display region.
Liquid crystal display panels employing transverse electrical field modes, liquid crystal display panels employing Vertical Alignment (VA) modes, and the like, for example, are widely used as active matrix liquid crystal display panels having wide viewing angle characteristics.
In-Plane Switching (IPS) mode liquid crystal display panels and Fringe Field Switching (FFS) mode liquid crystal display panels are examples of transverse electrical field mode liquid crystal display panels. In a transverse electrical field mode liquid crystal display panel, an electrical field is produced in the liquid crystal layer in a direction parallel to the substrate surfaces by applying voltages to pixel electrodes and common electrodes (also called “counter electrodes”) formed on the active matrix substrate. In a VA mode liquid crystal display panel, which is a vertical electrical field mode liquid crystal display panel, an electrical field is produced in the liquid crystal layer in a direction perpendicular to the substrate surfaces (a vertical direction) by applying a voltage to pixel electrodes and counter electrodes disposed facing each other with the liquid crystal layer located therebetween. Examples of VA mode liquid crystal display panels include Multidomain Vertical Alignment (MVA) mode liquid crystal display panels, where a plurality of domains in which the liquid crystal molecules are aligned in different directions are formed in a single pixel, and Continuous Pinwheel Alignment (CPA) mode liquid crystal display panels, where the directions in which the liquid crystal molecules are aligned are varied continuously central to a rivet or the like formed on an electrode in a central part of the pixel.
Generally, the thickness of the liquid crystal layer of a liquid crystal display panel (also called the “cell gap”) is defined by spacers disposed between the active matrix substrate and the counter substrate. In addition to being disposed within the display region, the spacers are sometimes disposed in the non-display region as well. There are also situations where spacers (granular spacers) are mixed into a sealing material for laminating the active matrix substrate to the counter substrate.
As the resolutions of liquid crystal display panels increase, methods in which photolithography processes are used to form spacers in predetermined locations are being widely employed. Spacers formed in this manner will be called photo spacers (sometimes abbreviated as “PS”).
Although usually formed on the counter substrate (a color filter substrate), photo spacers are sometimes provided on the active matrix substrate.
The liquid crystal display panel illustrated in FIG. 40 of PTL 1 is a FFS mode liquid crystal display panel, and a photo spacer is disposed corresponding to each pixel. Each photo spacer is formed on the active matrix substrate while overlapping with a gate bus line when viewed from a direction perpendicular to the substrate surface. Forming each photo spacer in the same location relative to the corresponding pixel makes it easier to ensure the photo spacers have a constant height. This is because an active matrix substrate has, for example, TFTs, gate bus lines, source bus lines, and the like on the surface of a glass substrate, and thus the surface is not necessarily flat; furthermore, the intensity distribution of light used in the exposure step for forming the photo spacers is not uniform. According to PTL 1, the photo spacers are formed using a synthetic resin film that levels the surface of the active matrix substrate prior to the common electrodes being formed. In the liquid crystal display panel illustrated in FIG. 40 of PTL 1, the photo spacers are disposed in a flat region above the gate bus lines.
PTL 1: WO 01/018597
However, according to investigations by the inventors of the present invention, a liquid crystal display panel such as that illustrated in FIG. 40 of PTL 1 has had a problem in that the display quality drops near the photo spacers due to disorder in the alignment of the liquid crystal molecules (e.g. the contrast drops or graininess arises).
Insufficient alignment treatment on an alignment film in the periphery of the photo spacers was found to be one cause of this problem. When subjecting an alignment film to a rubbing treatment as an alignment treatment for defining the alignment direction (called a “pretilt direction”) of the liquid crystal molecules when no electrical field is applied, there have been situations where the alignment film is insufficiently rubbed in the periphery of the photo spacers (particularly on the downstream side of the rubbing direction).
Partial peeling of the alignment film, caused by vibrations or external forces imparted on the liquid crystal display panel, was found to be another cause. The effects of vibrations are prominent in liquid crystal display panels installed in vehicles such as automobiles and aircraft, for example. Furthermore, in a liquid crystal display panel that incorporates a touch panel or a digitizer, forces are exerted on the liquid crystal display panel from the exterior by a user's finger or an input pen, which is thought to increase the likelihood that the alignment film will partially peel and cause the alignment to become disordered. This will be described in detail later.
In response to the problem of the display quality dropping due to disorder in the alignment of the liquid crystal molecules near the photo spacers, the drop in display quality can be suppressed by, for example, using a light shielding layer (a black matrix) provided on the counter substrate to cover the portions where the alignment of the liquid crystal molecules can become disordered. However, in this case, the light shielding layer (black matrix) has a greater surface area than in the related art, which causes the aperture ratio of the liquid crystal display panel to drop.
Having been achieved to solve the above-described problems, an object of the present invention is to suppress a drop in display quality caused by disorder in the alignment of liquid crystal molecules near photo spacers without reducing the aperture ratio in a liquid crystal display panel.
A liquid crystal display panel according to embodiments of the present invention includes: a first substrate; a second substrate; a liquid crystal layer provided between the first substrate and the second substrate; and a plurality of spacers configured to hold a gap between the first substrate and the second substrate. The first substrate includes: a first transparent substrate; a plurality of TFTs formed on the first transparent substrate, each of the plurality of TFTs including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; a plurality of first wiring lines including a part of a first metal layer, each of the plurality of first wiring lines being connected to one of the gate electrode and the source electrode of a corresponding one of the plurality of TFTs; a plurality of second wiring lines including a part of a second metal layer, each of the plurality of second wiring lines being connected to the other of the gate electrode and the source electrode of a corresponding one of the plurality of TFTs; an inorganic insulating layer formed on the second metal layer; a first transparent conductive layer formed under the inorganic insulating layer; a second transparent conductive layer formed on the inorganic insulating layer; and an organic insulating layer formed on the inorganic insulating layer. Each of the plurality of spacers overlaps with at least one of the source electrode and the drain electrode of a corresponding one of the plurality of TFTs, and each of the plurality of spacers includes a part of the organic insulating layer.
In some embodiments, the liquid crystal display panel includes a plurality of pixel openings, and each of the plurality of pixel openings includes a layered structure, the layered structure including the first transparent conductive layer, the inorganic insulating layer, and the second transparent conductive layer but not including the organic insulating layer.
In some embodiments, a part of the second transparent conductive layer is formed on the organic insulating layer.
In some embodiments, in a case that a distance, in a normal direction of the first substrate, from a surface of the first transparent substrate closer to the liquid crystal layer to a surface of the inorganic insulating layer closer to the liquid crystal layer is taken as a height, the height at places where the plurality of spacers are provided is greater than the height at places where the plurality of spacers are not provided and that include a layered structure including the first transparent conductive layer and the second transparent conductive layer.
In some embodiments, a part of the organic insulating layer is formed on the plurality of second wiring lines, and is formed substantially parallel to the plurality of second wiring lines while covering at least part of the plurality of second wiring lines.
In some embodiments, the plurality of second wiring lines include a part not covered by the organic insulating layer.
In some embodiments, the plurality of spacers do not overlap with the second transparent conductive layer.
In some embodiments, the plurality of spacers include spacers that, when viewed from the normal direction of the first substrate, overlap entirely with the first metal layer and/or the second metal layer.
In some embodiments, the first transparent conductive layer includes a first transparent electrode; the second transparent conductive layer includes a second transparent electrode opposing the first transparent electrode with the inorganic insulating layer between the first transparent electrode and the second transparent electrode; one of the first transparent electrode and the second transparent electrode is connected to one of the source electrode and the drain electrode; and the second transparent electrode includes at least one slit. The second transparent electrode may include a plurality of slits extending parallel to each other.
In some embodiments, the second transparent electrode functions as a common electrode, and the second transparent electrode covers a part of the organic insulating layer formed covering at least a part of the plurality of second wiring lines.
In some embodiments, the liquid crystal display panel includes a plurality of pixels, and each of the plurality of pixels includes an auxiliary capacitance formed by the first transparent electrode, the inorganic insulating layer, and the second transparent electrode.
In some embodiments, the plurality of spacers include a spacer in direct contact with the inorganic insulating layer.
In some embodiments, the plurality of spacers include a plurality of first spacers that define a gap between the first substrate and the second substrate, and a plurality of second spacers that are lower than the plurality of first spacers.
In some embodiments, the second substrate includes a plurality of projection-shaped structures protruding toward the first substrate; and the plurality of spacers include a spacer that further includes a corresponding one of the plurality of projection-shaped structures.
In some embodiments, the first substrate includes a first alignment film on a side of the first substrate closer to the liquid crystal layer; the second substrate includes a second alignment film on a side of the second substrate closer to the liquid crystal layer; and alignment restriction directions defined by the first alignment film and the second alignment film form an angle of greater than 0° and less than or equal to 15° degrees with a direction in which the plurality of second wiring lines extend.
In some embodiments, the liquid crystal layer includes a nematic liquid crystal material having positive dielectric anisotropy, and functions in a transverse electrical field mode.
According to embodiments of the present invention, a drop in display quality caused by disorder in the alignment of liquid crystal molecules near photo spacers can be suppressed without causing a drop in the aperture ratio in a liquid crystal display panel.
Embodiments of the present invention will be described below with reference to the drawings. Note, however, that the present invention is not limited to the following embodiments. In the descriptions of the drawings below, constituent elements having substantially identical functions will be given identical reference signs, and descriptions thereof may be omitted.
A liquid crystal display panel 100 according to a first embodiment of the present invention will be described with reference to
Although the liquid crystal display panel 100 illustrated here is a FFS mode liquid crystal display panel, the liquid crystal display panel according to the embodiments is not limited thereto, and can also be applied in an IPS mode liquid crystal display panel. Additionally, the embodiments of the present invention are not limited to a transverse electrical field mode. The embodiments can also be applied in a vertical electrical field mode (e.g. a VA mode and a Twisted Nematic (TN) mode) liquid crystal display panel. An example of a CPA mode liquid crystal display panel will be given later as an example of a vertical electrical field mode.
As illustrated in
The structure of the display region 100d in the liquid crystal display panel 100 will be described with reference to
As illustrated in
Next, the structures of the active matrix substrate 10 and the counter substrate 30 will be described in detail with reference to
The gate metal layer (first metal layer) 12 is provided on the first transparent substrate 11. The gate metal layer (first metal layer) 12 includes the gate electrodes 12g of the TFTs 17 and a plurality of the gate bus lines (a plurality of first wiring lines) G. The gate metal layer 12 may have a single-layer structure, or may have a layered structure in which a plurality of layers are layered. The gate metal layer 12 includes at least a layer formed from a metal material. In a case where the gate metal layer 12 has a layered structure, some of the layers may be formed from a metal nitride or a metal oxide.
In this specification, the gate metal layer (first metal layer) 12 is a layer containing electrodes, wiring lines, terminals, and the like formed by patterning a conductive film that forms the gate electrodes 12g and the gate bus lines G. In other words, in addition to the gate electrodes 12g and the gate bus lines G, the pattern of the gate metal layer 12 includes electrodes, wiring lines, terminals, and the like formed by patterning a conductive film that forms the gate electrodes 12g and the gate bus lines G. Likewise, the source metal layer (second metal layer) 16 is a layer containing electrodes, wiring lines, terminals, and the like formed by patterning a conductive film that forms the source electrodes 16s, the drain electrodes 16d, and the source bus lines S, and may include drain lead-out wiring lines for connecting the drain electrodes 16d to the pixel electrodes 22a, for example, in addition to the source electrodes 16s, the drain electrodes 16d, and the source bus lines S. In other words, in addition to the source electrodes 16s, the drain electrodes 16d, and the source bus lines S, the pattern of the source metal layer 16 includes electrodes, wiring lines, terminals, and the like (e.g. drain lead-out wiring lines) formed by patterning a conductive film that forms the source electrodes 16s, the drain electrodes 16d, and the source bus lines S.
The gate insulating layer 13 is provided on the gate metal layer 12. In other words, the gate insulating layer 13 is formed covering the gate electrodes 12g and the gate bus lines G. The gate insulating layer 13 is formed from an inorganic insulating material.
The semiconductor layer 14 is provided on the gate insulating layer 13, and includes an active layer of the TFTs 17. The active layer of the TFTs 17 includes channel regions 14i. The semiconductor layer 14 may have a layered structure including an intrinsic semiconductor layer (e.g. an amorphous silicon layer) and a semiconductor layer having reduced resistance obtained by doping a semiconductor with an impurity (e.g. a phosphorous-doped n+ amorphous silicon layer). However, the channel regions 14i do not include the impurity-doped semiconductor layer. The impurity-doped semiconductor layer is formed in portions aside from the channel regions 14i, for example. Preferably, the impurity-doped semiconductor layer is provided within the active layer of the TFTs 17, in source regions and drain regions. Part of the impurity-doped semiconductor layer may be disposed under the source bus lines S. In this case, parts of the impurity-doped semiconductor layer function as source bus lines.
The source metal layer (second metal layer) 16 is provided on the semiconductor layer 14. The source metal layer (second metal layer) 16 includes the source electrodes 16s and the drain electrodes 16d of the TFTs 17, and a plurality of the source bus lines (a plurality of second wiring lines) S. The source metal layer 16 may have a single-layer structure, or may have a layered structure in which a plurality of layers are layered. The source metal layer 16 includes at least a layer formed from a metal material. In a case where the source metal layer 16 has a layered structure, some of the layers may be formed from a metal nitride or a metal oxide. The gate metal layer 12 and the source metal layer 16, which include layers formed from a metal material, are generally more conductive than conductive layers formed from a transparent conductive material. This makes it possible to reduce the width of the wiring lines, which contributes to higher resolutions and improvements in pixel aperture ratios.
The first transparent conductive layer 22 is provided on the source metal layer 16. The first transparent conductive layer 22 is formed from a transparent conductive material. The first transparent conductive layer 22 includes first transparent electrodes 22a electrically connected to the drain electrodes 16d of corresponding ones of the TFTs 17. The first transparent electrodes 22a electrically connected to the drain electrodes 16d function as pixel electrodes. The pixel electrodes 22a are in direct contact with the drain electrodes 16d, for example. The first transparent conductive layer 22 and the source metal layer 16 may be in direct contact. Here, the first transparent conductive layer 22 and the source metal layer 16 being “in direct contact” means that no insulating layer is present between the first transparent conductive layer 22 and the source metal layer 16. In a case where no insulating layer is present between the pixel electrodes 22a and the drain electrodes 16d, the pixel electrodes 22a and the drain electrodes 16d can be electrically connected without carrying out a step for forming the insulating layer and a step for forming contact holes in the insulating layer. The TFTs 17 and the pixel electrodes 22a are provided on a pixel-by-pixel basis (i.e. each pixel includes a TFT 17 and a pixel electrode 22a).
The inorganic insulating layer 23 is provided on the semiconductor layer 14, the source metal layer 16, and the first transparent conductive layer 22. In other words, the first transparent conductive layer 22 is formed under the inorganic insulating layer 23.
The second transparent conductive layer 26 is formed on the inorganic insulating layer 23. The second transparent conductive layer 26 includes second transparent electrodes 26a that are not electrically connected to the pixel electrodes 22a. The second transparent electrodes 26a function as common electrodes. The common electrodes 26a face the pixel electrodes 22a with the inorganic insulating layer 23 located therebetween, and the pixel electrodes 22a, the common electrodes 26a, and the inorganic insulating layer 23 located therebetween constitute an auxiliary capacitance. The auxiliary capacitance is electrically connected (connected in parallel) to a liquid crystal capacitance (a capacitance formed by the pixel electrodes 22a, the common electrodes 26a, and the liquid crystal layer 40), and thus an effect can be achieved in which the auxiliary capacitance holds the liquid crystal capacitance. The pixel electrodes 22a and the common electrodes 26a constitute electrode pairs that produce a transverse electrical field in the liquid crystal layer 40. The common electrodes 26a include a plurality of slits 26as extending parallel to each other. Note that the arrangement relationship of the pixel electrodes 22a and the common electrodes 26a may be reversed. In other words, the first transparent electrodes 22a may function as the common electrodes and the second transparent electrodes 26a may function as the pixel electrodes. In this case, the pixel electrodes 26a include a plurality of slits. Here, the number of slits in the second transparent electrodes 26a (the common electrodes 26a or the pixel electrodes 26a) need not be a plurality for each pixel, and at least one slit per pixel is sufficient.
The organic insulating layer 25 is formed on the inorganic insulating layer 23. The organic insulating layer 25 may be in direct contact with the inorganic insulating layer 23. Parts of the organic insulating layer 25 constitute the spacers 50. In other words, each of the plurality of spacers 50 includes a part of the organic insulating layer 25. The plurality of spacers 50 may include spacers 50 in direct contact with the inorganic insulating layer 23. The spacers 50 are provided to hold a gap between the active matrix substrate 10 and the counter substrate 30.
The plurality of spacers 50 can include, for example, first spacers 51 that define a distance between the active matrix substrate 10 and the counter substrate 30, and second spacers 52 that are lower than the first spacers 51. In other words, the first spacers 51 control the thickness of the liquid crystal layer 40 (also called a “cell gap”). The first spacers 51 may be called “main spacers”, and the second spacers 52 may accordingly be called “sub spacers”. Typically, the first spacers 51 are in contact with the counter substrate 30, but the second spacers 52 are not in contact with the counter substrate 30. However, the first spacers 51 are not necessarily in contact with the counter substrate 30. For example, it is possible that the cell gap will vary in at least part of the liquid crystal layer 40 in a case where the temperature of the liquid crystal layer 40 changes, in a case where the display panel is attached to another object using attachment members (e.g. attachment screws or the like) and mechanically deforms at the positions where the attachment members are located, in a case where the liquid crystal display panel is installed in a curved state, or the like.
The second spacers 52 can be omitted, but including the second spacers 52 in addition to the first spacers 51 provides the following effects. In liquid crystal display panels in the related art, increasing the density at which photo spacers are disposed (the number of photo spacers per unit of area) to improve the load-bearing characteristics has been a problem in that doing so makes it more likely that low-temperature bubbling (vacuum bubbling) will occur. In the liquid crystal display panel 100, the cell gap is basically controlled only by the first spacers 51, and thus the spacer density is essentially defined by the first spacers 51 only. This makes it easy for the cell gap to follow contraction of the liquid crystal layer 40, which makes it possible to suppress the occurrence of low-temperature bubbling. Additionally, when the cell gap narrows due to a load being exerted on the liquid crystal display panel 100, both substrates are supported by both the first spacers 51 and the second spacers 52 (the effective spacer density at this time is defined by both the first spacers 51 and the second spacers 52), and thus good load-bearing characteristics can be realized.
The plurality of spacers 50 are provided on a pixel-by-pixel basis, for example. The plurality of spacers 50 may be provided for all of the plurality of pixels in the liquid crystal display panel 100, or may be provided for only some of the pixels. The ratio between the first spacers 51 and the second spacers 52 may also be set as desired, and may be set as appropriate in consideration of the application of the liquid crystal display panel (the planned usage environment), the number of pixels, and the like.
Each of the spacers 50 provided in the display region 100d of the liquid crystal display panel 100 is disposed overlapping with a corresponding TFT 17 when viewed from the normal direction of the active matrix substrate 10. In other words, as illustrated in
As illustrated in
A problem to be solved by embodiments of the present invention will be described next with reference to
In regions near spacers 950, which are indicated by dotted lines in
Insufficient alignment treatment on the alignment film in the periphery of the spacers was found to be one cause of the problem of the display quality dropping near the spacers due to disorder in the alignment of the liquid crystal molecules.
In a transverse electrical field mode liquid crystal display panel, the alignment direction of the liquid crystal molecules when no electrical field is applied is defined, for example, by subjecting the alignment film to a rubbing treatment as an alignment treatment. When a voltage is applied to electrode pairs (here, the pixel electrodes 22a and the common electrodes 26a) to produce a transverse electrical field in the liquid crystal layer 40 (an electrical field in the horizontal direction; an electrical field parallel to the plane of the liquid crystal layer), the transverse electrical field is produced in a direction orthogonal to the direction in which the slits 26as in the common electrodes 26a extend. For example, nematic liquid crystal molecules having positive dielectric anisotropy are aligned such that the long axes of the molecules (parallel to the director) are parallel to the electrical field. Accordingly, when the liquid crystal layer 40 includes a nematic liquid crystal material having positive dielectric anisotropy, rubbing the material in a direction substantially parallel to a direction orthogonal to the direction of the transverse electrical field (the direction in which the slits 26as extend) causes the liquid crystal molecules to be aligned substantially parallel to the slits 26as when no electrical field is applied. When viewed from the normal direction of the active matrix substrate 10, the orientation of the alignment as restricted by the first alignment film 27 and the second alignment film 37 is parallel or antiparallel, for example. Generally, the alignment direction of the liquid crystal molecules when no electrical field is applied is defined so as to form an angle of greater than 0° and less than or equal to 15°, for example, with a direction orthogonal to the direction of the transverse electrical field (the direction in which the slits extend). This makes it possible to define the direction in which the liquid crystal molecules rotate (counter-clockwise or clockwise) under the transverse electrical field when a voltage is applied. The response speed of the liquid crystal molecule when a voltage is applied can be improved as well. For example, in the liquid crystal display panel 900A according to the first comparative example illustrated in
In such a rubbing treatment, there have been situations where the alignment film is insufficiently rubbed in the periphery of the photo spacers (particularly in portions in the shadows of the spacers relative to the rubbing direction, i.e. downstream in the rubbing direction). This can produce disorder in the alignment of the liquid crystal molecules. Of the portions where the alignment treatment is insufficient, the display quality sometimes drops in regions not covered by the light shielding layer (black matrix) 32 of the counter substrate 30 (the regions indicated by dotted lines in
The method of the alignment treatment on the alignment film is not limited to a rubbing treatment, and may be an optical alignment treatment instead. For example, the alignment treatment is sometimes carried out through an optical alignment treatment in VA mode liquid crystal display panels. The problem of the alignment treatment on the alignment film being insufficient in the periphery of the spacers can arise in optical alignment treatments as well. For example, in a case where the substrate is irradiated with light from a direction slanted relative to the normal direction of the substrate, an alignment treatment using light may not be sufficient in parts in the shadows of the spacers.
A problem of insufficient alignment treatment on the alignment film in the periphery of the spacers has been described using a transverse electrical field mode liquid crystal display panel including a nematic liquid crystal material having positive dielectric anisotropy as an example, but this problem is not limited to this example. The same problem can arise in liquid crystal display panels including a nematic liquid crystal material having negative dielectric anisotropy, as well as in vertical electrical field mode liquid crystal display panels. When using a nematic liquid crystal material having negative dielectric anisotropy, the alignment orientation of the liquid crystal molecules when no electrical field is applied may be rotated 900 from the case where a nematic liquid crystal material having positive dielectric anisotropy is used. In other words, the alignment direction of the liquid crystals when no electrical field is applied may be defined as substantially parallel to the direction of the transverse electrical field (a direction orthogonal to the direction in which the slits extend) or so as to form an angle of approximately greater than 0° and less than or equal to 15° with the direction of the transverse electrical field. For example, in the example illustrated in
The alignment treatment on the alignment film can include a process for defining the alignment direction of the liquid crystal molecules when no electrical field is applied and a process for defining a pretilt angle. The “alignment direction (or alignment orientation) of the liquid crystal molecules” refers to an azimuth angle direction in the display plane, whereas the “pretilt angle” refers to an angle formed by the liquid crystal molecules with the surface of the alignment film.
The above-described problem of the display quality dropping due to insufficient alignment treatment on the alignment film in the periphery of the spacers can arise regardless of whether the spacers are main spacers or sub spacers. However, the higher the spacers are, the greater the region in the shadows of the spacers will be when carrying out the alignment treatment, which tends to make the above-described problem more likely to occur.
For such reasons, in the liquid crystal display panel 900A according to the first comparative example, the alignment of the liquid crystal molecules often becomes distorted in the regions near the spacers 950, indicated by the dotted lines in
The ability of the liquid crystal display panel 100 according to the first embodiment of the present invention to solve the above-described problems will be described with reference again to
As described above, unlike the liquid crystal display panel 900A according to the first comparative example, each of the spacers 50 provided in the display region 100d of the liquid crystal display panel 100 is disposed overlapping with a corresponding TFT 17 when viewed from the normal direction of the active matrix substrate 10. In other words, each of the spacers 50 is disposed overlapping with at least one of the source electrode 16s and the drain electrode 16d of a corresponding TFT 17 when viewed from the normal direction of the active matrix substrate 10.
In the liquid crystal display panel 100, a drop in the display quality is suppressed even in a case where an alignment treatment is carried out in the vertical direction in
Suppressing a drop in the display quality caused by insufficient alignment treatment on the alignment film in the periphery of the spacers will be described in more detail using the structure of the liquid crystal display panel 100 as an example.
The liquid crystal display panel 100 includes a plurality of pixels P, and each of the pixels P has a first domain P1 and a second domain P2 in which the slits 26as extend in different directions. An alignment restriction direction D1 defined by the first alignment film 27 forms an angle α1 of from 0° to 15° with the direction in which the slits 26as extend in the first domain P1 and an angle α2 of from 00 to 15° with the direction in which the slits 26as extend in the second domain P2. The angles α1 and α2 are typically equal. The direction in which the source bus lines S extend in each of the pixels P is substantially parallel to the direction in which the slits 26as extend. In other words, the source bus lines S extend in different directions in the first domain P1 and the second domain P2. The alignment restriction direction D1 defined by the first alignment film 27 forms the angle α1 with the direction in which the source bus lines S extend in the first domain P1 and the angle α2 with the direction in which the source bus lines S extend in the second domain P2. When viewed from the normal direction of the active matrix substrate 10, an alignment restriction direction D2 defined by the second alignment film 37 is, for example, antiparallel to the alignment restriction direction D1, as illustrated in
Although the alignment restriction direction defined by the first alignment film 27 is the same in regions corresponding to the first domain P1 and regions corresponding to the second domain P2 in the first alignment film 27, the alignment restriction direction is not limited thereto, and may be varied instead.
As illustrated in the drawings, in both the first domain P1 and the second domain P2, both end portions 26se and a central part 26sc of each of the slits 26as may form an angle of from 5° to 35° with the direction in which the slits 26as extend. This makes it possible for disorder in the alignment of the liquid crystal molecules arising when external stress is exerted on the surface of the liquid crystal display panel, e.g. when the surface of the liquid crystal display panel is pressed, to return to the normal alignment state more quickly upon the external stress being eliminated. The external stress exerted on the surface of the liquid crystal display panel sometimes acts so as to rotate the liquid crystal molecules in the direction opposite from the direction in which the liquid crystal molecules are rotated by the transverse electrical field, and thus a problem sometimes arises in which it is difficult for the liquid crystal molecules to return to the normal alignment state (i.e. the alignment state formed by the transverse electrical field) even when the external stress is eliminated. However, in a case where both end portions 26se and the central part 26sc of the slits 26as are slanted relative to the direction in which the slits 26as extend, the above-described problem is suppressed by an electrical field generated by both end portions 26se and the central part 26sc.
The following effect can also be achieved by setting both end portions 26se of the slits 26as to form an angle with the direction in which the slits 26as extend. When a voltage is applied to the electrode pairs, a transverse electrical field is produced in a direction orthogonal to the direction in which the slits 26as extend. However, edges (short sides) E of the slits 26as extend in a direction substantially orthogonal to the direction in which the slits 26as extend, and an electrical field substantially parallel to the direction in which the slits 26as extend is produced locally by the edges E. Forming both end portions 26se of the slits 26as so as to form an angle with the direction in which the slits 26as extend makes it possible to reduce the region into which the electrical field produced by the edges E extends into the slits 26as, which in turn makes it possible to suppress a drop in transmittance when a voltage is applied.
As illustrated in
Arranging the spacers 50 in this manner makes it possible to suppress a drop in the display quality caused by insufficient alignment treatment of the alignment film in the periphery of the spacers, without increasing the area of the light shielding layer 32, i.e. without reducing the aperture ratio. The positions where the spacers 50 are arranged are not limited to the above-described example, however, and may be adjusted as appropriate in consideration of the alignment restriction directions defined by the first alignment film 27 and the second alignment film 37, and the shape of the light shielding layer 32.
The spacers 50 may be provided at locations, in the display region 100d, where the height of inorganic insulating layer 23 is the greatest, for example. Here, the “height of the inorganic insulating layer 23” refers to the distance, in the normal direction of the active matrix substrate 10, from the surface of the first transparent substrate 11 closer to the liquid crystal layer 40 to the surface of the inorganic insulating layer 23 closer to the liquid crystal layer 40. The same applies to the other conductive layers or insulating layers provided on the active matrix substrate 10. Having the organic insulating layer 25 that forms the spacers 50 be thin has a benefit of making it easy to control variations in line widths, the shape of tapers, and the like in photolithography processes for patterning the organic insulating layer 25. Furthermore, in some cases, the amount of material used to form the spacers 50 can be reduced, which makes it possible to reduce manufacturing costs.
For example, the height of the inorganic insulating layer 23 at the places where the spacers 50 are provided is greater than the height of the inorganic insulating layer 23 at places where the spacers 50 are not provided but the pixel electrodes 22a and the common electrodes 26a are present.
As illustrated in
As can be seen by comparing
As described above, in the liquid crystal display panel 100, each of the spacers 50 is disposed overlapping with the source electrode 16s and the drain electrode 16d of a corresponding TFT 17 when viewed from the normal direction of the active matrix substrate 10. From the standpoint of achieving the above-described effect of suppressing a drop in the display quality caused by insufficient alignment treatment on the alignment film in the periphery of the spacers without reducing the aperture ratio, each of the spacers 50 may be disposed overlapping with at least one of the source electrode 16s and the drain electrode 16d of the corresponding TFT 17 when viewed from the normal direction of the active matrix substrate 10. Because the channel regions 14i of the semiconductor layer 14 are located between the source electrodes 16s and the drain electrodes 16d of the TFTs 17, it can also be said that the spacers 50 may be disposed overlapping with the channel regions 14i of the semiconductor layer 14 when viewed from the normal direction of the active matrix substrate 10.
Additionally, providing the spacers 50, which hold the gap between the active matrix substrate 10 and the counter substrate 30, on the active matrix substrate 10 makes it possible to suppress a problem in which the alignment film peels because of the spacers. Investigations made by the inventors of the present invention showed that spacers provided on the counter substrate can cause the alignment film provided on the active matrix substrate to partially peel under the influence of vibrations imparted on the liquid crystal display panel, forces from the exterior, and the like. In a case where the alignment film partially peels, the alignment of the liquid crystal molecules can become disordered in the portions where the alignment film has peeled, and this has been a cause of a drop in the display quality of liquid crystal display panels. Details will be given later. The liquid crystal layer 40 side of the active matrix substrate 10 is generally less flat than the liquid crystal layer 40 side of the counter substrate 30, and thus in a case where the counter substrate 30 includes the spacers 50, it is more likely that a problem in which the spacers 50 cause the first alignment film 27 to peel under vibrations, forces imparted from the exterior, and the like will arise. However, in the liquid crystal display panel 100, the active matrix substrate 10 includes the spacers 50, which makes it difficult for a problem to arise in which the spacers 50 cause the second alignment film 37 of the counter substrate 30 to partially peel.
Furthermore, providing the spacers 50, which hold the gap between the active matrix substrate 10 and the counter substrate 30, on the active matrix substrate 10 makes it possible to suppress unevenness in the cell gap. Even in a case where, during the step of manufacturing the active matrix substrate 10, the film thicknesses have become uneven in the steps leading up to the step of providing the spacers 50, making the heights from the first transparent substrate 11 to the spacers 50 (and more specifically, the heights, in the normal direction of the active matrix substrate 10, from the surface of the common electrodes 26a closer to the liquid crystal layer 40 to the surfaces of the spacers 50 closer to the liquid crystal layer 40) even compensates for such unevenness and makes it possible to ensure that the cell gap is constant.
In a case where the spacers 50 are provided on the counter substrate 30, there is a problem in that the aperture ratio can drop in order to control the cell gap. The liquid crystal layer 40 side of the active matrix substrate 10 is generally less flat than the liquid crystal layer 40 side of the counter substrate 30, and thus the surface area over which the spacers 50 contact the active matrix substrate 10 may become smaller than the cross-sectional area of the spacers 50 as viewed from the normal direction of the active matrix substrate 10 (in a case where the spacers 50 have a tapered shape, the area of the surfaces of the spacers closer to the liquid crystal layer 40). Therefore, in light of alignment skew between the active matrix substrate 10 and the counter substrate 30 (e.g. less than or equal to approximately 5 μm), it may be necessary to increase the surface area of the spacers 50 or increase the number of spacers 50 provided. Such a problem can be suppressed when the spacers 50 are provided on the active matrix substrate 10, and thus the cell gap can be controlled without reducing the aperture ratio.
As described above, the liquid crystal display panel 100 includes the TFTs 17, which are bottom-gate TFTs, for example. In a liquid crystal display panel including bottom-gate TFTs, a light shielding layer is typically provided covering the active layers of the TFTs, and thus such a panel can be used favorably for the object of the present invention, namely to suppress a drop in the display quality caused by disorder in the alignment of the liquid crystal molecules near the spacers without causing a drop in the aperture ratio of the liquid crystal display panel. However, the liquid crystal display panel according to embodiments of the present invention is not limited to the structure illustrated here, and may instead include top-gate TFTs, for example. In other words, the arrangement relationship of the gate metal layer 12 and the source metal layer 16 may be reversed.
Preferably, the plurality of spacers 50 are located on an inner side of a pattern provided in the gate metal layer 12, e.g. the gate electrodes 12g, when viewed from the normal direction of the active matrix substrate 10. This is because when patterning an organic insulating film using a photolithography process during the step of forming the organic insulating layer 25, in a case where the pattern includes a mixture of places where a metal layer (a reflective layer) is provided under the organic insulating film and places where such a metal layer is not provided, the exposure time required to achieve the desired spacer shape may vary. From the standpoint of preventing variations in the shapes of the spacers 50, it is preferable that the plurality of spacers 50 be located on an inner side of the pattern provided in the gate metal layer 12, e.g. the gate electrodes 12g, when viewed from the normal direction of the active matrix substrate 10. In other words, it is sufficient that the spacers 50 all overlap with the gate metal layer 12 and/or the source metal layer 16 when viewed from the normal direction of the active matrix substrate 10. That is, it is sufficient that the spacers 50 be on inner sides of the pattern provided in the gate metal layer 12 (e.g. the gate electrodes 12g) and/or the pattern provided in the source metal layer 16 (e.g. the source electrodes 16s, the drain electrodes 16d) when viewed from the normal direction of the active matrix substrate 10. To put it differently, it is sufficient that the spacers 50 be formed so as not to protrude from the pattern provided in the gate metal layer 12 and/or the pattern provided in the source metal layer 16.
As described above, each of the spacers 50 includes a part of the organic insulating layer 25. In other words, the spacers 50 are formed from the same organic insulating film as the organic insulating layer 25, and thus the spacers 50 can be formed without increasing the steps in the manufacturing process. The spacers 50 do not overlap with the second transparent conductive layer 26 when viewed from the normal direction of the active matrix substrate 10.
Preferably, part of the organic insulating layer 25 is formed on the source bus lines S. In other words, as illustrated in
An organic insulating material generally tends to have a lower relative dielectric constant than an inorganic insulating material. Accordingly, providing the organic insulating layer 25 between the source bus lines S and the common electrodes 26a in addition to the inorganic insulating layer 23 formed from an inorganic insulating material makes it possible to reduce the capacitance value of capacitance formed therebetween. Alternatively, the thickness of the insulating layers required to achieve the effect of reducing the capacitance between the source bus lines S and the common electrodes 26a can be reduced. This makes it possible to suppress disorder in the alignment of the liquid crystal molecules near the source bus lines S, for example. Additionally, providing part of the organic insulating layer 25 between the source bus lines S and the common electrodes 26a makes it possible to effectively maintain the insulated state between the source bus lines S and the common electrodes 26a (reduce leak current arising between the source bus lines S and the common electrodes 26a) even in a case where flaws such as pinholes or cracks arise in the inorganic insulating layer 23 between the source bus lines S and the common electrodes 26a.
From the standpoint of achieving the above-described effects of reducing the source bus line load and reducing leak current between the source bus lines S and the common electrodes 26a, it is preferable that a width w25 of a part of the organic insulating layer 25 formed substantially parallel to the source bus lines S and covering at least part of the source bus lines S be designed to be wider than a width w16 of the source bus lines S, e.g. approximately 4 μm wider. This value can be adjusted as appropriate in consideration of line width variations during the photolithography process, the alignment precision of the patterning of the organic insulating layer 25 with respect to the source bus lines S (e.g. approximately ±1 μm), and the like.
The source bus lines S need not be entirely covered by the organic insulating layer 25. The plurality of source bus lines S may include parts not covered by the organic insulating layer 25. In a case where the area of the parts of the source bus lines S not covered by the organic insulating layer 25 increases, the above-described effects of reducing the source bus line load and suppressing leak current between the source bus lines S and the common electrodes 26a can decrease. However, this can suppress disorder in the alignment of the liquid crystal molecules near the source bus lines S due to an increased thickness in the layered structure above the source bus lines S. As such, the area of the parts of the source bus lines S not covered by the organic insulating layer 25 may be set as appropriate in consideration of the drive capability of the source driver, the number of pixels, the resolution, and the like.
Preferably, part of the second transparent conductive layer 26 is formed on the organic insulating layer 25. As illustrated in
On the other hand, it is preferable that the layered structure not include the organic insulating layer 25 in each of the pixel openings, as illustrated in
A method for manufacturing the liquid crystal display panel 100 will be described next.
First, the gate metal layer (first metal layer) 12 including the gate electrodes 12g and the gate bus lines G is formed on the first transparent substrate (e.g. a glass substrate) 11. Specifically, the first metal layer 12 is formed by depositing a first conductive film on the first transparent substrate 11 and then patterning the first conductive film. For example, aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy thereof can be used as the material of the first conductive film. The first conductive film may have a single-layer structure, or may have a layered structure in which a plurality of layers are layered. For example, a Ti/Al/Ti (upper layer/intermediate layer/lower layer) layered body or a Mo/Al/Mo layered body can be used. The layered structure of the first conductive film is not limited to a three-layer structure, and may be a layered structure having two layers or four or more layers. Furthermore, it is sufficient that the first conductive film include at least a layer formed from a metal material, and in a case where the first conductive film has a layered structure, some of the layers may be formed from a metal nitride or a metal oxide. Here, a 30 nm-thick Ti layer, a 200 nm-thick Al layer, and a 100 nm-thick Ti layer are deposited in sequence through sputtering, for example, to form the first conductive film, and the first conductive film is then patterned through a photolithography process to form the first metal layer 12. A known photolithography process can be used. More specifically, a photoresist is applied on the first conductive film and is then patterned by exposing the photoresist using a photomask having a desired pattern and developing the photoresist. The first metal layer 12 having a desired pattern is formed on the first transparent substrate by etching the first conductive film using the resist pattern as an etching mask. Finally, the photoresist is removed.
As illustrated in
Next, the gate insulating layer 13 is formed on the first metal layer 12. The gate insulating layer 13 is, for example, a silicon dioxide (SiO2) film, a silicon nitride (SiNx) film, a silicon oxide nitride (SiOxNy (x>y)) film, a silicon nitride oxide (SiNxOy (x>y)) film, an aluminum oxide film, a tantalum oxide film, or a layered film thereof. Here, the gate insulating layer 13 is formed by depositing a 410 nm-thick SiNx film through Chemical Vapor Deposition (CVD), for example.
Next, as illustrated in
The semiconductor layer 14, the source metal layer (second metal layer) 16, and the first transparent conductive layer 22 can be formed using two photomasks through the following step. Specifically, first, a semiconductor film is deposited on the gate insulating layer 13. Then, without patterning the semiconductor film, a second conductive film is deposited on the semiconductor film. The semiconductor film and the second conductive film are then patterned through a photolithography process using the same photomask. Next, a first transparent conductive film is deposited on the semiconductor film and the second conductive film. The first transparent conductive film is formed so as to contact the second conductive film directly. Then, the semiconductor layer 14, the source metal layer (second metal layer) 16, and the first transparent conductive layer 22 are formed by patterning the second conductive film and the first transparent conductive film through a photolithography process. In a case where the semiconductor layer 14 has a layered structure including an intrinsic semiconductor layer and an impurity-doped semiconductor layer, a step of removing the impurity-doped semiconductor film from the channel regions may furthermore be carried out.
Here, a 130 nm-thick amorphous Si film and a 40 nm-thick phosphorous-doped n+ amorphous Si film are deposited in sequence through Chemical Vapor Deposition (CVD), for example. These semiconductor films may be deposited in sequence with the above-described SiNx film. Then, the second conductive film is formed on the amorphous Si film and the n+ amorphous Si film, without patterning the semiconductor films. Here, the second conductive film is formed by depositing a 200 nm-thick MoNb film through sputtering, for example. The semiconductor film and the second conductive film are then patterned through a photolithography process using the same photomask. As a result, the amorphous Si film, the n+ amorphous Si film, and the second conductive film are formed having substantially the same pattern shape. The pattern shapes of the amorphous Si film, the n+ amorphous Si film, and the second conductive film are at this time the same as the shape of an amorphous silicon film included in the semiconductor layer 14, and are the same as the shape of the semiconductor layer 14 illustrated in
Next, the first transparent conductive film is deposited on the patterned amorphous Si film, n+ amorphous Si film, and second conductive film. Here, the first transparent conductive film is formed by depositing a 65 nm-thick IZO film through sputtering, for example. The n+ amorphous Si film, the second conductive film, and the first transparent conductive film are then patterned through a photolithography process. In the photolithography process, first, a photoresist is applied on the first transparent conductive film, and the photoresist is then exposed using a photomask and developed to pattern the photoresist. The photoresist is patterned so as to be provided on the portions where the pixel electrodes 22a are formed and the portions where the second metal layer 16 is formed (portions aside from the channel regions 14i). The first transparent conductive film and the second conductive film are patterned through wet etching using the resist pattern as an etching mask. The second metal layer 16 including the source electrodes 16s, the drain electrodes 16d, and the source bus lines S, and the first transparent conductive layer 22 including the first transparent electrodes 22a, are obtained from this patterning. Then, the n+ amorphous Si film in the channel regions 14i is removed through dry etching using the same resist pattern as an etching mask. The semiconductor layer 14 including the channel regions 14i is obtained from this dry etching. The semiconductor layer 14, the second metal layer 16, and the first transparent conductive layer 22 are formed in this manner.
Manufacturing the semiconductor layer 14, the second metal layer 16, and the first transparent conductive layer 22 through the above-described step results in the second metal layer 16 and the first transparent conductive layer 22 having substantially the same pattern shape, aside from the pixel electrodes 22a. When viewed from the normal direction of the first transparent substrate 11, the first transparent conductive layer 22 is formed on the second metal layer 16, and the second metal layer 16 and the first transparent conductive layer 22 are in direct contact, in the regions where the second metal layer 16 is formed. The drain electrodes 16d are island-shaped, for example. Additionally, the semiconductor layer 14 has a layered structure including an intrinsic semiconductor layer and an impurity-doped semiconductor layer, whereas the channel regions 14i do not have the impurity-doped semiconductor layer. When viewed from the normal direction of the active matrix substrate 10, in the regions where the source bus lines S are formed, the semiconductor layer 14 (including the intrinsic semiconductor layer and the impurity-doped semiconductor layer) is formed under the source bus lines S, and the source bus lines S and the semiconductor layer 14 (the impurity-doped semiconductor layer) are in direct contact. When viewed from the normal direction of the active matrix substrate 10, in the regions where the source bus lines S are formed, the first transparent conductive layer 22 is formed on the source bus lines S, and the source bus lines S and the first transparent conductive layer 22 are in direct contact. The parts of the semiconductor layer 14 (the intrinsic semiconductor layer and the impurity-doped semiconductor layer) and the first transparent conductive layer 22 in direct contact with the source bus lines S function as source bus lines.
In the step of removing the n+ amorphous Si film in the channel regions 14i through dry etching, the surface of the amorphous Si film in the channel regions 14i can also be etched. Accordingly, it is preferable that the thickness of the amorphous Si film deposited in the step of depositing the amorphous Si film be greater than the thickness of the amorphous Si film removed in the step of removing the n+ amorphous Si film in the channel regions 14i through dry etching. Preferably, the thickness of the amorphous Si film deposited in the step of depositing the amorphous Si film is greater than the thickness of the n+ amorphous Si film deposited in the step of depositing the n+ amorphous Si film.
For example, aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy thereof can be used as the material of the second conductive film. The second conductive film may have a single-layer structure, or may have a layered structure in which a plurality of layers are layered. For example, a Ti/Al/Ti (upper layer/intermediate layer/lower layer) layered body or a Mo/Al/Mo layered body can be used. The layered structure of the second conductive film is not limited to a three-layer structure, and may be a layered structure having two layers or four or more layers. Furthermore, it is sufficient that the second conductive film include at least a layer formed from a metal material, and in a case where the second conductive film has a layered structure, some of the layers may be formed from a metal nitride or a metal oxide. An Al film or an Al alloy film may further be formed as a lower layer of the MoNb film described as an example of the second conductive film. By further forming an Al film or an Al alloy film as a lower layer of the MoNb film, the resistance of the second metal layer 16 can be reduced.
Various types of transparent conductive materials can be used as the material of the first transparent conductive film, and for example, a metal oxide such as ITO, IZO, or ZnO can be used.
Next, the inorganic insulating layer 23 is formed on the semiconductor layer 14, the second metal layer 16, and the first transparent conductive layer 22. The inorganic insulating layer 23 is, for example, a silicon dioxide (SiO2) film, a silicon nitride (SiNx) film, a silicon oxide nitride (SiOxNy (x>y)) film, a silicon nitride oxide (SiNxOy (x>y)) film, an aluminum oxide film, a tantalum oxide film, or a layered film thereof. Here, a 250 nm-thick SiNx film is deposited through Chemical Vapor Deposition (CVD), for example. Openings are formed through patterning in the inorganic insulating layer 23, for example in regions of the non-display region 100f corresponding to contact portions for electrically connecting the first metal layer 12 and the second metal layer 16. The inorganic insulating layer 23 need not have openings in the display region 100d.
Next, the organic insulating layer 25 is formed on the inorganic insulating layer 23, as illustrated in
Next, the second transparent conductive layer 26 is formed on the organic insulating layer 25, as illustrated in
The first alignment film 27 and the second alignment film 37 are formed on the surfaces of the active matrix substrate 10 formed in this manner and the separately-prepared counter substrate 30. The counter substrate 30 can be manufactured through a variety of known methods. A sealing material is then added, using, for example, a dispenser method or a screen printing method, so as to enclose the region of the active matrix substrate 10 or the counter substrate 30 corresponding to the display region 100d. The liquid crystal layer 40 is formed by dripping a liquid crystal material through a dripping method onto the substrate provided with the sealing material. After the active matrix substrate 10 and the counter substrate 30 are affixed in a vacuum, the sealing material is cured by being irradiated with ultraviolet light, for example.
The liquid crystal display panel 100 can be manufactured through this step.
The liquid crystal display panel and the method for manufacturing the liquid crystal display panel according to the present embodiment are not limited to the examples described above.
For example, in the above-described manufacturing step, the semiconductor layer 14, the source metal layer (second metal layer) 16, and the first transparent conductive layer 22 are formed using two photomasks. Specifically, after the semiconductor film is deposited on the gate insulating layer 13, the second conductive film is deposited on the semiconductor film without patterning the semiconductor film. However, the semiconductor layer 14, the source metal layer (second metal layer) 16, and the first transparent conductive layer 22 may be formed using three photomasks. Specifically, the semiconductor film deposited on the gate insulating layer 13 may be patterned, after which the second conductive film may be deposited on the semiconductor film. Here, a 130 nm-thick amorphous Si film and a 40 nm-thick phosphorous-doped n+ amorphous Si film may be deposited in sequence through Chemical Vapor Deposition (CVD), for example, after which an intrinsic semiconductor film and an impurity-doped semiconductor film may be patterned through a photolithography process. The shape of the pattern of the amorphous Si film at this time is the same as the shape of the amorphous silicon layer included in the semiconductor layer 14.
According to this manufacturing method, a liquid crystal display panel having an island-shaped semiconductor layer 14 can be manufactured. In other words, when viewed from the normal direction of the first transparent substrate 11, the semiconductor layer 14 (including the intrinsic semiconductor layer and the impurity-doped semiconductor layer) is not formed under the source bus lines S, and thus the thickness of the layered structure can be reduced in the regions where the source bus lines S are formed. Accordingly, the difference between the height of the common electrodes 26a above the source bus lines S and the height of the common electrodes 26a at the pixel openings can be reduced, which makes it possible to suppress disorder in the alignment of the liquid crystal molecules caused by steps near the source bus lines S, for example.
The TFTs 17 may be a known TFT such as an amorphous silicon TFT (a-Si TFT), a polysilicon TFT (p-Si TFT), or a microcrystalline silicon TFT (μC-Si TFT), and a TFT having an oxide semiconductor layer (an oxide TFT) may be used. The semiconductor layer 14 need not include an impurity-doped semiconductor layer. The semiconductor layer 14 also need not have a layered structure. In a case where the TFTs 17 are amorphous silicon TFTs as described above, it is preferable that the semiconductor layer 14 have a layered structure including an amorphous Si layer and an n+ amorphous Si layer, but in a case where the TFTs 17 are oxide TFTs, for example, the semiconductor layer 14 may have a single-layer structure of an oxide semiconductor layer. In a case where the semiconductor layer 14 has a single-layer structure, the semiconductor layer 14 may, for example, have the same pattern shape as the source metal layer 16 with the exception of the channel regions 14i. In this case, the semiconductor layer 14 and the source metal layer (second metal layer) 16 can be formed using a single photomask by using a gray scale mask. In other words, the semiconductor film and the second conductive film may be patterned through photolithography processes using the same photomask, after which the second conductive film may be removed from the channel regions.
The semiconductor layer 14 may contain an oxide semiconductor. The semiconductor layer 14 may be an oxide semiconductor layer.
The oxide semiconductor contained in the oxide semiconductor layer may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline part. A polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface can be given as examples of the crystalline oxide semiconductor.
The oxide semiconductor layer may have a layered structure of two or more layers. In a case where the oxide semiconductor layer has a layered structure, the oxide semiconductor layer may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, the oxide semiconductor layer may include a plurality of crystalline oxide semiconductor layers having different crystal structures. In addition, the oxide semiconductor layer may include a plurality of amorphous oxide semiconductor layers. In a case where the oxide semiconductor layer has a two-layer structure including an upper layer and a lower layer, the energy gap of the oxide semiconductor included in the upper layer is preferably greater than the energy gap of the oxide semiconductor included in the lower layer. However, in the case where the difference in the energy gap between these layers is comparatively small, the energy gap of the lower-layer oxide semiconductor may be greater than the energy gap of the upper-layer oxide semiconductor.
JP 2014-007399 A, for example, describes a material, a structure, and a film formation method of the amorphous oxide semiconductor and each of the above-described crystalline oxide semiconductors, a configuration of an oxide semiconductor layer having a layered structure, and the like. The entire contents of JP 2014-007399 A are incorporated into the present specification by reference.
The oxide semiconductor layer may contain at least one metal element selected from In, Ga, and Zn, for example. In the present embodiment, the oxide semiconductor layer contains, for example, an In—Ga—Zn—O semiconductor (e.g. indium gallium zinc oxide). Here, the In—Ga—Zn—O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc); the ratio of In, Ga, and Zn (the composition ratio) is not particularly limited to a specific ratio, and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, and the like. Such an oxide semiconductor layer can be formed from an oxide semiconductor film containing an In—Ga—Zn—O semiconductor. Note that a channel-etched type TFT having an active layer containing an oxide semiconductor such as an In—Ga—Zn—O semiconductor may be called a “CE-OS-TFT”.
The In—Ga—Zn—O semiconductor may be amorphous or crystalline. For a crystalline In—Ga—Zn—O semiconductor, a crystalline In—Ga—Zn—O semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
Note that the above-described JP 2014-007399 A, JP 2012-134475 A, and JP 2014-209727 A, for example, disclose crystal structures of crystalline In—Ga—Zn—O semiconductors. The entire contents of JP 2012-134475 A and JP 2014-209727 A are incorporated into the present specification by reference. A TFT having an In—Ga—Zn—O semiconductor layer has a high mobility (greater than 20 times that of an a-Si TFT) and a low leak current (less than 1/100th that of an a-Si TFT), and thus can be used favorably as a driving TFT (for example, a TFT included in a drive circuit provided on the same substrate as a display region including a plurality of pixels, in the periphery of the display region) and a pixel TFT (a TFT provided in a pixel).
The oxide semiconductor layer may contain another oxide semiconductor instead of an In—Ga—Zn—O semiconductor. For example, the oxide semiconductor layer may contain an In—Sn—Zn—O semiconductor (e.g. In2O3—SnO2—ZnO; InSnZnO). The In—Sn—Zn—O semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may contain an In—Al—Zn—O semiconductor, an In—Al—Sn—Zn—O semiconductor, a Zn—O semiconductor, an In—Zn—O semiconductor, a Zn—Ti—O semiconductor, a Cd—Ge—O semiconductor, a Cd—Pb—O semiconductor, CdO (cadmium oxide), a Mg—Zn—O semiconductor, an In—Ga—Sn—O semiconductor, an In—Ga—O semiconductor, a Zr—In—Zn—O semiconductor, a Hf—In—Zn—O semiconductor, an Al—Ga—Zn—O semiconductor, a Ga—Zn—O semiconductor, or the like.
The TFTs 17 are not limited to the channel-etched TFTs described here. The TFTs 17 may be etch-stop TFTs. With “channel-etched TFTs”, an etching stop layer is not formed above the channel regions, and lower faces of the end portions of the source and drain electrodes closer to the channel are arranged to be in contact with the upper face of the semiconductor layer, as illustrated in
A variation on the liquid crystal display panel according to the present embodiment will be described next.
In the liquid crystal display panel 100A, the area of the openings 32o in the light shielding layer 32 is greater than that in the liquid crystal display panel 100. In other words, the liquid crystal display panel 100A has a greater pixel aperture ratio than that of the liquid crystal display panel 100. For example, the pixel aperture ratio of the liquid crystal display panel 100A is approximately 28% greater than the pixel aperture ratio of the liquid crystal display panel 100. For example, in the liquid crystal display panel 100, a width w32b of the second portions 32b of the light shielding layer 32 that cover the gate bus lines G is 53.5 μm, whereas in the liquid crystal display panel 100A, the width w32b of the second portions 32b of the light shielding layer 32 is 20 μm.
The liquid crystal display panel 100A also differs from the liquid crystal display panel 100 in terms of the shapes of the gate electrodes 12g, the source electrodes 16s, and the drain electrodes 16d. This, too, makes it possible to achieve a greater area for the openings 32o in the light shielding layer 32 than that in the liquid crystal display panel 100. Additionally, by providing drain lead-out wiring lines 16de for connecting the drain electrodes 16d to the pixel electrodes 22a so that the drain lead-out wiring lines 16de overlap with end portions of the slits 26as in the common electrodes 26a, disorder in the alignment of the liquid crystal molecules caused by the electrical field from the gate bus lines G can be suppressed, and thus a drop in the display quality can be effectively prevented.
The liquid crystal display panel 100A having this configuration can achieve effects similar to those of the liquid crystal display panel 100.
As illustrated in
With the liquid crystal display panel 200, a drop in the display quality caused by insufficient alignment treatment of the alignment film in the periphery of the spacers can be suppressed, without increasing the area of the light shielding layer 32, i.e. without reducing the aperture ratio.
Additionally, with the liquid crystal display panel 200, a situation in which the projection-shaped structures 39 provided on the counter substrate 30 cause the first alignment film 27 provided on the active matrix substrate 10 to partially peel under the influence of vibrations imparted on the liquid crystal display panel, forces from the exterior, and the like, resulting in a drop in the display quality, can be suppressed. This effect will be described in more detail hereinafter with reference to
In the liquid crystal display panel 900B according to the second comparative example, insufficient alignment treatment of the alignment film in the periphery of the spacers was found to be one cause of a drop in the display quality near the spacers 950 (the regions indicated by dotted lines in
Partial peeling-off of the alignment film, caused by vibrations or external forces imparted on the liquid crystal display panel 900B according to the second comparative example, was found to be another cause. Specifically, the first alignment film 27 provided on the active matrix substrate 10 may partially peel under the influence of vibrations or forces, due to the spacers 950 provided on the counter substrate 30. In a case where the alignment film partially peels, the alignment of the liquid crystal molecules may become disordered at the locations where the alignment film has peeled. The alignment of the liquid crystal molecules has also become disordered by alignment film pieces peeled from the alignment film intermixing with the liquid crystal layer. In a case where the parts where the alignment of the liquid crystal molecules is disordered are not covered by a light shielding layer (black matrix), a drop in the display quality, such as the display becoming grainy, may result.
The effects of vibrations are prominent in liquid crystal display panels installed in vehicles such as automobiles and aircraft, for example. Furthermore, in a liquid crystal display panel that incorporates a touch panel or a digitizer, forces exerted by a user's finger or an input pen (including, for example, a stylus or a digitizer pen) touching the panel are also thought to have an effect. Touch panels include external types (where a polarizing plate is arranged on an observer side, and a touch panel is arranged closer to the observer than the polarizing plate), on-cell types, and in-cell types. (On-cell and in-cell types may be collectively referred to as “built-in types”.) Of these, the problem of the alignment film peeling arises easily in on-cell and in-cell touch panels. The same problem arises easily in external types as well, in a case where the configuration provides no air gap between the display panel and the touch panel. Here, “cell” refers to a display cell (called “display panel” hereinafter). For example, a liquid crystal display panel includes a pair of substrates (e.g. an active matrix substrate and a counter substrate) facing each other with a liquid crystal layer therebetween, but does not include a polarizing plate. “On-cell” refers to a panel in which a layer providing touch panel functionality is present between a polarizing plate and the counter substrate of the liquid crystal display panel, whereas “in-cell” refers to a panel in which a layer providing touch panel functionality is present on the liquid crystal layer side of the counter substrate or on the active matrix substrate in the liquid crystal display panel.
Generally, spacers are provided so as to overlap with a light shielding layer (black matrix) provided on the counter substrate. As such, even in a case where the alignment film partially peels, the display quality will not drop as long as the places where the alignment of the liquid crystal molecules has become disordered overlap with the light shielding layer (black matrix). However, in a case where, for example, the positions of active matrix substrate 10 and the counter substrate 30 become skewed or the substrates warp (even temporarily) under the influence of the above-described vibrations or forces from the exterior, the places where the alignment film has peeled are more likely to extend to the periphery of the locations where the spacers 950 are provided. The display quality may drop in a case where the places where the alignment film has peeled and the alignment of the liquid crystal molecules has become disordered extend to locations aside from where the light shielding layer (black matrix) is provided, as illustrated in
It was also found that the problem of the first alignment film 27 peeling in the periphery of the places where the spacers 950 are provided arises easily in a case where, as illustrated in
The problem of the alignment film partially peeling under vibrations or forces applied from the exterior can arise in both vertical electrical field mode and transverse electrical field mode liquid crystal display panels, and can arise regardless of the liquid crystal material contained in the liquid crystal layer and the alignment treatment method for the alignment film.
For such reasons, in the liquid crystal display panel 900B according to the second comparative example, the alignment of the liquid crystal molecules often becomes distorted in the regions near the spacers 950, indicated by the dotted lines in
The ability of the liquid crystal display panel 200 according to the second embodiment of the present invention to solve the above-described problems, particularly the problem of the display quality dropping due to the alignment film partially peeling under vibrations or forces applied from the exterior, will be described with reference again to
Unlike the liquid crystal display panel 900B according to the second comparative example, each of the spacers 50 provided in the display region of the liquid crystal display panel 200 is arranged, when viewed from the normal direction of the active matrix substrate 10, overlapping with at least one of the source electrode 16s and the drain electrode 16d of a corresponding TFT 17. In other words, each of the spacers 50 is disposed overlapping with at least one of the source electrode 16s and the drain electrode 16d of a corresponding TFT 17 when viewed from the normal direction of the active matrix substrate 10.
As can be seen by comparing
As can be seen by comparing
The spacers 950 in the liquid crystal display panel 900B according to the second comparative example are the projection-shaped structures 39 provided on the counter substrate 30, and do not include the organic insulating layer 25. However, the spacers 50 in the liquid crystal display panel 200 include part of the organic insulating layer 25 and the projection-shaped structures 39, and thus the height of the projection-shaped structures 39 can be kept lower in the liquid crystal display panel 200 than in the liquid crystal display panel 900B according to the second comparative example. A difference Δ2 between the height of the spacers 50 and the height of the spacers 950 (see
The spacers 50 in the liquid crystal display panel 200 have the sum of the thickness of the organic insulating layer 25 and the height of the projection-shaped structures 39, and thus hold a gap between the active matrix substrate 10 and the counter substrate 30. The problem of the first alignment film 27 peeling in the periphery of the spacers 50 due to the projection-shaped structures 39 when the organic insulating layer 25 is made thicker can be more effectively suppressed. This is because the problem of the first alignment film 27 peeling in the periphery of the spacers 50 due to the projection-shaped structures 39 can be more effectively suppressed in a case where there is a large difference in the height of the layered structure provided on the first transparent substrate 11 between where the spacers 50 are provided and the periphery of the spacers 50 (e.g. Δ2 or Δ3 indicated in
In the process of manufacturing the liquid crystal display panel 200, it is not necessary to use a gray scale mask when forming the organic insulating layer 25. The projection-shaped structures 39 are formed before the second alignment film 37 is formed on the surface of the counter substrate 30. Specifically, the projection-shaped structures 39 are formed by depositing an organic insulating film on the second transparent substrate 31 and then patterning the organic insulating film. A negative-working or positive-working photosensitive resin (photoresist) can be used as the material of the organic insulating film, for example.
A variation on the liquid crystal display panel according to the present embodiment will be described next.
The liquid crystal display panel 200A differs from the liquid crystal display panel 200 in terms of the portions of the source bus lines S not covered by the organic insulating layer 25. Of the source bus lines S, portions near the spacers 50 are not covered by the organic insulating layer 25. There is a large difference in the heights of the layered structure provided on the first transparent substrate 11, between the portions of the region in which the source bus lines S are formed that are not covered by the organic insulating layer 25 and the places where the spacers are provided. As such, in the liquid crystal display panel 200A, the problem can be effectively suppressed in which the first alignment film 27 peels in the periphery of the spacers 50 due to the projection-shaped structures 39.
Providing portions of the source bus lines S not covered by the organic insulating layer 25 also makes it possible to achieve the following effects. For example, when washing the active matrix substrate 10 before forming the first alignment film 27, a situation where washing fluid accumulates in specific locations can be suppressed. Furthermore, when forming the first alignment film 27 through a dripping method, it is easier for the alignment film to spread evenly, which makes it possible to suppress unevenness in the application of the alignment film.
The portions of the source bus lines S that are not covered by the organic insulating layer 25 have a length w25s in the y-axis direction of 10 μm, for example. As described earlier, in a case where the area of the portions of the source bus lines S not covered by the organic insulating layer 25 increases, the above-described effects of reducing the source bus line load and suppressing leak current between the source bus lines S and the common electrodes 26a can decrease. As such, the length w25s of the portions of the source bus lines S not covered by the organic insulating layer 25 may be set as appropriate in consideration of the drive capability of the source driver, the number of pixels, the resolution, and the like.
The portions of the source bus lines S not covered by the organic insulating layer 25 are not limited to the example illustrated in
The liquid crystal display panel 200A having this configuration can achieve effects similar to those of the liquid crystal display panel 200.
The spacers 50 in the liquid crystal display panel 200B include first spacers 51 and second spacers 52, which have different heights. In the liquid crystal display panel 200B, the first spacers 51 and the second spacers 52 are formed by varying the thicknesses of the parts of the organic insulating layer 25 that constitute the spacers 50. Each of the first spacers 51 includes a part 25a of the organic insulating layer 25 and the projection-shaped structure 39, and each of the second spacers 52 includes a part 25b of the organic insulating layer 25 and the projection-shaped structure 39. The parts 25a and 25b of the organic insulating layer 25 that constitute the first spacers 51 and the second spacers 52, respectively, have different thicknesses. The heights of the projection-shaped structures 39 constituting the first spacers 51 and the second spacers 52 are the same.
The configuration is not limited to that illustrated here, and the first spacers 51 and second spacers 52 may be formed by varying the heights of the projection-shaped structures 39 while keeping the thickness of the organic insulating layer 25 in the first spacers 51 and second spacers 52 the same.
The liquid crystal display panel 200B having this configuration can achieve effects similar to those of the liquid crystal display panel 200.
In the liquid crystal display panel 200C, the area of the openings 32o in the light shielding layer 32 is greater than in the liquid crystal display panel 200. In other words, the liquid crystal display panel 200C has a greater pixel aperture ratio than that of the liquid crystal display panel 200. The light shielding layer (black matrix) 32 of the liquid crystal display panel 200C may be the same as that of the liquid crystal display panel 100A illustrated in
The liquid crystal display panel 200C also differs from the liquid crystal display panel 200 in terms of the shapes of the gate electrodes 12g, the source electrodes 16s, and the drain electrodes 16d. This, too, makes it possible to achieve a greater area for the openings 32o in the light shielding layer 32 than that of the liquid crystal display panel 200. Additionally, by providing drain lead-out wiring lines 16de for connecting the drain electrodes 16d to the pixel electrodes 22a so that the drain lead-out wiring lines 16de overlap with end portions of the slits 26as in the common electrodes 26a, disorder in the alignment of the liquid crystal molecules caused by the electrical field from the gate bus lines G can be suppressed, and thus a drop in the display quality can be effectively prevented.
The liquid crystal display panel 200C having this configuration can achieve effects similar to those of the liquid crystal display panel 200.
As illustrated in
With the liquid crystal display panel 300, a drop in the display quality caused by insufficient alignment treatment on the alignment film in the periphery of the spacers can be suppressed, without increasing the area of the light shielding layer 32, i.e. without reducing the aperture ratio.
In particular, when the liquid crystal layer 40 contains a nematic liquid crystal material having positive dielectric anisotropy, an alignment treatment is carried out in the horizontal direction in
Variations on the liquid crystal display panel according to the present embodiment will be described next.
In the liquid crystal display panel 300A, the surface area of the openings 32o in the light shielding layer 32 is greater than in the liquid crystal display panel 300. In other words, the liquid crystal display panel 300A has a greater pixel aperture ratio than that of the liquid crystal display panel 300. For example, the pixel aperture ratio of the liquid crystal display panel 300A is approximately 44% greater than the pixel aperture ratio of the liquid crystal display panel 300. For example, in the liquid crystal display panel 300, the width w32b of the second portions 32b of the light shielding layer 32 that cover the gate bus lines G is 53.5 μm, whereas in the liquid crystal display panel 300A, the width w32b of the second portions 32b of the light shielding layer 32 is 20 μm. Additionally, although the light shielding layer 32 is present between the first domain P1 and the second domain P2 of each pixel P in the liquid crystal display panel 300, such is not the case in the liquid crystal display panel 300A.
The liquid crystal display panel 300A also differs from the liquid crystal display panel 300 in terms of the shapes of the gate electrodes 12g, the source electrodes 16s, and the drain electrodes 16d. This, too, makes it possible to achieve a greater area for the openings 32o in the light shielding layer 32 than that of the liquid crystal display panel 300. Additionally, by providing drain lead-out wiring lines 16de for connecting the drain electrodes 16d to the pixel electrodes 22a so that the drain lead-out wiring lines 16de overlap with end portions of the slits 26as in the common electrodes 26a, disorder in the alignment of the liquid crystal molecules caused by the electrical field from the gate bus lines G can be suppressed, and thus a drop in the display quality can be effectively prevented.
The liquid crystal display panel 300A having this configuration can achieve effects similar to those of the liquid crystal display panel 300.
The liquid crystal display panel 300B differs from the liquid crystal display panel 300A in terms of the configuration of the spacers 50. Each of the plurality of spacers 50 in the liquid crystal display panel 300B includes part of the organic insulating layer 25 and the projection-shaped structure 39, as in the second embodiment. The spacers 50 of the liquid crystal display panel 300B may be the same as in the second embodiment.
The liquid crystal display panel 300B having this configuration can achieve effects similar to those of the liquid crystal display panel 300. Furthermore, in the liquid crystal display panel 300B, a drop in the display quality caused by the alignment film partially peeling in the periphery of the spacers, without reducing the aperture ratio, can be suppressed.
The liquid crystal display panel 400 differs from the liquid crystal display panel 100 in that the liquid crystal display panel 400 is a CPA mode liquid crystal display panel. In the liquid crystal display panel 400, the second transparent electrodes 26a function as pixel electrodes. Each pixel electrode 26a is electrically connected to a corresponding drain electrode 16d through a contact hole CH provided in the inorganic insulating layer 23. The counter substrate 30 includes counter electrodes 36 provided facing the pixel electrodes 26a. The counter electrodes 36 are formed from a transparent conductive material (e.g. ITO). The pixel electrodes 26a are provided individually for each pixel. However, the counter electrodes 36 are conductive films that, for example, continue along the vertical direction in
The liquid crystal layer 40 is a vertically-aligned liquid crystal layer. In other words, the liquid crystal molecules contained in the liquid crystal layer 40 have negative dielectric anisotropy and are aligned substantially perpendicular to the substrate surfaces (with a typical pretilt angle of greater than or equal to 85° and less than 90°) in a state where no voltage is applied between the pixel electrodes 26a and the counter electrodes 36. The first alignment film 27 and the second alignment film 37 are vertical alignment films.
Each pixel P has a first domain P1 and a second domain P2 exhibiting an axially symmetrical alignment. Alignment restriction projections 35, which protrude toward the active matrix substrate 10, are provided in the counter substrate 30, in regions corresponding to what is substantially the center of each domain. The alignment restriction projections 35 ensure the axially symmetrical alignment of the liquid crystal molecules in each domain. Oblique electrical fields produced at the edges of the pixel electrodes 26a also work to align the liquid crystal molecules in an axially symmetrical manner.
With the liquid crystal display panel 400, a drop in the display quality caused by the alignment film partially peeling due to vibrations or forces applied from the exterior can be suppressed, without increasing the area of the light shielding layer 32, i.e. without reducing the aperture ratio.
A variation on the liquid crystal display panel according to the present embodiment will be described next.
In the liquid crystal display panel 400, the auxiliary capacitance electrodes 22a are formed in a continuous manner for each column of pixels. In the liquid crystal display panel 400A, auxiliary capacitances of adjacent pixel columns are electrically connected to each other by connection wiring lines 12c. The connection wiring lines 12c are formed by the gate metal layer 12. The connection wiring lines 12c connects two or more of the auxiliary capacitance electrodes 22a in the row direction, which can reduce resistance. The connection wiring lines 12c can be provided so as to connect any two auxiliary capacitance electrodes 22a adjacent in the row direction. Rather than being provided throughout the same pixel rows, a number equivalent to (number of pixel rows−1) or more of the connection wiring lines 12c may be formed as necessary to ensure that the voltage supplied to the auxiliary capacitance electrodes 22a is uniform throughout the entire display region. The connection wiring lines 12c can cause a drop in the pixel aperture ratio, and thus the number of connection wiring lines 12c may be adjusted as appropriate in consideration of the area and the like of the display region in the liquid crystal display panel, for example.
According to embodiments of the present invention, a drop in display quality caused by disorder in the alignment of liquid crystal molecules near photo spacers can be suppressed without causing a drop in the aperture ratio in a liquid crystal display panel. The liquid crystal display panels according to embodiments of the present invention can be used as transverse electrical field mode or vertical electrical field mode liquid crystal display panels.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-008843 | Jan 2016 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2017/001054 | 1/13/2017 | WO | 00 |
