Patent Application
20240393628
Photonic integrated circuits (PICs) generally include predefined on-chip optical waveguides, e.g., fabricated using integration platforms such as indium phosphide (InP), silicon-oninsulator (SOI), silica, and lithium niobate, and have been deployed in optical communication networks.
Existing PICs are generally fabricated using lithography and etching or diffusion processes; thus, their functionality is fixed, and they are sensitive to inevitable fabrication imperfections and variations. To shorten the design cycle and lower the cost of application-specific PICs, partially reconfigurable PICs based on arrays of waveguides and tunable components (e.g., Mach-Zehnder interferometers) have been proposed and demonstrated. However, such multipurpose PICs often have sensitivity to fabrication errors and consume significant electrical power. Several approaches for reconfiguring PICs have been pursued by academia and industry, including thermal and electrooptic phase shifters, electroabsorptive switches, and microelectromechanical systems (MEMs), but they have been hindered by their high-power consumption, large device footprints, and limited reconfigurability. There are benefits to improving the designs of photonic integrated circuits.
An exemplary reconfigurable optical vector-matrix multiplier (VMM) and related optical waveguide switch are provided herein that can be employed in linear, reconfigurable photonic integrated circuits using CMOS electronic drivers developed and optimized for liquid crystal displays (LCDs). The exemplary VMM device can be straightforward to manufacture as compared to counterpart PIC and lower in cost. The exemplary VMM can be configured as a reconfigurable processing unit or waveguide that can be programmed and reprogrammed in real-time to realize different PICs for applications in, e.g., optical communications, linear optical classical and quantum computing, neuromorphic computing, and optical sensing.
In some embodiments, the exemplary VMM is configured as a compact, low loss, and fast optical switch with ultralow power consumption. The small size and the ultralow power consumption can allow for the implementation of large and dense optical network switches that enable a large number of optical systems, such as lidars and vector-matrix multipliers, with applications in, e.g., linear optical classical and quantum computing, neuromorphic computing, and AI accelerators.
In an aspect, an optical vector-matrix multiplier (VMM) is disclosed comprising a base layer; a two-dimensional (2D) electrode array arranged on top of the base layer; a waveguide layer arranged on top of the 2D electrode array, wherein the waveguide layer comprises a plurality of input waveguides and a plurality of output waveguides; and a liquid crystal layer evanescently coupled to the waveguide layer, wherein the liquid crystal layer has a spatially varying refractive index that is selectively defined by an electrical field generated by each electrode of the 2D electrode array, and wherein light is directed through the waveguide layer based on the spatially varying refractive index of the liquid crystal layer.
In some embodiments, the base layer comprises a CMOS chip or an interposer.
In some embodiments, the VMM further includes a top layer formed of glass or SU-8.
In some embodiments, the waveguide layer is separated from the base layer by a spacer.
In some embodiments, the spacer comprises a layer of photoresist.
In some embodiments, the layer of photoresist surrounds a top face and side edges of each electrode of the 2D electrode array such that each electrode of the 2D electrode array extends into the layer of photoresist.
In some embodiments, the layer of photoresist is SU-8.
In some embodiments, the liquid crystal layer is a nematic liquid crystal layer.
In some embodiments, the liquid crystal layer comprises an E7 mixture.
In some embodiments, the liquid crystal layer has a birefringence of ne−no=0.22 at a wavelength of 1550 nm.
In some embodiments, the liquid crystal layer is formed by patterning a layer of photoresist.
In some embodiments, the waveguide layer is formed of amorphous silicon (aSi).
In another aspect, an optical waveguide switch is disclosed comprising a base layer; a two-dimensional (2D) electrode array arranged on top of the base layer; a liquid crystal layer; and one or more waveguides that extend through the liquid crystal layer, wherein the liquid crystal layer has a spatially varying refractive index that is selectively defined by an electrical field generated by each electrode of the 2D electrode array, and wherein light traveling through the one or more waveguides is manipulated based on the spatially varying refractive index of the liquid crystal layer by controlling the electrical field generated by each electrode of the 2D electrode array.
In some embodiments, the base layer comprises a CMOS chip or an interposer.
In some embodiments, the optical waveguide switch further includes a top layer formed of glass or SU-8.
In some embodiments, the liquid crystal layer is a nematic liquid crystal layer.
In some embodiments, the liquid crystal layer comprises an E7 mixture.
In some embodiments, the liquid crystal layer is formed by patterning a well into a layer of photoresist and filling the well with an E7 mixture.
In some embodiments, the one or more waveguides comprises at least three waveguides.
In some embodiments, the one or more waveguides are formed of amorphous silicon (aSi).
Additional advantages will be set forth in part in the description which follows or may be learned by practice. The advantages will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive, as claimed.
Various objects, aspects, features, and advantages of the disclosure will become more apparent and better understood by referring to the detailed description taken in conjunction with the accompanying drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements.
Some references, which may include various patents, patent applications, and publications, are cited in a reference list and discussed in the disclosure provided herein. The citation and/or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to any aspects of the present disclosure described herein. In terms of notation, “[n]” corresponds to the n-th reference in the list. All references cited and discussed in this specification are incorporated herein by reference in their entirety and to the same extent as if each reference was individually incorporated by reference.
Referring generally to the figures, a reconfigurable optical vector-matrix multiplier (VMM) and related optical waveguide switch, as noted above, are shown, according to various implementations. The VMM described herein, in some implementations, can enable linear photonic integrated circuits (PICs), which can be rapidly (e.g., in approximately 10 μs) reconfigured. In some implementations, the VMM described herein enables linear PICs that can be derived using well-established CMOS electronic drivers developed and optimized for liquid crystal displays (LCDs). In some implementations, PICs enabled by the disclosed VMM are relatively simple to manufacture compared to conventional counterparts and low in cost. Devices based on the disclosed VMM can be programmed and reprogrammed in real-time to realize different PICs for applications in, e.g., optical communications, linear optical classical and quantum computing, neuromorphic computing, and optical sensing.
Existing photonic integration platforms, such as InP PICs [2] and silicon photonics [3], have successfully implemented photonic circuits with fixed functionalities for optical communications, sensing, and computation [7] applications. Such PICs are similar to application-specific integrated circuits (ASICs) used in electronics because their functionalities are fixed by lithographic patterning during fabrication. In addition, their response is sensitive to small imperfections and errors in the shape and dimensions of the patterned structures and their reliable fabrication requires precise control over nanoscale features. Several recent efforts have been dedicated to addressing these issues by developing tunable and partially reconfigurable PICs (e.g., [1], [9], [10], [11]). A goal of such efforts is to develop PICs that resemble electronic field-programmable gate arrays (FPGAs). The tunability alleviates the sensitivity to fabrication imperfections and the reconfigurability reduces the design cycle and cost of developing PICs. State-of-the-art reconfigurable PICs are composed of cascades or meshes of 2×2 couplers tuned by heaters and using the thermo-optic effect [1], [10], thus consuming significant power while providing limited reconfigurability and requiring complex calibration and programming algorithms.
The disclosed device addresses these issues and enables fully reconfigurable PICs with low power consumption. In contrast to other optical integration platforms, the flow of light in the chip's plane is entirely controlled by an array of electrodes that define a reconfigurable spatially varying refractive index distribution. The fabrication process of the proposed PICs does not involve lithography and patterning of the optical slab region; thus, nanoscale imperfections due to patterning do not affect the device performance. In some implementations, the functionality of the VMM described herein can be fully defined, e.g., through software. As mentioned above, most existing PICs are designed to have predefined fixed functions that are set by micro and nanoscale patterning of dielectrics, semiconductors, and metals. As a result, the development of any new photonic chip requires a significant investment and is time-consuming. Furthermore, a PIC that can be programmed and reconfigured quickly will enable highly desirable devices and systems such as lidar transceivers, large switches for optical communications, high-speed free-space optical communications, and accelerators.
The VMM described herein generally utilizes liquid crystals for reconfigurability. Liquid crystals are a proven technology for displays and liquid-crystal-on-silicon spatial light modulators. However, it has been long believed that they have significant absorption and scattering losses that limit their application in PICs and have a slow response. These and other limitations have been addressed by the VMM described herein through a design that alleviates loss-inducing mechanisms. As demonstrated herein, a high-speed response can be achieved using liquid crystals by driving them into their desired states using large electric fields. These advancements can enable a new class of PICs that are fully reconfigured in sub-millisecond time scales and with a power consumption at least 6 orders of magnitude lower than competing solutions.
As noted above, also disclosed herein, is a compact, low-loss, and fast optical switch with ultralow power consumption. The small size and the ultralow power consumption allow for the implementation of large and dense optical network switches that enable a large number of optical systems, such as lidars and vector-matrix multipliers, with applications in, e.g., linear optical classical [7] and quantum computing [13], neuromorphic computing [14], and AI accelerators [14]. The exemplary system and method can be employed in such architectures.
The disclosed optical switch consumes orders of magnitudes lower power than competing technologies (e.g., thermo-optic and carrier-injection) and is significantly smaller than waveguide switches with low power consumption (e.g., electro-optic, depletion, and MEMs). The switching mechanism, which is based on phase matching, is different from other switches that are typically based on interference (e.g., Mach-Zehnder interferometer or changing the coupling strength, MEMs switches with moving waveguides). Example VMM with Linear PIC
Referring now to
In the example shown in
The VMM 100 is an example implementation of the universal linear optical element and can be entirely reconfigured using a dense array 104 of electrodes 106, e.g., fabricated on silicon chips 108. The device 100 can also implement a wide range of waveguide-based PICS and enables a new family of integrated optics components and structures based on on-demand continuously varying refractive index distributions.
In some implementations, light is input from a set of input waveguides 110 and then enters a slab waveguide region that is evanescently coupled to a layer of LC 112 with a spatially varying refractive index, which is defined by the voltages of the electrode array 104. The light is confined to the slab waveguide (e.g., of the LC 112) and is diffracted and directed by the spatially varying refractive index of the LC as it propagates in or along a plane of the chip. The LC's director direction, and thus the local effective index of the slab waveguide, is controlled by a quasi-electrostatic field generated by an electrode array 104 that is energized and controlled by a CMOS silicon chip 108. The dense array 104 of electrodes 106 allows for the realization of a wide range of refractive index distributions. By selecting the electrode voltages, waveguides and structures with continuously varying refractive index distributions can be realized. The VMM (e.g., 100) enables low-cost lithography-free fully reconfigurable linear PICs whose programming and control complexities are delegated to well-established CMOS chips.
Referring now to
In some embodiments, the frequency range is from 1 kHz-200 kHz, e.g., 1 kHz-2 kHz, 2 kHz-3 kHz, 3 kHz-4 kHz, 4 kHz-5 kHz, 5 kHz-6 kHz, 6 kHz-7 kHz, 8 kHz-9 kHz, 9 kHz-10 kHz. In some embodiments, the frequency range is from 1 kHz-10 kHz, 10 kHz-20 kHz, 20 kHz-30 kHz, 30 kHz-40 kHz, 40 kHz-50 kHz, 50 kHz-60 kHz, 60 kHz-70 kHz, 70 kHz-80 kHz, 80 kHz-90 kHz, 90 kHz-100 kHz, 100 kHz-110 kHz, 110 kHz-120 kHz, 120 kHz-130 kHz, 130 kHz-140 kHz, 140 kHz-150 kHz, 150 kHz-160 kHz, 160 kHz-170 kHz, 170 kHz-180 kHz, 180 kHz-190 kHz, 190 kHz-200 kHz. In some embodiments, the frequency is greater than 200 kHz.
The VMM (100) may use an LC layer 112 whose director axis at zero fields is aligned normal to the chip's plane. Such an alignment is known as the homeotropic alignment, to provide a transverse electric (TE) mode of the slab waveguide, whose electric field is polarized parallel to the chip's plane, is not affected by the anisotropy of the LC 112 at zero applied field. Applying a quasi-static electric field along a direction parallel to the plane of the chip can rotate the director axis, increasing the in-plane refractive index of the LC cladding and thus affecting the propagation of the TE-polarized light inside the slab. In its simplest form, the director's orientation over a straight strip of the LC layer 112 can rotate and become parallel to the chip's plane and normal to the strip's direction. Such a distribution can be generated using two parallel electrodes and can lead to the confinement of light in the slab's plane by defining a straight waveguide.
The 2D electrode array 104, e.g., shown in
For N input waveguides and M output waveguides for a VMM device that can receive complex-valued phasor amplitude of the optical waves in the input and output waveguides by N×1 and M×1 vectors a and b, respectively, the operation performed by the VMM shown in
For a given LC index distribution (i.e., fixed electrode voltages), light entering from different input waveguides is directed to output waveguides by different ratios and phase shifts that are given by the elements in different rows of the L matrix.
In the example of a vector matrix multiplier, the input can be applied to a given pattern of electrode array having a matrix p×q to perform a multiplier operation that can be observed at the output. The multiplier can thus be used as a processing unit or co-processing unit that operates with a microprocessor.
In the example of a switch, the input can be applied to a given pattern of electrodes, e.g., corresponding to network addresses, to allow for routing.
Referring now to
In this example, the VMM 500 includes an array 104 of interdigitated electrodes 106 (now referred to as 502) that can generate and define uniform electric fields along the electrode's length. In some implementations, the electronic chip's surface is planarized by spin coating a ˜200-nm-thick layer of SU-8 polymer (e.g., 206;
In some implementations, the surface of each chip is coated with monolayers of a hexadecyltrimethylammonium bromide surfactant (HTAB) for achieving the homeotropic alignment of the LC [15]. Other surfactants can be used.
Finally, in some implementations, each chip was diced and bonded, and the LC cell filled with the E7 liquid crystal mixture (e.g.,
To confirm the homeotropic alignment and that the interdigitated electrodes define stripes of the director's reorientation, the transmission of visible light normal to the bonded chip's plane was measured. The bonded chip was placed between two crossed polarizers, and the electrodes were at 45° with respect to the polarizer's transmission axes. The transmitted light was imaged using an optical microscope, and the recorded photos are presented in
Next, it was confirmed that the transmitted light—and thus the director's orientation—are not modulated at the 1 kHz rate of the applied voltage; therefore, the waveguides defined by the LC are not temporally modulated. To further examine the creation and propagation loss of waveguides defined by the LC, a 1550 nm laser light was coupled to one of the short aSi waveguides at the edge of the device. The coupling was achieved by focusing the polarized laser light on the waveguide's diced facet using a microscope objective and imaging the chip from the top using another microscope objective, a tube lens, and an InGaAs camera. By applying a square wave with 5 Vp-p to the electrodes, an array of waveguides were formed and the light entering the slab from the short aSi waveguide was guided by one of them that was best aligned to the aSi waveguide.
In some implementations, the waveguides could be “switched off” using the electrode voltage, to examine the propagation loss by observing the light's intensity scattered off from the LC-defined waveguide. It was found that the propagation loss is on the order of a few dB/cm. Scattering loss dominates the propagation loss in LCs due to the director's thermal fluctuations; however, the light in the slab only interacts with the LC close to the slab's surface whose director's orientation is anchored at the surface by the alignment layer (the surfactant monolayer). This finding is consistent with previous reports of a significant reduction of propagation loss in anchored LCs.
In
Generally, in
As shown, a controller 608 can further be electrically coupled to one or more of array 602, light source 604, and detector 606 to control the operations of each component. In particular, controller 608 may be configured to control light source 604 by selectively activating 604, e.g., to cause light source 604 to emit light. In some implementations, controller 608 can transmit data to light source 604 to cause light source 604 to emit light in specific patterns, etc. In some implementations, controller 608 can receive and process data from detector 606. For example, controller 608 can extract data based on the light detected by detector 606. In some implementations, controller 608 can control each optical VMM of array 602 by controlling a voltage provided to the electrode array on each optical VMM. In this regard, controller 608 may be able to dynamically reconfigure each optical VMM to modify the transmission of light through array 602. Thus, array 602 can be operated as an optical field programmable gate array (FPGA).
Controller 608 is shown to include a processor and memory. The processor can be a general-purpose processor, an ASIC, one or more FPGAs, a group of processing components, or other suitable electronic processing structures. In some embodiments, the processor is configured to execute program code stored on memory to cause controller 608 to perform one or more operations, as described below in greater detail. It will be appreciated that, in embodiments where controller 608 is part of another computing device, the components of controller 608 may be shared with, or the same as, the host device.
Memory can include one or more devices (e.g., memory units, memory devices, storage devices, etc.) for storing data and/or computer code for completing and/or facilitating the various processes described in the present disclosure. In some embodiments, the memory includes tangible (e.g., non-transitory), computer-readable media that store code or instructions executable by the processor. Tangible, computer-readable media refers to any physical media that is capable of providing data that causes controller 608 to operate in a particular fashion. Example tangible, computer-readable media may include, but is not limited to, volatile media, non-volatile media, removable media and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. Accordingly, memory can include RAM, ROM, hard drive storage, temporary storage, non-volatile memory, flash memory, optical memory, or any other suitable memory for storing software objects and/or computer instructions. Memory can include database components, object code components, script components, or any other type of information structure for supporting the various activities and information structures described in the present disclosure.
While shown as individual components, it will be appreciated that the processor and/or memory can be implemented using a variety of different types and quantities of processors and memory. For example, the processor may represent a single processing device or multiple processing devices. Similarly, memory may represent a single memory device or multiple memory devices. Additionally, in some embodiments, controller 608 may be implemented within a single computing device (e.g., one server, one housing, etc.). In other embodiments, controller 608 may be distributed across multiple servers or computers (e.g., that can exist in distributed locations). For example, controller 608 may include multiple distributed computing devices (e.g., multiple processors and/or memory devices) in communication with each other that collaborate to perform operations. For example, but not by way of limitation, an application may be partitioned in such a way as to permit concurrent and/or parallel processing of the instructions of the application. Alternatively, the data processed by the application may be partitioned in such a way as to permit concurrent and/or parallel processing of different portions of a data set by the two or more computers. In some implementations, rather than communicating directly with controller 608, one or more of array 602, light source 604, and detector 606 may alternatively or additionally coupled to another remote computing device.
The number of electrical connections for the ultralow power liquid crystal switch may be smaller as compared to the structure, e.g., for a vector matrix multiplier. In some embodiments, the number of electrical connections may be between two and four to either drive an external driver or use an integrated CMOS driver.
An array of switches can be used to make an optical circuit with some reconfigurability. A single switch can also operate as an independent device without having to be implemented in an array. The ultralow-power liquid crystal switch may be employed in similar application domains (AI accelerators, Linear quantum optics commuting, Optical communications, Lidars, etc., e.g., as described in relation to [22], [23], [24]) The switch may have a smaller footprint for applications that have a few inputs and a few outputs but the VMM (e.g., discussed above) can provide a more compact and versatile structure for the case when the number of inputs and outputs are larger than, for example, ten.
Referring first to
In general, the switch is composed of two evanescently coupled waveguides of different widths. Because of the different widths, the two waveguides have different effective indices (e.g., are not phase-matched) and the light does not efficiently couple from one to another. By properly selecting the coupling length of the two waveguides, the coupling between the two waveguides can become very small (e.g., the OFF state of the switch). Simulation results for two amorphous silicon (aSi) waveguides with a core thickness of 50 nm and widths of 0.72 μm and 1 μm are also shown in
The schematic of the cross-section and the optical intensities for the TE modes of the two waveguides composing the switch are shown in
A localized quasi-electrostatic field can be applied using two electrodes placed under the two waveguides, as shown. The gap between the two electrodes is aligned to the center of the narrower waveguide such that the static field is mainly along the x-axis in the region over the narrower waveguide and along the y-axis over the wider waveguide, as verified by the electrostatic simulation results. By applying a field with a correct amplitude, an effective index change of 0.035 is achievable, and the switch can be turned ON. The power consumption of the switch, when driven by a 200 kHz, 5 V peak-to-peak signal, is estimated as 5 nW using its approximate impedance value of 100-j700 MΩ [27].
A study was conducted to develop and evaluate an optical vector matrix multiplier (VMM) and related optical waveguide switch, e.g., for the exemplary device and method described in relation to
LC Loss and Speed. The study evaluated the LC loss and speed.
Two potential concerns related to the use of LCs are their potential excess loss and switching speeds. To examine these issues, the device shown in
To determine the switching speed of the LC, the transmission of visible light normal to the chip's plane was measured (
Bidirectional 1×3 waveguide switch. The study evaluated a 1×3 waveguide switch.
Referring now to
LC-cladded strip waveguide.
The construction and arrangement of the systems and methods as shown in the various implementations are illustrative only. Although only a few implementations have been described in detail in this disclosure, many modifications are possible (e.g., variations in sizes, dimensions, structures, shapes and proportions of the various elements, values of parameters, mounting arrangements, use of materials, colors, orientations, etc.). For example, the position of elements may be reversed or otherwise varied, and the nature or number of discrete elements or positions may be altered or varied. Accordingly, all such modifications are intended to be included within the scope of the present disclosure. The order or sequence of any process or method steps may be varied or re-sequenced according to alternative implementations. Other substitutions, modifications, changes, and omissions may be made in the design, operating conditions, and arrangement of the implementations without departing from the scope of the present disclosure.
Although the figures show a specific order of method steps, the order of the steps may differ from what is depicted. Also, two or more steps may be performed concurrently or with partial concurrence. Such variation will depend on the software and hardware systems chosen and on designer choice. All such variations are within the scope of the disclosure. Likewise, software implementations could be accomplished with standard programming techniques with rule-based logic and other logic to accomplish the various connection steps, processing steps, comparison steps and decision steps.
It is to be understood that the methods and systems are not limited to specific synthetic methods, specific components, or to particular compositions. It is also to be understood that the terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting.
As used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Ranges may be expressed herein as from “about” one particular value, and/or to “about” another particular value. When such a range is expressed, another implementation includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms another implementation. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.
“Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where said event or circumstance occurs and instances where it does not.
Throughout the description and claims of this specification, the word “comprise” and variations of the word, such as “comprising” and “comprises,” means “including but not limited to,” and is not intended to exclude, for example, other additives, components, integers or steps. “Exemplary” means “an example of” and is not intended to convey an indication of a preferred or ideal implementation. “Such as” is not used in a restrictive sense, but for explanatory purposes.
Disclosed are components that can be used to perform the disclosed methods and systems. These and other components are disclosed herein, and it is understood that when combinations, subsets, interactions, groups, etc. of these components are disclosed that while specific reference of each various individual and collective combinations and permutation of these may not be explicitly disclosed, each is specifically contemplated and described herein, for all methods and systems. This applies to all aspects of this application including, but not limited to, steps in disclosed methods. Thus, if there are a variety of additional steps that can be performed it is understood that each of these additional steps can be performed with any specific implementation or combination of implementations of the disclosed methods.
The following patents, applications, and publications, as listed below and throughout this document, are hereby incorporated by reference in their entirety herein.
This U.S. patent application claims priority to, and the benefit of, U.S. Provisional Patent Application No. 63/503,224, filed May 19, 2023, entitled “Liquid Crystal Enabled Reconfigurable Photonic Integrated Circuit,” which is incorporated by reference here in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63503224 | May 2023 | US |
