1. Technical Field
The disclosure relates to liquid crystal display (LCD) technology, and more particularly, to a liquid crystal panel and an LCD having pre-charging switch units between a data line and a common line thereof.
2. Description of Related Art
LCDs have the advantages of portability, low power consumption, and low radiation, and thus are widely used in various portable information technology products, such as notebooks, personal digital assistants, video cameras, and the like.
In the LCD 10, the scanning lines 141 are electrically coupled to the scanning driver 11 for receiving scanning signals, the common lines 142 are electrically coupled to the common voltage driver 13 for receiving common voltage signals, and the data lines 143 are electrically coupled to the data driver 12 for receiving data signals. Each pixel unit 15 includes a thin film transistor (TFT) 151, a liquid crystal capacitor 152, and a storage capacitor 153. A gate electrode of the TFT 151 is electrically coupled to a corresponding scanning line 141, and a source electrode of the TFT 151 is electrically coupled to a corresponding data line 142. Further, a drain electrode of the TFT 151 is electrically coupled to the liquid crystal capacitor 142. The storage capacitor 153 is electrically coupled between the drain electrode of the TFT 151 and the common line 142, and parallel to the liquid crystal capacitor 152.
Because the data line 143 is perpendicular to the common line 142, each pixel unit 15 may further include a parasitic capacitor 154 between the data line 143 and the common line 342. The parasitic capacitor 154 is located where the data line 143 superposes the common line 142, and is cooperatively formed by the data line 143, the common line 142, and an insulator layer (not shown) therebetween.
Referring to
When the LCD 10 displays an (n+1)th frame, the common voltage driver 13 provides a high level common voltage VCOMH to the common line 142, and the data driver 12 provides a negative data voltage Vd2 to reversely charge the liquid crystal capacitor 152 and the storage capacitor 153, so as to drive the pixel unit 15 to display a corresponding picture unit.
The alternation of positive data voltage Vd1 and negative data voltage Vd2 in the LCD 10 can protect liquid crystal molecules within the liquid crystal capacitors 152 from decay or damage, however, when the data voltage is switched between positive and negative, the common voltage provided to the common line 142 correspondingly alternates between the low level common voltage VCOML and the high level common voltage VCOMH, so as to ensure a potential difference in the liquid crystal capacitor 152. Therefore, a voltage variation in the common line 142 may be excessive, due to a capacitor coupling effect of the parasitic capacitor 154, such variation may further cause the data voltage provided to the pixel unit 15 to be coupled and shift from that output from the data driver 12. This may affect display quality of the LCD 10.
What is needed is to provide an LCD that can overcome the described limitations.
The components in the drawings are not necessarily drawn to scale, the emphasis instead placed upon clearly illustrating the principles of at least one embodiment. In the drawings, like reference numerals designate corresponding parts throughout the various views.
Reference will now be made to the drawings to describe certain exemplary embodiments of the present disclosure in detail.
Referring to
In the LCD 30, the scanning lines 341 are electrically coupled to the scanning driver 31 for receiving scanning signals, the common lines 342 are electrically coupled to the common voltage driver 33 for receiving common voltage signals, and the data lines 343 are electrically coupled to the data driver 32 for receiving data signals. Each pixel unit 35 includes a thin film transistor (TFT) 351, a liquid crystal capacitor 352, and a storage capacitor 353. A gate electrode of the TFT 351 is electrically coupled to a corresponding scanning line 341, and a source electrode of the TFT 351 is electrically coupled to a corresponding data line 342. Further, a drain electrode of the TFT 351 is electrically coupled to the liquid crystal capacitor 342. The storage capacitor 353 is electrically coupled between the drain electrode of the TFT 351 and the common line 342, and parallel to the liquid crystal capacitor 352.
Because the data line 343 is perpendicular to the common line 342, each pixel unit 35 may further include a parasitic capacitor 354 between the data line 343 and the common line 342. The parasitic capacitor 354 is located where the data line 343 superposes and insulates from the common line 342, and is cooperatively formed by the data line 343, the common line 342, and an insulator layer (not shown) therebetween.
The pre-charging switch unit 39 may correspond to a row of pixel units 35. The pre-charging switch unit 39 includes a control terminal 391 and a pair of connecting terminals 392 and 393. The control terminal 391 is electrically coupled to the timing controller 38, and is configured for receiving a control signal Vp from the timing controller 38. The control signal Vp is used to control a working state of the pre-charging switch unit 39, for example, the control signal Vp may switch the pre-charging switch unit 39 on as to connect the connecting terminals 392 and 393, or switch the pre-charging switch unit 39 off as to disconnect the connecting terminals 392 and 393. The connecting terminals 392 and 393 can be electrically coupled to a selected one of the data line 343 and a common line 342 corresponding to the row of pixel units 35 respectively.
With this configuration, when the pre-charging switch unit 39 is switched on under the control of the control signal Vp, a voltage of the common line 342 can be pre-charged to approximately the same as that of the data line 343. In an embodiment, the pre-charging switch unit 39 can be a transistor, for example, a Negative-Positive-Negative type bipolar junction transistor (NPN BJT), with a base electrode, a collector electrode and an emitter electrode thereof respectively serving as the control terminal 391 and the connecting terminals 392 and 393.
The timing controller 38 is configured to provide a timing signal to the scanning driver 31, the data driver 32, and the common voltage driver 33, so as to control operational timing of these drivers 31, 32 and 33. Moreover, the timing controller 38 may also be configured to output the control signal Vp for controlling the working state of the pre-charging switch unit 39.
The scanning driver 31 is configured to provide a plurality of scanning signals Vg to the pixel units 35, thereby activating the pixel units 35 row by row. The data driver 32 is configured to provide a plurality of data signals Vd to the activated pixel units 35. The common voltage driver 33 is configured to provide a common voltage signal having a predetermined electrical potential level to the common line 342. In particular, the common voltage driver 33 may alternately output a high level common voltage VCOMH and a low level common voltage VCOML according to the timing signal provided by the timing controller 38.
In one embodiment, the common voltage driver 33 may include a first common voltage generator 331 for generating the high level common voltage VCOMH, a second common voltage generator 332 for generating the low level common voltage VCOML, and a selector 333 for selectively outputting one of the high level common voltage VCOMH and the low level common voltage VCOML under the control of the timing signal provided by the timing controller 38. Due to the selective output process, the common voltage driver 33 may respectively output the high level common voltage VCOMH and the low level common voltage VCOML to a common line 342 in two subsequential frame periods.
Referring to
When the LCD 30 displays an (n+1)th frame of picture (i.e., enter (n+1)th frame period), the timing controller 38 stops outputting the control signal Vp and accordingly the pre-charging switch unit 39 is switched off, the scanning driver 31 provides a plurality of scanning signals Vg to activate the pixel unit 35 according to a timing signal output from the timing controller 38, and the common voltage driver 13 re-selects the high level common voltage VCOMH as an output signal and then outputs to the common lines 142. Because the common line 342 is pre-charged to about the positive data voltage Vd1 at the end of the nth frame period, the electrical potential of the common line 342 can be pulled up to the high level common voltage VCOMH in a very short time.
In addition, upon activation the scanning signal Vg, the TFTs 351 in the activated pixel units 35 are switched on. Using the pixel unit 35 as illustrated in
Similarly, at the end of the (n+1)th frame period, the timing controller 38 re-outputs the control signal Vp to switch on the pre-charging switch unit 39 again, and thus the common line 342 is pre-charged to about the negative data voltage Vd2. When the LCD 30 enters an (n+2)th frame period, the control signal Vp is removed and thus the Page of pre-charging switch unit 39 is switched off, and the common voltage driver 13 re-selects the low level common voltage VCOML to output to the common line 142. Due to the pre-charging process, the common line 342 is pre-charged to about the negative data voltage Vd2 prior to the (n+2)th frame period, the electrical potential of the common line 342 can be pulled up to the high level common voltage VCOML quickly in the (n+2)th frame period. Additionally, the data voltage provided to the pixel unit 35 recovers to the positive data voltage Vd1, and the positive data voltage Vd1 charges the liquid crystal capacitor 352 and the storage capacitor 353, so as to drive the pixel unit 35 to display a corresponding picture unit.
Moreover, in alternative embodiments, the pre-charging switch unit 39 can also be integrated in the liquid crystal panel 34, for example, in the form of TFTs. Furthermore, in other alternative embodiments, the LCD 30 can include a plurality of pre-charging switch units 39 each corresponding to a respective common line 342 and coupled between the corresponding common line 342 and a respective data line 343.
In the LCD 30 of the present disclosure, the pre-charging switch unit 39 is employed to enable the voltage of the common line 342 to be adjusted by the data voltage before entering a subsequential frame period. With this configuration, a voltage variation in the common line 342 can be lowered when the LCD 30 switches from a Page of current frame period to a subsequent frame period. As such, the data voltage shift that might otherwise exist decreases, and accordingly, a display quality of the LCD 30 is improved.
It is to be further understood that even though numerous characteristics and advantages of a preferred embodiment have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only; and that changes may be made in detail, especially in matters of shape, size and arrangement of parts within the principles of disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
Number | Date | Country | Kind |
---|---|---|---|
200910309855.1 | Nov 2009 | CN | national |