1. Field of the Invention
The present invention relates to a liquid crystal panel having compensation capacitors for balancing RC delay effect, and more particularly to a liquid crystal panel with uniform delay times in all control lines.
2. Description of the Related Art
Typically, a liquid crystal panel includes an active matrix substrate 10 having a plurality of data lines 13 and scanning lines 12, and the data lines 13 are perpendicular to the scanning lines 12, as shown in
The data lines 13 and the scanning lines 12 extend out of the active area B for transmitting signals from driving devices. A plurality of pads are formed in outer-lead bonding (OLB) areas 14 located on the periphery of the active area B, and are used for mounting the driving devices. Each of the OLB areas 14 is separately connected to one of fan-out areas 16 including a plurality of leads 15.
where ρ, L and S respectively represent resistance, length, and cross sectional area of the lead 15.
The transverse axle in FIG. 3(a) represents the assigned numbers of the leads 15 from the leftmost one to the rightmost one with regard to FIG. 2. Furthermore, FIG. 3(b) shows a graph of the variable capacitances of all the leads 15. The product of resistance R and capacitance C is directly related to the delay time of a signal transmitted by either one of the data lines 13 or one of the scanning lines 12. Therefore, the delay time caused by RC delay effect is variable from the most outside lead 151 to the middle lead 152, as shown in FIG. 3(c).
Unfortunately, the variation of the delay time in the scanning lines 12 gives rise to a flicker phenomenon so as to deteriorate image quality. Therefore, the zigzag configuration of a fan-out area 16′ is provided for only reducing the variation of resistances, as shown in FIG. 4. Because all the leads is enclosed by the certain area of the fan-out area 16′, the total length of a zigzag middle lead 152′ is still shorter than the length of a straight outside lead 151′. In conclusion, the product R×C of the lead 151′ is different from that of the lead 152′. That is, the flicker phenomenon also exists in the liquid crystal panel with zigzag leads.
An objective of the present invention is to provide a liquid crystal panel having compensation capacitors for balancing RC delay effect. Each compensation capacitor with a predetermined capacitance is connected to each lead so as to minimize the variation of RC delay effect between all leads.
In order to achieve the objective, the present invention discloses a liquid crystal panel having compensation capacitors for balancing RC delay effect, which comprises an active matrix substrate, an opposing substrate facing the active matrix substrate, and a liquid crystal layer disposed between the active matrix substrate and the opposing substrate. On the active matrix substrate, a plurality of parallel signal lines and a plurality of parallel scanning lines are arranged for forming a matrix of pixels called an active area.
A plurality of pads are formed in outer-lead bonding (OLB) areas located on the periphery of the active area, and are used for mounting driving devices. Each of the OLB areas is separately connected to one of fan-out areas including a plurality of leads. Each compensation capacitor with a predetermined capacitance is connected to each lead so as to minimize variation of RC delay effect between all leads.
The invention will be described according to the appended drawings in which:
FIG. 3(a) is a graph illustrating variation of resistances of the leads of the fan-out area in
FIG. 3(b) is a graph illustrating variation of capacitances of the leads of the fan-out area in
FIG. 3(c) is a graph illustrating variation of the products of resistances and capacitances between all the leads in
FIG. 6(a) is an enlarged diagram of portion E in
FIG. 6(b) is an equivalent circuit diagram of the lead L1 and the capacitor C1 in FIG. 6(a);
FIG. 6(c) is a diagram similar to that of FIG. 6(a), with series-connected capacitances;
FIG. 7(a) is a graph illustrating variation of resistances of the leads in
FIG. 7(b) is a graph illustrating variation of capacitances of the leads in
FIG. 7(c) is a graph illustrating variation of the products of resistances and capacitances between all the leads in FIG. 6.
The data lines 53 and the scanning lines 52 extend out of the active area D for transmitting signals from driving devices. A plurality of pads are formed in outer-lead bonding areas 54 near the periphery of the active area D, and are used for mounting the driving devices. Each of the OLB areas 54 is separately connected to one of fan-out areas 56. A plurality of leads 55 are enclosed in each of the fan-out areas 56.
In comparison with the active matrix substrate 10 in
In this case, each of the compensation capacitors C1-C2n is separately connected to corresponding one of the leads L1-L2n in parallel (connection in series is another embodiment). FIG. 6(b) shows an equivalent circuit diagram of the lead L1 and the capacitor C1, wherein RL1 and CL1 separately represent an equivalent resistance and an equivalent capacitance of the lead L1. The total capacitance CT of these capacitors in parallel can be present as follows:
Cr=CL1+C1
Alternatively, the plurality of lead L1-L2n are connected to the plurality of compensation capacitors C1-C2n located in a compensation circuit area 51′ in series, as shown in FIG. 6(c).
FIG. 7(a) is a graph illustrating variation of the resistances of leads in FIG. 6. The transverse axle in FIG. 7(a) represents the assigned numbers of the leads 55 from the leftmost one L1 to the rightmost one L2n with regard to
Apparently, we can determine that a compensation capacitor with a maximum capacitance is connected to the middle lead Ln, and one with a minimum capacitance is connected to the most outside lead L1 or L2n. FIG. 7(b) is a graph illustrating variation of the predetermined capacitances. From the most outside lead L1 to the middle lead Ln, the corresponding capacitances gradually increase in order to balance the RC delay effect of these leads.
The product of resistance and capacitance is directly related to the delay time of a signal transmitted by one of the data lines 53. FIG. 7(c) is a graph illustrating variation of the products of resistances and capacitances between all leads in FIG. 6. From the leftmost lead L1 to the rightmost lead L2n, the products of resistances and capacitances regarding all these leads are uniform. Therefore, the RC delay effect of these leads are similar, and flicker phenomenon is reduced due to minimizing the difference of the delay times between each other.
The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by persons skilled in the art without departing from the scope of the following claims.
Number | Name | Date | Kind |
---|---|---|---|
4787712 | Ukai et al. | Nov 1988 | A |
5714770 | Kim | Feb 1998 | A |
5760858 | Hodson et al. | Jun 1998 | A |
6104465 | Na et al. | Aug 2000 | A |