The present disclosure relates to a liquid ejection head and a process for producing a liquid ejection head.
Liquid ejection apparatuses such as inkjet printing apparatuses use a liquid ejection head. In the liquid ejection head, a device chip having a plurality of ejection ports is disposed. In recent years, liquid ejection heads in which a plurality of device chips are disposed in a line to achieve a wider print width have been used.
The specification of U.S. Patent Application Publication No. 2011/0020965 (hereinafter referred to as document 1) discloses an IC chip shape to dispose the IC chips of a print head in a line, and a layout of each IC chip and a flow path unit relative to each other. Specifically, document 1 discloses that a plurality of IC chips 100 are arrayed in a line with no clearance therebetween, as shown in FIG. 2 of document 1. (In the foregoing and following description, the reference numerals used in document 1 are referenced herein.) Also, as shown in FIG. 11 of document 1, the IC chips 100 are positioned using reference marks 103A on the IC chips 100 and reference marks 103B on a channel molding 124 having a liquid flow path structure.
In document 1, since the IC chips 100 are arrayed in a line with no clearance therebetween, the reference marks 103B on the channel molding 124, having a liquid flow path structure, cannot be disposed on an array axis extending in the array direction of the plurality of IC chips 100. For this reason, the accuracy of the positioning of the adjacent chips may possibly be lowered.
A liquid ejection head according to an aspect of the present disclosure is a liquid ejection head comprising a base plate and at least two device chips in which ejection ports for ejecting a liquid are formed and which are disposed on the base plate. At least one first reference mark is provided on the base plate. A second reference mark is provided on each of the device chips. At least one space is formed between adjacent ones of the device chips. The second reference marks and the first reference mark present in the space are disposed on an array axis along which the device chips are arrayed.
Further features of the present disclosure will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
Embodiments will be described below with reference to the drawings. It is to be noted that the embodiments to be described below are appropriate specific examples and therefore involve various technically preferable limitations. However, the present disclosure is not limited to the embodiments in this specification or other specific methods.
The device chips 2 are joined in a straight line to the upper surface of the base plate 1 with an adhesive agent (not shown in
Each device chip 2 comprises a substrate 3 and an ejection port forming member 4 on the upper surface of the substrate 3. The device chip 2 also comprises electrical connecting portions 5 and a second reference mark 8 in a region of the upper surface of the substrate 3 where the ejection port forming member 4 is not provided. A plurality of ejection ports 6 are formed in the ejection port forming member 4.
The shape of each device chip 2 is such that a space is formed between the adjacent device chips 2 in the state where they are arrayed. Assume for example a case where a first device chip and a second device chip are arrayed in a line in the array direction in which the device chips are arrayed. The device chips 2 in the present embodiment are shaped such that a clearance is formed in at least one region between the first device chip and the second device chip. Forming such a clearance makes part of the surface of the base plate 1 visible through the clearance in a case where the device chips 2 are viewed from their upper surfaces. The first reference marks 7 are disposed on this part of the surface of the base plate 1. This allows positioning using the reference marks (first reference marks 7) disposed on the base plate 1.
Meanwhile, the shape of the device chips 2 in the present embodiment only need to be such that a space is formed between the adjacent device chips. Thus, the device chips 2 may be device chips of an unsymmetrical irregular shape as shown in
Also, the ejection ports are preferably formed such that the ejection ports of the device chips 2 lying adjacent to each other in the state where the device chips 2 are disposed on the base plate 1 overlap each other in the array direction. In this way, in the liquid ejection head 13 with the device chips 2 disposed in the array direction, the ejection ports 6 overlap each other in the array direction between the adjacent device chips. Thus, at each region where adjacent device chips lie in proximity to each other, the liquid can be ejected from the ejection ports 6 of either device chip. This allows continuous ejection without a break in the array direction.
In the present embodiment, on the base plate 1, the first reference marks 7 are disposed, which are used for the positioning of the device chips 2 in disposing them. The first reference marks 7 are formed along the array axis along which the device chips 2 are disposed. The method of forming the first reference marks 7 includes a processing method using mold shaping, laser depiction, or the like in a case where the base plate 1 is made of a resin material, and a processing method using ultrasonic processing, metal transfer, or the like in a case where the base plate 1 is made of ceramic. The method only needs to be a processing method capable of accurately marking the first reference marks 7 on the base plate 1.
In the liquid ejection head 13 in the present embodiment, the second reference marks 8 on the device chips and the first reference marks 7, present in the spaces formed between the adjacently disposed device chips 2, are disposed on the array axis along which the device chips are arrayed. For example, in the present embodiment, the first reference marks 7 are disposed on the base plate 1 to be located in the spaces formed between the adjacently disposed device chips 2. To put it differently, the device chips 2 are formed in such a shape(s) so as not to cover the first reference marks 7, which are disposed on the base plate 1. In sum, the positions on the base plate 1 where the first reference marks 7 are disposed and the shape(s) of the device chips 2 are related to each other.
In the present embodiment, the second reference marks 8 are disposed on the device chips 2. The second reference marks 8 are marks for positioning relative to the first reference marks 7. The second reference marks 8 and the ejection ports 6 are accurately disposed on the device chips 2 since they are patterned by an apparatus for producing semiconductor devices. In the liquid ejection head 13 in the present embodiment, the second reference marks 8 and the first reference marks 7 are disposed on the array axis of the device chips 2. Specifically, the second reference marks 8 on the adjacent device chips 2 and the first reference marks 7 on the base plate are disposed on the array axis of the device chips 2. Also, in the present embodiment, the electrical connecting portions 5 are arrayed on the device chips 2 in the array direction of the device chips, and the second reference marks 8 are disposed on the array axis of these electrical connecting portions 5.
Note that the drawings in the present embodiment show an example where the shapes of the first reference marks 7 and the second reference marks 8 are circular shapes, but the shapes are not limited to circular shapes. The shapes may be cross shapes or patterns that are unlikely to be falsely recognized as patterns around them. Also, the shape of the first reference marks 7 and the shape of the second reference marks 8 may be the same shape or different shapes. Further, the plurality of first reference marks 7 may have the same shape or different shapes. Furthermore, the plurality of second reference marks 8 may have the same shape or different shapes.
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Lastly, electric wiring members for driving the energy generating elements are electrically joined (not shown) to the electrical connecting portions 5 formed on the device chips 201, 202, 203, and 204. As a result, the liquid ejection head 13 is completed.
As described above, the device chips 2 in the present embodiment are configured in such a shape(s) that a space is formed between the adjacent device chips. Moreover, the first reference marks 7 are disposed on the base plate 1 at positions corresponding to these spaces. The first reference marks 7 are disposed on an array axis. The second reference marks 8 are disposed on the device chips 2. Further, in joining the device chips 2 to the base plate 1, they are positioned relative to each other on the array axis by using the first reference marks 7 and the second reference marks 8.
In the present embodiment, since the positioning is performed on the array axis by using the first reference marks 7 and the second reference marks 8, as described above, accurate positioning is achieved. By positioning the second reference marks 8 on the device chips relative to the first reference marks 7 on the base plate as in the present embodiment, accurate positioning is achieved as compared to relative positioning in which the second reference marks 8 are positioned relative to each other. Also, by positioning the second reference marks 8 relative to the first reference marks 7, which are disposed on the array axis, accurate positioning without displacement from the axis is achieved as compared to a case where, for example, the reference marks are disposed in a direction orthogonal to the array direction (the width direction of the liquid ejection head 13). Also, since the device chips 2 in the present embodiment have such a shape(s) that a space is formed between the adjacent device chips, the device chips other than the device chips located at the end sections in the array direction are also positioned relative to the corresponding first reference marks 7, which are disposed on the array axis. Hence, accurate positioning is achieved.
In embodiment 1, a description has been given a liquid ejection head in which device chips are arrayed in a line in the print width direction (Y axis). In embodiment 2, a description will be given of a liquid ejection head in which device chips are arrayed in a matrix in both the print width direction (Y axis) and a direction orthogonal to the print width direction (X axis). The production process is substantially the same as that in embodiment 1, and therefore the difference will be mainly described below.
Since the device chips 201 to 209 in the present embodiment are disposed in a matrix, their electrical connecting portions 5 are configured as back surface electrodes disposed on the back surface sides of the device chips.
In electrically joining the device chips, electric wiring members are disposed on the base plate 1. In order to prevent electric short circuit and the like and avoid contact with a liquid such as ink after the device chips are electrically joined, a sealing agent 15 is injected around the electrical connecting portions 5 from a space 16 between the adjacent device chips. In doing so, the amount and duration of injection of the sealing agent are adjusted such that the sealing agent does not seal the ejection ports 6 in
As described above, even in the case of producing a liquid ejection head in which device chips are arrayed in a matrix, the device chips are accurately positioned and disposed on a base plate.
While the present disclosure has been described with reference to exemplary embodiments, it is to be understood that the disclosure is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2018-166888 filed Sep. 6, 2018, which is hereby incorporated by reference herein in its entirety.
Number | Date | Country | Kind |
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2018-166888 | Sep 2018 | JP | national |
Number | Date | Country | |
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Parent | 17392419 | Aug 2021 | US |
Child | 18517965 | US | |
Parent | 16536675 | Aug 2019 | US |
Child | 17392419 | US |