Patent Application
20180293140
The field of the invention is data processing, or, more specifically, methods, apparatus, and products for live partition mobility with I/O migration.
The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today's computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago.
One area of advancement includes data centers providing cloud services with various types of virtualization services. Regardless of the particular type of virtualization service being offered, most virtualization services make use of massive amounts of data I/O traffic and network bandwidth. In such a computing environment, live partition mobility in which a logical partition executing on a first host is migrated, without reboot, to a second host, is difficult to perform while maintaining the I/O and network connections of the logical partition executing on the first host.
Methods, apparatus, and products for live partition mobility in a computing environment are disclosed in this specification. Such a computing environment includes a source system and a target system. Live partition mobility may include: pausing a logical partition on the source system, wherein the logical partition is mapped to an I/O (input/output') adapter of the source system; copying, to the target system, configuration information describing the mapping of the logical partition to the I/O adapter; copying, to the target system, the logical partition of the source system; placing an I/O adapter of the target system into an error state; mapping, in dependence upon the configuration information, the logical partition of the target system to the I/O adapter of the target system; placing the I/O adapter of the target system into an error recovery state; and resuming the logical partition on the target system.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of exemplary embodiments of the invention.
Embodiments of methods, apparatus, and computer program products for live partition mobility with I/O migration are described with reference to the accompanying drawings, beginning with
The example data center (120) of
Any sized partition can be moved. Essentially, memory is copied asynchronously from one system to another to create a clone of a running partition, with “dirty” memory pages being re-copied as necessary. When a threshold is reached (such as when a high percentage of the pages have been successfully copied across), the logical partition is transitioned to the target machine and any remaining pages are copied across synchronously. Live partition mobility may be used to avoid outages for planned server maintenance, for load balancing across multiple servers, for energy conservation, and the like.
As mentioned above, in prior art computing environments, live partition mobility is restricted to migration of I/O functionality only with respect to completely virtualized I/O. That is, in prior art computing environments, an I/O communications channel between a logical partition and a physical I/O adapter, such as a PCI or PCIe adapter, cannot be migrated with live partition mobility. As explained below in greater detail, the example computing environment of
The computing system (102) includes at least one computer processor (156) or “CPU” as well as random access memory (168) or “RAM,” which is connected through a high speed memory bus (166) and bus adapter (158) to processor (156) and to other components of the computing system (102).
Stored in RAM (168) is a hypervisor (136) and a management console (138). The management console (138) may provide a user interface through which a user may direct the hypervisor (136) on instantiating and maintaining multiple logical partitions (116, 118), where each logical partition may provide virtualization services to one or more clients. Although depicted in the example of
Also stored in RAM (168) are two instances of an operating system (154), one for each logical partition (116, 118). Operating systems useful in computers configured for live partition mobility with physical I/O migration according to various embodiments include UNIX™, Linux™, Microsoft Windows™, AIX™, IBM's i™ operating system, and others as will occur to those of skill in the art. The operating systems (154), hypervisor (136), and management console (138) are shown in RAM (168), but many components of such software may typically be stored in non-volatile memory such as, for example, on a data storage (170) device or in firmware (132).
The computing system (102) may also include a storage device adapter (172) coupled through expansion bus (160) and bus adapter (158) to processor (156) and other components of the computing system (102). Storage device adapter (172) connects non-volatile data storage to the computing system (102) in the form of data storage (170). Storage device adapters useful in computers configured for live partition mobility with physical I/O migration according to various embodiments include Integrated Drive Electronics (“IDE”) adapters, Small Computing system Interface (“SCSI”) adapters, and others as will occur to those of skill in the art. Non-volatile computer memory also may be implemented for as an optical disk drive, electrically erasable programmable read-only memory (so-called “EEPROM” or “Flash” memory (134)), RAM drives, and so on, as will occur to those of skill in the art.
The example computing system (102) may also include one or more input/output (“I/O”) adapters (178). I/O adapters implement user-oriented input/output through, for example, software drivers and computer hardware for controlling output to display devices such as computer display screens, as well as user input from user input devices (181) such as keyboards and mice. The example computing system (102) may also include a video adapter (114), which may be an example of an I/O adapter specially designed for graphic output to a display device (180) such as a display screen or computer monitor. Video adapter (114) may be connected to processor (156) through a high speed video bus (164), bus adapter (158), and the front side bus (162), which may also be a high speed bus.
The example computing system (102) of
Any of the example network adapters from among network adapters (124, 126, and 128) may be configured to support SR-IOV and provide multiple virtual functions, where each of the virtual functions may be mapped to a respective logical partition (116, 118). In this way, each of the logical partitions may independently use a physical network adapter that is being shared among different logical partitions. Such network adapters may also be configured for data communications with other computers or devices (not shown) and for data communications with a data communications network (100, 101). Such data communications may be carried out serially through RS-232 connections, through external buses such as a Universal Serial Bus (“USB”), through PCI and PCIe fabrics, through data communications networks such as IP data communications networks, and in other ways as will occur to those of skill in the art. Network adapters may implement the hardware level of data communications through which one computer sends data communications to another computer, directly or through a data communications network. Examples of communications adapters useful in computers configured for live partition mobility with physical I/O migration according to various embodiments include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.
The network adapters (124, 126, and 128) may further be configured for data communications with hosts (195) over a network (101) reachable through local area networks (LANs), such as LAN (100). The network adapters (124, 126, and 128) may further be configured for data communications with storage area networks (SANs), such as SAN (112), and for data communications with various storage devices (104), such as storage devices (106) and storage devices (108).
As mentioned above, the computing system (102) of
While in this disclosure, various embodiments are described in the context of the SR-IOV standard and PCIe, such descriptions are intended to be illustrative, not limiting. Readers will recognize that failover of a virtual function exposed by an SR-IOV adapter of a computing system may be carried out utilizing other virtualization standards, or no standard at all.
The network adapters (124, 126, and 128) are for purposes of illustration, not for limitation. Other I/O adapters may be utilized in live partition mobility according to embodiments of the present invention. Similarly, data centers according to various embodiments may include additional servers, routers, other devices, and peer-to-peer architectures, not shown in the figures, as will occur to those of skill in the art. Networks in such data processing systems may support many data communications protocols, including for example TCP (Transmission Control Protocol), IP (Internet Protocol), HTTP (HyperText Transfer Protocol), WAP (Wireless Access Protocol), HDTP (Handheld Device Transport Protocol), and others as will occur to those of skill in the art. Various embodiments may be implemented on a variety of hardware platforms in addition to those illustrated.
For further explanation,
An adjunct partition as the term is used in this specification refers to a partition instantiated by a hypervisor and configured for management of SR-IOV adapter resources, including various configuration parameters of virtual functions (224, 226) exposed by the network adapter (232). In some embodiments, for example, each adjunct partition (202) is associated and mapped (212) with a physical function (222) of a discrete network adapter (232). The adjunct partition may include, in addition to a kernel, a driver for managing a network adapter through a management channel specified in the protocol for the network adapter.
The example source system (250) of
To migrate the logical partition (204) from the source system to the target system utilizing live partition mobility with I/O migration, the hypervisor (136a) may pause execution of the logical partition (204), copy, to the target system, configuration information describing the mapping of the logical partition (204) to the I/O adapter (232), and copying, to the target system, the logical partition (204) of the source system. These steps need not occur in any particular order. For example, copying the logical partition (204) to the target system may be done asynchronously over time, page by page until a threshold number of pages has been copied.
The hypervisor (136a) may then direct the hypervisor (136b) to place an I/O adapter of the target system into an error state. An error state may include the ‘EEH’ (enhanced error handling) error state which is an extension to the PCI standard specification and enabled in systems running IBM's Power™ Processors. In embodiments in which the I/O adapter is an SR-IOV adapter and the logical partition migrated to the target system is to be mapped to a virtual function exposed by the SR-IOV adapter, placing the I/O adapter in the error state may include placing only the virtual function in the error state. Once the virtual function is placed in the error state, the hypervisor (136b) may map (220) the logical partition (210) of the target system to a virtual function (230) exposed by the I/O adapter (234) of the target system (252). Mapping the logical partition (210) to the virtual function (230) may include mapping direct memory access (DMA) memory space; MMIO space; mapping interrupts, and other configurations or settings that enable a given logical partition to communicate and use physical resources by interfacing with a given virtual function on a network adapter.
After mapping the logical partition (210) to the virtual function (230), the hypervisor (136b) may place the I/O adapter of the target system into an error recovery state and resume the logical partition on the target system. Once placed into the error recovery state and upon resuming execution of the logical partition, the logical partition (210) will reconnect to the virtual function (230) as if reestablishing communication with the virtual function (226) of the source system. That is, the logical partition (210), from the perspective of I/O functionality, has no knowledge that the logical partition is executing on a different system and coupled for I/O to a different adapter.
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In such an embodiment, mapping (326) the logical partition (314) of the target system (312) to the I/O adapter (316) of the target system is carried out by mapping (406) the logical partition (314) of the target system (312) to a virtual function (404) exposed by the SR-IOV adapter (316) of the target system (312). Mapping the logical partition to a virtual function may be carried out through an adjunct partition configured to manage the SR-IOV adapter (316) of the target system. The hypervisor may update various mappings for the virtual function (404) in the adjunct partition which includes an SR-IOV physical function driver. The SR-IOV physical function driver may also utilize the PF driver management channel of the physical function to configure the I/O adapter as necessary. Some configurations may include instantiating a new virtual function if a standby is not available, mapping MIMO space, DMA space, and so on.
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As changes are made over time to the configuration of the I/O adapter, the copy (608) of the I/O configuration is updated to reflect those changes. As such, responsive to mapping (326) the logical partition (314) of the target system to the I/O adapter (316) of the target system (312), the method of
The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
It will be understood from the foregoing description that modifications and changes may be made in various embodiments of the present invention without departing from its true spirit. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present invention is limited only by the language of the following claims.
This application is a continuation application of and claims priority from U.S. patent application Ser. No. 15/049,506, filed on Feb. 22, 2016.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15049506 | Feb 2016 | US |
| Child | 16007134 | US |
