Patent Application
20080008204
The above and other objects, advantages and features of the present invention will be more apparent from the following description of the exemplary embodiments made in conjunction with the accompanying drawings, in which:
Hereinafter, a load balanced type switching apparatus according to exemplary embodiments of the present invention will be described in detail with reference to the attached drawings.
The load balanced type switching apparatus according to a first exemplary embodiment of the present invention will be described. The basic configuration of the load balanced type switching apparatus of the present invention is as shown in
The destination detecting section 21 detects one of the output stages as a destination of a reception cell supplied from an external unit to the input stage 1 and outputs the reception cell to the VOQ unit 22 and the transmission cell determining section 23. The VOQ unit 22 receives the cell from the destination detecting section 21, and stores it in a VOQ buffer for each destination output stage. Also, the VOQ unit 22 reads the head cell of the VOQ buffer associated with a specified destination output stage in response to a read request from the transmission cell determining section 23, and transmits to a mesh connection section 4. The transmission cell determining section 23 manages the number of cells in each of the VOQ buffers based on the destination output stage data of each cell received from the destination detecting section 21 and determines from which of the VOQ buffers the cell is transmitted into cell time slot. The transmission cell determining section 23 manages the following data in the control memory 24: that is, the number of cells voq_cnt [i] stored in the VOQ buffer for each destination output stage i, cell transmission counter value out_cnt [i] [j] for each output stage i and for each intermediate stage j (j=1 to K: K is the number of the intermediate stages), and the minimum value min_cnt [i] (the minimum value of out_cnt [i] [1], out_cnt [i][2], . . . , and out_cnt [i] [K]) and the maximum value max_cnt [i] (the maximum value of out_cnt [i] [1], out_cnt [i] [2], . . . , and out_cnt [i] [K]) of the transmission counter value out_cnt [i] [j] for each destination output stage i. The number of VOQ accumulated cells for each destination output stage is counted up when the cell is received from the destination detecting section 21, and it is counted down when being determined to be a read target from the VOQ buffer. The transmission counter for each intermediate stage and for each output stage manages the transmission counter value for each cell transfer route defined by the intermediate stage and the output stage. At this time, it is preferable that the cells transmitted from the input stages 1 to the intermediate stage 2 are similar in size. However, they are not always limited to the fixed length cell. For example, in case of a variable length cell, the number of the cells is not counted, and the size (data length) of the cell may be counted. Here, since a good result in view of the performance can be expected in case of the fixed length cell, the fixed length cell is only exemplified here.
The transmission cell determining section 23 recognizes that a cell is received destined to a destination output stage i.
When recognizing that the cell destined to the destination output stage i is received, the transmission cell determining section 23 increments the number of cells in the VOQ buffer corresponding to the destination output stage i (voq_cnt[i]++).
The transmission cell determining section 23 checks whether or not any cell stored in the VOQ buffer associated with a certain destination output stage i exists (voq_cnt[i]>0) and whether or not the destination output stage that is not yet checked exists. If such an output stage does not exist, the process is ended.
If such an output stage exists, whether or not the cell having the destination output stage i can be transmitted in a current intermediate stage cell time slot is determined. If the cell is transmittable, the cell is transmitted and the process is consequently ended. If the cell cannot be transmitted, whether or not a different destination output stage exists is again checked. Then, the process is repeated until the transmittable cell can be found out or until the cell targeted for the check is reduced to 0.
At first, whether or not a difference between a maximum value and a minimum value (max_cnt[i]−min_cnt[i]) is smaller than an allowable difference value is determined. If the difference is smaller than the allowable difference value, the cell can be unconditionally transmitted.
Otherwise, whether or not a transmission counter value out_cnt[i][j] corresponding to the destination output stage i and the intermediate stage j in a current cell time slot coincides with the maximum value max_cnt[i] of the counter is further checked. When the counter value out_cnt[i][j] coincides with the maximum value max_cnt[i], the difference exceeds the allowable difference value if the cell destined to the destination output stage i is transmitted to the intermediate stage j. Thus, the transmission of the cell is determined to be not allowed (No). If the count out_cnt[i][j] does not coincide with the maximum value max_cnt[i], the transmission of the cell to the intermediate stage j is determined to be allowed (Yes).
If the cell destined to the destination output stage i is determined to be transmitted to the intermediate stage j, the number of cells stored in the VOQ buffer is decremented (voq_cnt[i]−−), and the transmission counter value is incremented (out_cnt[i][j]++). Also, the maximum value max_cnt[i] and the minimum value min_cnt[i] are updated as necessary. That is, depending on the counter value out_cnt[i][j], the maximum value max_cnt[i] and the minimum value min_cnt[i] are updated. For example, if the counter value out_cnt[i][j] becomes greater than the maximum value max_cnt[i] at that time, the counter value out_cnt[i][j] is set to the maximum value max_cnt[i] (max_cnt[i]=out_cnt[i][j]). Similarly, if the counter value out_cnt[i][j] becomes smaller than the minimum value min_cnt[i] at that time, the counter value out_cnt[i][j] is set to the minimum value min_cnt[i] (min_cnt[i]=out_cnt[i][j]). Through the above control, a distributing process can be realized to uniformly suppress the difference between the intermediate stages in the number of transmission cells within the allowable difference value for each destination output stage.
It should be noted that in this flowchart, a process is performed of determining for every cell time slot, whether the transmittable cell by using the cell time slot is present. However, under the condition that a plurality of cells are accumulated or stored in the VOQ buffer, the transmittable cells may be determined for the plurality of time slots. By allowing the transmission reservation for the plurality of cell time slots to be performed in one cell time slot, the cells can be transmitted in the throughput of 100% when an average of the determining process times is within one cell time slot, even if an increase or decrease occurs in the determining process time to determine a cell to be transmitted in each cell time slot. Also, when the plurality of cells are continuously transmitted to the same destination, it is possible to reduce the determining process time for each cell time slot. For example, when the difference between the maximum value max_cnt[i] and the minimum value min_cnt[i] is smaller than the allowable difference value in a certain destination output stage i, the difference never becomes greater than the allowable difference value as long as the cells are continuously transmitted. Thus, by performing the once determining process, it is possible to determine that all of the cells accumulated in the VOQ buffer for the destination output stage i can be continuously transmitted.
At a time t=2, a cell having the destination output stage i=2 arrives. At this time, the intermediate stage cell time slot is “2”, and the cell is transmittable. Therefore, the transmission counter is incremented to the counter value out_cnt[2][2]=1, and the maximum value max_cnt[2] is set to “1”.
At t=7, a cell having the destination output stage i=1 arrives. At this time, the intermediate stage cell time slot is “1”. However, the difference between the maximum and the minimum is “2”, i.e., max_cnt[1]−min_cnt[1]=2, and is equal to the allowable difference value. Also, the transmission counter value out_cnt[1][1]=2 having the intermediate stage j=1 and the destination output stage i=1 is equal to the maximum value max_cnt[1]=2. Thus, the cell cannot be transmitted. Therefore, a reception cell is not transmitted, but is accumulated in the VOQ buffer. Also, the transmission counter is incremented to voq_cnt[1]=1.
In a next cell time slot t=8, the intermediate stage cell time slot becomes 2. The value of the transmission counter of the intermediate stage j=2 is out_cnt[1][2]=0. Thus, the transmission of the cell is determined to be possible.
At t=14, the cell destined to the destination output stage i=3 is received. At this time, the intermediate stage cell time slot is 2. Since the stored count voq_cnt[3][2]=1 and this is smaller than the maximum value max_cnt[3]=2, the received cell can be transmitted. However, at a time t=13, the cell accumulated in the VOQ buffer for the destination output stage 1 is selected to be transmitted. Therefore, the received cell destined to the destination output stage i=3 is not transmitted, and this is accumulated in the VOQ buffer (voq_cnt[3]=1).
As in a time t=14, when the cell destined to a destination output stage i2 (in this case, i2=3) is received under the condition that the cell having a destination output stage i1 (in this case, i1=1) is accumulated in the VOQ buffer, there may be a case that the number of the transmittable cells is 2 or more. As the selecting method in case that the plurality of cells can be selected, the following methods are considered.
(a) Random Selection
The reason of the random selection is to remove the deviation between the ports.
(b) Selection by Round Robin Method by Using Previous Selected Cell Having Lowest Priority
When the cell has been outputted from the port 2 at a previous time, a checking process will be performed by a round robin method (3, 1 and 2) from the port 3 at a next time. The reason of selection by the round robin method is to remove a deviation between the ports, similarly to a case of random selection, and an easy installation is possible.
(c) Control of Giving Priority to Cell Accumulated in VOQ Rather than Received Cell in Addition to Above Control
The reason why a priority is given to a cell accumulated in the VOQ buffer rather than the received cell is to prevent increase in delay of the accumulated cell because the cell continues to remain in the switching apparatus. A different selecting method will be described in another example. Here, a transmission cell determining method will be described.
In the present invention,
It should be noted that the count out_cnt[i][j], the maximum value max_cnt[i] and the minimum value min_cnt[j] are parameters that imply the numbers of the transmitted cells, and are also the parameters for performing the distribution control not to exceed the allowable difference value. Actually, as the value stored in the control memory, a K value when meets K>maximum allowable difference value is used as a value after the modulo K calculation. As the value after the modulo K calculation, a remainder when each parameter is divided by K is used. For example, in case of K=4, the counter value 4 is converted into 0 (4 mod 4=0), and the counter value 13 is converted into 1 (13 mod 4=1).
An operation of the control memory updating process (S202-3) when the transmission cell determining section 23 transmits the cell having the destination output stage i to the intermediate stage j will be described below.
A value of 1 is subtracted from the VOQ accumulation cell count (voq_cnt[i]) having the destination output stage i of a target transmission cell. That is, the VOQ accumulation cell number of the destination output stage i of the target transmission cell is decremented (voq_cnt[i]−−).
Next, whether or not the transmission counter value out_cnt[i][j] associated with the output stage i and the intermediate stage j is same as the maximum value max_cnt[i] is checked.
If they are the same, “1” is added to the maximum value max_cnt[i]. That is, the maximum value is incremented (maximum value max_cnt[i]++).
Next, whether or not the transmission counter value out_cnt[i][j] associated with the output stage i and the intermediate stage j is same as the minimum value min_cnt[i] and whether or not the transmission counter out_cnt[i][j] having the minimum value is only one with respect to the destination output stage i are checked.
Next, if the transmission counter value out_cnt[i][j] associated with the output stage i and the intermediate stage j is equal to the minimum value min_cnt[i] and there is only one transmission counter out_cnt[I][j] having the minimum value with regard to the destination output stage i, “1” is subtracted from the minimum value (minimum value min_cnt[i]−−).
Finally, a counter distribution cnt_num [i][ ] is updated.
The value of “1” is added to the transmission counter value out_cnt[i][j] (out_cnt[i][j]++).
In the first example, the updating process of the control memory when the transmission cell is determined is attained independently of the number M of the intermediate stages. Thus, the process can be performed within a fixed time.
At a time t=0 in the initial state, all of the transmission counter values out_cnt[1][1], out_cnt[1][2] and out_cnt[1][3] are 0. Thus, in the counter distribution, the counter distribution cnt_num [1][0]=3, and the counter distributions cnt_num [1][1]=0, cnt_num [1][2]=0 and cnt_num [1][3]=0.
At a time t=1, the counter value out_cnt[1][1] is changed from 0 to 1. Thus, the counter distribution cnt_num [1][0] is decremented to 2, and the counter distribution cnt_num [1][1] is incremented to 1.
At a time t=22, the conceptual counter value out_cnt[1][1]=4. However, the value that is registered in the control memory becomes the counter value out_cnt[1][1]=0, because of the module K(=4) calculation. The counter distribution becomes cnt_num [1][0]=1 in order to calculate the distribution of the transmission counter values after the module K calculation.
Here, a method of determining a VOQ check order will be described. In a second example, a process of determining the check order will be described when the transmission cell determining section 23 checks whether or not the cells in the VOQ are transmittable. The transmission cell determining section 23 is assumed to manage the check order with respect to the destination output stage in accordance with a check order list, in order to determine the destination output stage to be checked.
The transmission cell determining section 23 performs a check process sequentially from the head of the check order list and repeats the check process until a transmittable cell is discovered. When the transmittable cell is discovered and the cell in the corresponding VOQ buffer is reduced to 0, the data of the corresponding destination output stage is deleted from the check order list. Irrespectively of the discovery of the transmittable cell, if the cell remains in the corresponding VOQ buffer, the data of the corresponding destination output stage is shifted to the end of the check order list.
Also, in case of receiving the cell destined to the destination output stage i that is the cell count voq_cnt[I]=0, the destination output stage i is added to the check order list.
At a time t=1, the cell destined to the output stage 4 is newly received, and the cell count voq_cnt[4]=1 is established. Thus, the cell is added to the end of the check order list.
At a time t=2, the cell having the destination output stage 2 is transmitted. However, although the cell count voq_cnt[2]>0 is still kept, the destination output stage i=2 in the check order list is shifted to the end of the check order list.
In this way, since the check order list is used, the transmission cell determining section 23 can determine the transmission cells at a high rate, by using only the cell accumulated in the VOQ buffers as a check target. Also, the cell still accumulated in the VOQ buffer for the longest time can be transmitted with priority. Also, the longest length of the check order list is K. Thus, this implies that there is a transmission chance once per K times even under the worst condition.
In a third example, similarly to the second example, the transmission cell determining section 23 uses the check order list and checks whether or not the cell can be transmitted in the order of the destination output stage i registered in the list. However, when the order of the check order list is defined, it is supposed that a priority parameter for each destination output stage is used to carry out the check in an order starting from the highest value of the priority parameter or an order starting from the lowest value.
As the priority parameter, for example, the followings may be considered.
(a) The order of a more amount of cells stored in the VOQ buffers
(b) The order starting from the largest of differences between the maximum value and the minimum value (max_cnt[I]−min_cnt[I])
(c) In addition to the above order, when the differences are equal to each other, the order starting from the smallest counter distribution cnt_num [i] [min_cnt[i]] of the intermediate stages having the minimum count value
The order starting from the largest one (max_cnt[i]−min_cnt[i])×K+(K−cnt_num [i] [min_cnt[i]])
Since the foregoing parameters are used, the destination output stage having the highest possibility that the cell cannot be transmitted because a deviation is caused in the cell transmission is checked with priority. Therefore, there is an effect of the reduction in the maximum delay time from when a cell is received by the input stage to when the cell is transmitted.
Also, when rearrangement based on the priority parameters is performed for each cell time slot, the following priority parameters are considered.
(a) The order starting from the largest value of max_cnt[i]−out_cnt[i][j]
(b) In addition to the above description, when the above values are equal to each other, the destination output stage having the smaller number of the intermediate stages is checked which have smaller values than the counter value out_cnt[i][j] (j′ satisfies out_cnt[i][j]>out_cnt[i][j′])
By using the foregoing parameter, the cell can be checked with priority, wherein the cell has the highest possibility that the cell cannot be transmitted because of a deviation caused in the cell transmission but the cell is transmitted to the intermediate stage j to improve the deviation.
A specific example of the cell transmitting process based on the priority parameter in the check order list will be described below.
At a time t=0, there is no reception of the cell, and a cell destined to the output stage 1 is transmitted. Thus, the priority parameter of the destination output stage 1 is decreased by 1.
At a time t=1, a cell destined to the output stage 1 is received, and the cell destined to the output stage 4 having the highest priority parameter next to the destination output stage 1 is transmitted. Thus, the priority parameter of the destination output stage 4 is decreased by 1.
At a time t=2, since the priority parameter of the destination output stage 4 is decreased by 1, the order between the destination output stage 3 and the destination output stage 4 is changed. Since the priority parameter is already 5 (the VOQ buffer length=5) in the cell destined to the output stage 1, the cell destined to the destination output stage 3 is received. Also, the cell destined to the output stage 2 having the highest priority parameter next to the destination output stage 4 is transmitted, and the priority parameter of the destination output stage 2 is decreased by 1. At this time, since the priority parameter of the destination output stage 2 becomes 0, the destination output stage 2 is erased from the list.
At a time t=3, since the destination output stage 2 is deleted from the list, the number of the destination output stages is three of 1, 3 and 4. Thus, a cell destined to the output stage 5 is newly received, and the cell destined to the output stage 1 having the highest priority parameter is transmitted.
At a time t=4, the cell destined to the output stage 5 having the lowest priority parameter is received, and the cell destined to the output stage 1 having the highest priority parameter is transmitted.
At a time t=5, the cell destined to the output stage 5 is received, and the priority parameter of the destination output stage 5 becomes higher than the priority parameter of the destination output stage 4. Thus, the order is changed. Also, since the priority parameter of the destination output stage 1 becomes lower than the priority parameter of the destination output stage 3, the order is changed. Thus, the cell destined to the output stage 3 is transmitted.
The allowable difference value in the load balanced type switching apparatus of the present invention is 1. In the load balanced type switching apparatus of the present invention, a small delay in the high load state is attained in cases that the numbers of the switch ports are 4 and 128. This reason is as follows. That is, in the load balanced type switching apparatus of the present invention, the input stage can transmit the cells without any waiting, as long as the deviation is not caused in the cells to be transmitted, and while the delay at the input stage is suppressed to the small value, the cells are uniformly distributed to the respective intermediate stages, and the delay for the waiting at the output stage can be reduced.
A second operation example of the load balanced type switching apparatus according to the first exemplary embodiment of the present invention will be described below. Here, an operation of the FOFF at the later stage will be described. In the second operation example, the operation of a transmitting cell selecting process is different in the first exemplary embodiment. In the second operation example, if the transmittable cell does not exist in the transmission counter as the result of the VOQ check, the VOQ buffer is again checked. If there are the M or more accumulation cells, in the M cell cycles therefrom, the cells are transmitted from the VOQ buffer of the specified same destination output stage. Since the output process is performed under the collection of the cells, the deviation does not occur in the number of the cells transmitted to any intermediate stage, as the result of the addition of this process.
Whether or not the transmittable cell exists is determined. In the first exemplary embodiment, there is a case of the reservation that the plurality of cells are transmitted at the same time. Thus, in each cell time slot, when the cell is already in the reservation state, the transmission determination is not required.
If the cell in the reservation state does not exist, whether or not there is a transmittable cell among the cells accumulated in the VOQ buffer is checked by using the transmission counter, similarly to the first exemplary embodiment of the present invention. At this time, the transmission cell determining section 23 checks whether or not there is cell having a certain destination output stage i and stored in the VOQ buffer, namely, whether or not there is the destination output stage in which voq_cnt[i]>0 and on which the check is not still performed. If there is not the foregoing output stage, the process is ended. This process is a same as the Step S201.
If there is such an output stage, whether or not the cell having the destination output stage i can be transmitted by use of a cell time slot in the current intermediate stage is determined. If it can be transmitted, the corresponding cell is transmitted, and then the process is ended. If it cannot be transmitted, whether or not there is a different destination output stage is again checked. Then, until the transmittable cell is found out, or until any cell targeted for the check is reduced to 0, the process is repeated. This process is same as the Step S202.
If there is not the transmittable cell, whether or not there is the destination output stage i in which the VOQ accumulation cell count voq_cnt[i] is equal to or greater than M that implies the number of the intermediate stages 2 is checked.
If there is the destination output stage i in which the M or more cells are accumulated in the VOQ buffer, the transmission of the M cells is reserved. At the step S304, if there are the plurality of destination output stages in which the M or more cells are accumulated, which of the cells is used is considered by using a randomly selecting method, a round robin selecting method, and a method of selecting the destination output stage having the greatest one in the number of the accumulated cells.
In the second operation example, even in the cell time slot in which it cannot be transmitted in the first exemplary embodiment, if the N or more cells are accumulated in the VOQ buffer associated with a certain output stage, the cells can be transmitted. Thus, the effect of the reduction in the delay time at the input stage of that part can be attained.
The second operation example of the load balanced type switching apparatus of the present invention will be described below. Here, the former stage FOFF operation will be described.
In the second operation example, whether or not there is the destination output stage i in which the VOQ accumulation cell number is M or more is checked (S302). In case of the existence, a process of reserving the transmission of the M cells (S303) is performed prior to the transmission determining processes (S304 and S305) that use the transmission cell counter.
Whether or not there is the transmittable cell is determined. In each cell time slot, when the cell is already in the reservation state, the transmission determination is not required.
If there is not the transmittable cell, whether or not there is the destination output stage i in which the VOQ accumulation cell count voq_cnt[i] is equal to or greater than M that implies the number of the intermediate stages 2 is checked.
If there is the destination output stage i in which the M or more cells are accumulated in the VOQ buffer, the transmission of the M cells is reserved.
If there is not any cell in the reservation state, similarly to the first exemplary embodiment, whether or not there is any transmittable cell of the cells accumulated in the VOQ buffer is checked by using the transmission counter. At this time, the transmission cell determining section 23 checks whether or not there is the VOQ accumulation cell having the destination output stage i, namely, whether or not there is the destination output stage in which voq_cnt[i]>0 and on which the check is not still performed. If there is not such an output stage, the process is ended.
If there is such an output stage, whether or not the cell having the destination output stage i can be transmitted in the current intermediate stage cell time slot is determined. If it can be transmitted, the corresponding cell is transmitted, and then the process is ended. If it cannot be transmitted, whether or not there is a different destination output stage is again checked. Then, until the transmittable cell is found out, or until the cell targeted for the check is reduced to 0, the process is repeated.
The M or more accumulated cells are outputted with priority. Thus, the larger number of accumulated cells are transmitted with priority, and the effect of the reduction in the longest delay time can be attained.
Next, the load balanced type switching apparatus according to a third exemplary embodiment of the present invention will be described below. Here, a counter resetting operation will be described. In the third exemplary embodiment, under the condition that a cell is not received (or transmitted) in a certain period, the counter values (out_cnt, maximum value max_cnt and minimum value min_cnt) are reset. Under the condition that the cell is not received in the certain period, the transmitted cell is assumed to already arrive at the output stage 3 through the intermediate stage 2. Thus, even if a variation occurs in the transmission counter for each intermediate stage associated with a certain destination output stage, the cell does not actually exist in the intermediate stage. Thus, it is assumed that any deviation does not exist in the accumulation cell number. Therefore, the values in the respective counters that are in the deviated states are reset, which leads to the situation that there is no deviation.
It should be noted that as the reset control of the counter, a method is considered of performing it on the whole irrespectively of the destination output stage. However, a method is considered of performing the reset control only on the destination output stage that does not receive (or transmit) a cell in a certain period, for each destination output stage.
Since the counter of the output stage that does not receive (or transmit) any cell in the certain period is reset, the situation that the counter value is still in the deviated state is prevented, which can reduce the possibility that the cell cannot be transmitted due to the deviation of the counter. Thus, the effect of the reduction in the delay time at the input stage can be obtained.
The load balanced type switching apparatus according to a fourth exemplary embodiment of the present invention will be described below. Here, the counter resetting operation will be described.
In the fourth exemplary embodiment, an empty cell (a cell data that actually has no content) is inserted into the cell time slot in which the transmitting of the cell is not performed. The meaning of inserting the empty cell is to relax a deviation with regard to the destination output stage in which the deviation has occurred. For this purpose, the empty cell should not be unnecessarily inserted. For example, there is a case that a difference between the maximum transmission count and the minimum transmission count is within the allowable difference value, and the number of the intermediate stages in the minimum transmission count is K/4 or less, and the intermediate stage j under the transmission schedule is in the minimum transmission count. These conditions are represented by the following equation.
min_cnt[i]−max_cnt[i]==Differential Allowable Value &&
num_cnt[i][min_cnt[i]]<K/4 &&
out_cnt[i][j]==min_cnt[i]
It should be noted that with regard to the insertion of the empty cell, two kinds of the method that an empty cell is actually inserted and the method that the counter is updated under an assumption that the empty cell is imaginarily inserted are considered.
The second exemplary embodiment of the present invention will be described below.
The input stage 101 is provided with a destination detecting section 21, an FIFO unit 122, a transmission cell determining section 123 and a control memory 24. The destination detecting section and the control memory are the same as those of the input stage 1 in
The FIFO unit 122 has only a single queue and transmits cells in an order of reception of reception cells. Also, the FIFO unit 122 notifies the data of the destination output stage of the head cell accumulated in the head of the queue to the transmission cell determining section 123.
The transmission cell determining section 123 is the same as the transmission cell determining section 23 in the first exemplary embodiment of the present invention, except that this determines the transmission of only the head cell of the FIFO unit 122 and notifies to the FIFO unit, whether or not it can be transmitted.
The transmission cell determining section 123 checks whether or not the cell is accumulated in a FIFO in the FIFO unit 122. If the cell is not accumulated in the FIFO, there is no cell targeted for the process. Thus, the process is ended.
If the cell is accumulated in the FIFO, whether or not the cell having the destination output stage i can be transmitted is determined. The process content is identical to that of the S202. If the cell can be transmitted, the cell transmission is requested. However, if it cannot be transmitted, the cell transmission is not requested, and the process is ended.
In the second exemplary embodiment of the present invention, instead of the VOQ unit 22, the FIFO unit 122 is used to simplify the circuit. Also, only one cell per cell time slot is always determined. Therefore, the cell transmission can be determined within the fixed time irrespectively of the number of the ports.
The third exemplary embodiment of the present invention will be described below.
The input stage 201 is provided with the destination detecting section 21, an FIFO unit 222, a transmission cell determining section 223 and the control memory 24. The destination detecting section and the control memory are the same as those of the input stage 1 in
The FIFO unit 222 separately manages a single waiting FIFO to accumulate a cell that cannot have been transmitted when it is received; and the cell immediately after the reception. The transmission cell determining section 223 can select and read the head cell in the FIFO and the cell immediately after the reception.
The transmission cell determining section firstly checks whether or not the cell is accumulated in the FIFO.
If it is accumulated, whether or not the head cell can be transmitted is checked. The process content is identical to that of the step S2-2.
If it can be transmitted, a transmission request of the head cell is issued, and the process is ended. If the transmission has not been done, whether or not there is the cell immediately after the reception is checked.
If there is the cell immediately after the reception, whether or not the cell in the same destination output stage exists in the FIFO is checked.
If there is no cell immediately after the reception, the process for determining whether or not the corresponding cell can be transmitted is performed. The process content is identical to that of the step S2-2. If the transmission is determined to be possible, the process of transmitting the reception cell is performed.
In the third exemplary embodiment of the present invention, similarly to the second exemplary embodiment of the present invention, instead of the VOQ unit 22, the FIFO unit 122 is used. Accordingly, the circuit configuration is simplified. Also, the transmission of the cell is determined two times per cell time slot at maximum. Thus, irrespectively of the number of the ports, the transmission of the cell can be determined within a predetermined time.
It should be noted that the mesh connection section 4 between the input stages 1 and the intermediate stages 2 shown in
Finally, features of the load balanced type switching apparatus of the present invention will be described below in detail.
The load balanced type switching apparatus of the present invention is provided with L input stages, M intermediate stages, N output stages, a mesh connection section for connecting the respective input stages and intermediate stages in the mesh manner; and a mesh connection section for connecting the respective intermediate stages and output stages in the mesh manner. In a process for distributing reception cells to the respective intermediate stages, the input stage performs the process of distributing cells so as to manage the transmission counter value out_cnt[i] [j] for each intermediate stage j and each destination output stage i so that for each destination output stage, the number of the cells transmitted to each intermediate stage falls in the certain range.
In the transmission cell determining section in each input stage, in a process of determining whether or not the cell destined to the destination output stage i can be transmitted to the intermediate stage j, this manages the maximum value max_cnt[i] and the minimum value min_cnt[i] in the transmission counter to each intermediate stage for each destination output stage i, and determines the cell to be transmittable if the difference between the maximum value and the minimum value is a value smaller than an allowable difference value or if the value of the transmission counter out_cnt[i][j] to the intermediate stage j does not become the maximum value max_cnt[i].
With regard to the respective parameters max_cnt, min_cnt and out_cnt, the value of K which exhibits K>the allowable difference value is used to manage them as the values (the remainders when the respective parameters are divided by K) after the module K calculation.
For each destination output stage i, the distribution of the count value (out_cnt[i][j]) to each intermediate stage j after module K calculation is managed in the counter distribution cnt_num [i][ ].
In the process of updating min_cnt[i], when the number of the intermediate stages having the minimum value min_cnt[i] is 1 (=cnt_num [i][min_cnt[i]]==1) and the transmission counter to the intermediate stage j for sending the cell coincides with min_cnt[i], min_cnt[i] is updated.
In the input stage, this is provided with the destination detecting unit, the VOQ unit, the transmission cell determining section and the control memory, and the transmission cell determining section selects one transmittable cell from the cells accumulated in the VOQ unit.
The input stage is provided with the destination detecting unit, a FIFO unit, the transmission cell determining section and the control memory, and the transmission cell determining section determines whether or not the cell accumulated in the head of the FIFO unit can be transmitted.
The input stage is provided with the destination detecting unit, the FIFO unit, the transmission cell determining section and the control memory. The FIFO unit has a function of accumulating the cell, which cannot be transmitted at the time of the reception, in the FIFO unit and separately manages the cells immediately after the reception. The transmission cell determining section has a function of specifying and reading the head cell in the FIFO unit or the cell immediately after the reception. Also, the transmission cell determining section determines whether or not the head cell in the FIFO unit can be transmitted, transmits the head cell in the FIFO unit if it can be transmitted, and determines whether or not the reception cell can be transmitted, if it cannot be transmitted.
The transmission reservation of a plurality of cell time slots can be performed in one cell time slot. When the cell is transmitted to a certain destination output stage i and when there are the plurality of cells accumulated in the VOQ buffer, the plurality of cells are continuously transmitted to the same destination output stage i. With regard to the destination output stage i for the transmission check, when there are the plurality of cells in the VOQ buffer and when the difference between the maximum value and the minimum value (max_cnt[i]−min_cnt[i]) is smaller than a allowable difference value, the transmission reservation is continuously performed on the plurality of cell time slots.
A process of selecting a transmittable cell from the cells accumulated in the VOQ buffer checks the destination output stages i in a random order. The process of selecting the transmittable cell from the cells accumulated in the VOQ buffer may check the destination output stages i in the order of a round robin method. In addition, the process of selecting the transmittable cell from the cells accumulated in the VOQ buffer checks the destination output stage of the cells in the VOQ buffer with higher priorities than the destination output stage of the cells immediately after the reception.
When the transmittable cell does not exist from the transmission counter value and when the destination output stage, in which the cells equal to or greater than K implying the number of the intermediate stages are accumulated, exists in the VOQ unit, the K cells in the output stage are continuously transmitted. Also, when the destination output stage, in which the cells equal to or more than K implying the number of the intermediate stages are accumulated, exists in the VOQ unit, the K cells in the destination output stage are continuously transmitted, and only when such a cell does not exist, the process of distributing the cells is performed in accordance with the transmission counter value.
A process of selecting a transmittable cell from the cells accumulated in the VOQ buffer, uses the list targeted for the check and sequentially checks from the head of the list. Also, only the destination output stage in which the cell is accumulated in the VOQ buffer is included in the list.
When the destination output stage of the cell to be transmitted is determined, the destination output stage is once removed from the list and if the cell remains in the VOQ unit, it is re-added to the tail of the list. Also, the possession of the priority parameter to determine an order of the list of the check target.
As the priority parameter, the number of the cells accumulated in the VOQ unit is used to preferentially check the cell in the destination output stage having the great number of the cells accumulated in the VOQ. Also, as the priority parameter, the difference between the maximum value and the minimum value (max_cnt[i]−max_cnt[i]) is used to preferentially check the cell in the destination output stage having the high priority parameter.
Although as the priority parameter, the cell in the destination output stage having the great difference (max_cnt[i]−max_cnt[i]) between the maximum value and the minimum count is used with a priority level, if the difference between the maximum count and the minimum count (max_cnt[i]−max_cnt[i]) is equal to each other, the cell in the destination output stage which has the small number (=cnt_num [i][min_cnt[i]] of the intermediate stages that is the minimum count value is checked with priority.
When the cell is transmitted to the intermediate stage j as the priority parameter, the cell in the destination output stage in which max_cnt[i]−out_cnt[i][j] is great is checked with priority. Also, when the cell is transmitted to the intermediate stage j as the priority parameter, the cell in the destination output stage in which the difference is great is checked with priority, and if the differences are equal to each other, the cell in the destination output stage having the small number of the intermediate stages, in which the count value is smaller than out_cnt[i][j] (j′ is out_cnt[i][j]>out_cnt[i][j′]) is checked with priority.
A process of each cell time slot in an updating process of the check target list updates only the check order of the received or transmitted cells in the destination output stage i. Also, a process of each cell time slot in the updating process of the check target list rearranges the check target list for each cell time slot.
The possession of a function of resetting the transmission counters, when the cell is not received in the certain period. The possession of the function of monitoring the reception interval of the cells for each destination output stage and resetting the value of the transmission counter in the destination output stage, when the cell is not received in the certain period. Moreover, the possession of a function of resetting the transmission counter values, when the cell is not transmitted during a certain period. The possession of a function of monitoring a transmission interval of the cells for each destination output stage and resetting the transmission counter value in the destination output stage, when the cell is not transmitted in the certain period.
If as the result of the determination using the transmission counter, there is no cell targeted for the transmission, the counter value is updated under the assumption that the cell is imaginarily transmitted to a certain destination output stage. Also, the process, which updates the counter value under the assumption that the cell is imaginarily transmitted, transmits the empty cell whose content is invalid.
As mentioned above, in the present invention, the input stage counts the number of cells, which are transmitted to the respective intermediate stages, for each output stage, and carries out the control so that the difference between the intermediate stages satisfies the allowable difference value. If the difference does not exceed the allowable difference value, the received cell is immediately transmitted to the intermediate stage. Thus, it is possible to attain the uniformly dispersing process for the intermediate stages, while reducing the delay at the input stage.
Each of the input stages in the load balanced type switching apparatus counts the number of the cells transmitted to each intermediate stage for each destination output stage, and carries out a control so that the number of the cells transmitted to each intermediate stage for each destination output stage falls within a certain range, and uniformly disperses the cells.
Each of the input stages can send the cells to the intermediate stages at the delay of 0, without any waiting for the received cells, in the situation that the number of the cells transmitted to each intermediate stage falls within the certain range. Thus, the number of the intermediate stages to which the cells can be transmitted is not limited to one location. Hence, while the delay at the input stage is reduced, the uniform dispersion to the intermediate stages can be attained.
Although the present invention has been described above in connection with several exemplary embodiments thereof, it will be apparent by those skilled in the art that those exemplary embodiments are provided solely for illustrating the present invention, and should not be relied upon to construe the appended claims in a limiting sense.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-188930 | Jul 2006 | JP | national |
