Patent Application
20190253357
Packet processing systems typically provision a number of “worker” processing threads running on processor cores (sometimes called “worker cores”) to perform the processing work of packet processing applications. Worker cores consume packets from dedicated queues which in some scenarios is fed by one or more network interface controllers (NICs), by input/output (I/O) threads, or by other processing threads.
Load balancers typically make decisions about processor core workload and where to add packets to queues based on the current length of the queue(s) being serviced by a core (e.g., length being measured by the number of packets in the queue(s) to be processed). Another approach is to make the decisions based on the total number of bytes of packets in each queue. A load balancer typically schedules the next packet to a queue with the least number of packets or bytes. Some packets could result in higher workloads, thereby taking longer times to process. The assumption that processing workloads is proportional to the number of packets in the queue and/or the total number of bytes in packets in the queue is not necessarily true. The load balancer has no information about the actual time anticipated to process the packets in a queue. If load balancing for the packet processing system is done solely based on queue lengths or number of bytes of packets in the queue, multiple high workload packets can get scheduled onto a shorter length/smaller byte count queue. Any subsequent packets (especially including time sensitive packets) now getting scheduled to this queue due to the queue's shorter length/smaller byte count may face increased latency. This results in occasional spikes in latency experienced in the packet processing system.
Embodiments of the present invention provide an approach for load balancing of processing cores. Embodiments provide for packet processing applications to identify and/or mark packets with an associated processing load factor called a processing weight herein. In an embodiment, the processing weight field is included in packet metadata. With this added processing weight field, a load balancer makes better packet scheduling decisions based at least in part on actual or anticipated processing loads of packets waiting in queues instead of assuming core workloads are proportional to current sizes of queues (e.g., either lengths or byte counts) assigned to the cores. This results in better overall system latency times and improved core utilization. Embodiments can be used in deploying “cloudified” applications in data center systems that can scale up and down in size and provide more efficient packet processing operations.
Embodiments of the present invention leverage a load balancing capability of a hardware queue manager (HQM) to assign packets to queues based at least in part on processing weights of packets to improve efficiency while maintaining performance (e.g., throughput and latency) requirements. A worker thread is a consumer from the HQM and packet processing work is distributed amongst the worker threads on the worker cores based at least in part on the processing weight factor.
Although the data units being processed in embodiments of the present invention are described as packets and associated packet metadata, the concepts described herein are also applicable to any data units (e.g., bitstreams of data) or tasks to be processed by a computing platform.
According to some examples, computing platform 101, as shown in
In some examples, computing platform 101, includes but is not limited to a server, a server array or server farm, a web server, a network server, an Internet server, a work station, a mini-computer, a main frame computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, multiprocessor systems, processor-based systems, a laptop computer, a tablet computer, a smartphone, or a combination thereof. In one example, computing platform 101 is a disaggregated server. A disaggregated server is a server that breaks up components and resources into subsystems and connects them through network connections. Disaggregated servers can be adapted to changing storage or compute loads as needed without replacing or disrupting an entire server for an extended period of time. A server could, for example, be broken into modular compute, I/O, power and storage modules that can be shared among other nearby servers.
Circuitry 120 having processing cores 122-1 to 122-m may include various commercially available processors, including without limitation Intel® Atom®, Celeron®, Core (2) Duo®, Core i3, Core i5, Core i7, Itanium®, Pentium®, Xeon® or Xeon Phi® processors, ARM processors, AMD processors, and similar processors. Circuitry 120 may include at least one cache 135 to store data.
Uncore 182 describe functions of a processor that are not in processing cores 122-1, 122-2, . . . 122-m, but which are closely connected to the cores to achieve high performance. Cores contain components of the processor involved in executing instructions, including the arithmetic logic unit (ALU), the floating-point unit (FPU) and level one and level two caches. In contrast, in various embodiments, uncore 182 functions include interconnect controllers, a level three cache, a snoop agent pipeline, an on-die memory controller, and one or more I/O controllers. In an embodiment, uncore 182 is resident in circuitry 120. In an embodiment, uncore 182 includes last level cache 135.
According to some examples, primary memory 130 may be composed of one or more memory devices or dies which may include various types of volatile and/or non-volatile memory. Volatile types of memory may include, but are not limited to, dynamic random-access memory (DRAM), static random-access memory (SRAM), thyristor RAM (TRAM) or zero-capacitor RAM (ZRAM). Non-volatile types of memory may include byte or block addressable types of non-volatile memory having a 3-dimensional (3-D) cross-point memory structure that includes chalcogenide phase change material (e.g., chalcogenide glass) hereinafter referred to as “3-D cross-point memory”. Non-volatile types of memory may also include other types of byte or block addressable non-volatile memory such as, but not limited to, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magneto-resistive random-access memory (MRAM) that incorporates memristor technology, spin transfer torque MRAM (STT-MRAM), or a combination of any of the above. In another embodiment, primary memory 130 may include (but is not limited to) one or more hard disk drives within and/or accessible by computing platform 101.
Computing platform 101 includes hardware queue manager (HQM) 180 to assist in managing queues of data units such as packets and/or packet metadata. In an embodiment, the data units are packets to be transmitted to and/or received from network I/O device 110, and also packets exchanged between cores. In another embodiment, the data units include timer events. In an embodiment, HQM 180 is part of circuitry 120. In another embodiment, HQM 180 is part of uncore 182.
In an embodiment, uncore 182 includes a plurality of consumer queues CQ 1204, CQ 2206, . . . CQ N 208, where N is a natural number, stored in cache 135. Each consumer queue stores zero or more blocks of metadata. In an embodiment, a block of metadata is a packet descriptor including information describing a packet. In one embodiment, there is a one to one correspondence between each worker core and a consumer queue. For example, worker core 1210 is associated with CQ 1204, worker core 2212 is associated with CQ 2206, and so on until worker core N 214 is associated with CQ N 208. However, in other embodiments there may be a plurality of consumer queues per worker core. In yet another embodiment, at least one of the worker cores is not associated with a consumer queue. The sizes of the consumer queues may all be the same or may be different in various embodiments. The sizes of the consumer queues are implementation dependent. In at least one embodiment, the consumer queues store metadata describing packets, but not the packets themselves (since the packets are stored in one or more of primary memory 130, cache 135, and storage devices 165 while being processed after receipt from network I/O device 110). In an embodiment, the metadata includes a processing weight field for each packet.
HQM 180 distributes packet processing tasks to enabled worker cores 210, 212, . . . 214 by adding packet descriptors to consumer queues CQ 1204, CQ 2206, . . . CQ N 208 in uncore 182. HQM 180 acts as a traffic buffer smoothing out spikes in traffic flow. HQM 180 performs load balancing while considering flow affinity. Disabled worker cores are not allocated any traffic when disabled and can enter low power states semi-statically, or be switched to other duties.
In an embodiment, processing proceeds as follows. DSI core 216 enqueues packet descriptors (e.g., packet metadata) to HQM 180 via uncore 182. HQM 180 distributes (i.e., load balances) packet descriptors to active consumer queues CQ1204, CQ 2206, . . . CQ N 208 in uncore 182, based at least in part on processing weight fields of packets. Worker cores 210, 211, . . . 214 get packet descriptors from corresponding consumer queues for packet processing. Worker cores with nothing to do (i.e., there are no packet descriptors in their consumer queues to be processed), go to sleep.
In an embodiment, classifier 503 is implemented as software running on DSI core 216. In another embodiment, classifier 503 is part of application 160 (running on any core of the packet processing system), when application 160 generates or forwards data units, such as packets, from one application to another application (whether running on the same core or a different core). In a further embodiment, classifier 503 is implemented in hardware circuitry as part of HQM 180. In yet another embodiment, classifier 503 is implemented in hardware circuitry as part of network I/O device 110, when network I/O device processes newly arrived data packets from network 170.
The entity within the packet processing system that sets the processing weight of a packet is implementation dependent. In various embodiments, the entity is application 160, an external application that sent the packet, network I/O device 110, an operating system (OS), a network interface controller (NIC) driver software, other entities across network 170, or classifier 503. Classifier 503 receives incoming data 502 (such as packets) and classifies the data before forwarding the data to load balancer 504. In an embodiment, an application 160 generating or forwarding the packet can set the processing weight of the packet. The factors and/or information used in setting the processing weight is implementation dependent and may vary across packet processing systems. Generally, the factors and/or information can include any data allowing data units such as packets to be typed or grouped based at least in part on known and/or anticipated processing loads when packets are processed by cores. For example, one factor could be processing time to process a packet on a core. Application 160 can determine which packets will trigger a high processing load and can adjust the processing weight of packets accordingly. The processing weight field in packet metadata can also be added/modified before sending or forwarding such packets. In another embodiment, network I/O device 110 and/or network I/O device driver 140 can set the processing weight of packets received from network 170 based at least in part on application-configured lookup tables (not shown in
When a packet is received, classifier 503 classifies the packet, assigns a classification value and stores the classification value in classification field 412 of packet metadata 408. Based at least in part on the classification, classifier 503 assigns a processing weight for the packet and stores the processing weight in processing weight field 410 of packet metadata 408. In an embodiment, classifier 503 adjusts the processing weight based at least in part on packet type using an application-configured lookup table (not shown in
Load balancer 504 generates an estimate of total processing load of a queue by considering associated packet processing weights. In embodiments of the present invention, load balancer 504 load balances based at least in part on this processing weight load estimate instead of based on queue lengths or byte counts. The entity within the packet processing system that implements load balancer is implementation dependent. In various embodiments, the entity is application 160, an external application that sent the packet, network I/O device 110, an operating system (OS), a network interface controller (NIC) driver software, other entities across network 170, or classifier 503.
In one embodiment, each packet can carry a default processing weight of 1 and thus the packet processing system will behave identically to current load balancers. (e.g., the total processing weight of a queue equals the number of packets in the queue). In other embodiments, other default processing weight values may be used.
Processing intensive packets are assigned a processing weight greater than 1. This will result in the queue holding these packets as being viewed as having a higher total processing weight estimate compared to other queues holding the same number of default processing weight packets (i.e., packets with processing weights of 1). Load balancer 504 will automatically reduce packet flow to the queues with high processing weight packets, thereby resulting in lower latencies and fairer load balancing for the entire packet processing system.
There are some packets which can trigger events like statistic collections, periodic cleanup, maintenance, etc., which are time consuming activities. To promote greater efficiency in the packet processing system, when these packets are queued, other packets are not added to those queues until they are consumed since the potential for newly added packets to those queues experiencing a larger latency is high. This scenario cannot be avoided with a queue length-based or byte-based load balancer. In embodiments of the present invention, a large processing weight can be added to such packets, effectively stopping any further scheduling to those queues until the high processing weight packets have been consumed.
In an embodiment, classifier 503 is included in the packet processing system to classify packets based on type of application and assign or modify processing weights based at least in part on packet type. In this embodiment, the application provides the packet type information to the classifier to aid in processing load mapping of packets to queues.
In case of atomic flows, if a flow is locked to a core, then load balancing is not done based on queue processing weights. Instead, the atomic flow's affinity to the locked core is used for scheduling. If atomic flow is unlocked, then queue processing weights can be used to switch a packet flow to queue for a new core with a lower processing weight.
Packet re-ordering is performed in a second stage of packet processing where processed packets are enqueued back by the core. Thus, re-ordering is not affected by the present approach. This approach helps in calculating better estimates of queue processing weights for fairer load balancing and lower latencies.
Load balancing is based on computing the processing weight of all packets in each queue. This results in an estimated queue total processing weight. Queues with higher total processing weights will not be allowed to be built up with additional packets as compared to other queues with low total processing weight.
If a queue only has regular packets (processing weight=1), total processing weight will be same as queue length. Thus, if required, an existing packet processing model already in use can be fully supported by embodiments of the present invention.
A large processing weight can be added to a packet to block any more packet scheduling to a queue behind such packets.
In an embodiment, a signal indicating early completion may be sent by a core when the core determines the core is nearing the end of processing of packets in a queue. The core can then drop the extra queue weight early and allow the load balancer to queue more packets to the core's queue.
Load balancer 504 receives incoming data 502 (such as packets and/or associated metadata, for example) from classifier 503. Load balancer 504 determines which queue of consumer queues CQ1204, CQ2206, CQ3207, . . . CQN 208 is to receive a new packet for processing by assigned worker cores 210, 212, 213, . . . 214, respectively.
In this example, CQ1204 has five entries, each entry having a normal processing weight of 1. Thus, at this point in time CQ 1204 has a length of 5 and a total processing weight of 5. CQ 2206 has four entries, with three entries having a normal processing weight and one entry having a processing weight of 5. The packet in the entry with processing weight of 5 is expected to take five times longer to process as compared to a packet with a processing weight of 1. Thus, at this point in time CQ 2206 has a length of 4 and a total processing weight of 8. CQ 3207 has seven entries, each entry having a normal processing weight of 1. Thus, at this point in time CQ 3207 has a length of 7 and a total processing weight of 7. Finally, CQ N 208 has eight entries, each entry having a normal processing weight of 1. Thus, at this point in time CQ N 208 has a length of 8 and a total processing weight of 8. With a traditional queue length-based load balancer, the next packet to be enqueued will get added to CQ 2206 as this queue has the least number of queue entries (four in this example). But the newly queued packet to CQ 2206 will experience higher latency because CQ 2206 already has a packet in the queue with a processing weight of 5, which will take longer to process. With a processing weight-based load balancer of embodiments of the present invention, the next packet will be added to CQ 1204 instead of CQ 2206 because CQ 1204 has a lowest total processing weight (e.g., 4) of any queue. This next packet will experience a lower latency as compared to the traditional queue length-based load balancer.
In one embodiment, at block 606, classifier 503 determines a load balancing queue group based at least in part on the packet classification. In one embodiment, a load balancing queue group is a collection of queues (i.e., CQs 204, 206, 207, . . . 208) grouped together. In one embodiment, every packet that needs load balancing is mapped to a queue group (e.g., a group of consumer queues to which the packet needs to be load balanced). A queue group is defined by an identification number which corresponds to group of consumer queues. When a configuration is one consumer queue per core, a queue group maps to load balancing across associated cores. A queue group is configured by the application. Classifier performs the classification operation and based on the classification, the packet is assigned to a particular queue group inside load balancer.
It is a common practice in some computing systems to limit certain packet processing to a subset of available cores. This is typically done using core masks. In some cases, the behavior of a subset of queues is different (atomic vs. ordered vs. unordered queues). Thus, it may be desirable to form a queue group to process a set of queues together.
In one embodiment, load balancing queue groups are omitted, and all queues are considered individually.
At block 608, load balancer 504 computes a total processing weight of each queue in a load balancing queue group. The total processing weight of a queue is the sum of the processing weights of all packets in the queue. At block 610, load balancer assigns the packet to the queue with the lowest total processing weight in the load balancing queue group.
In one embodiment, blocks 602 through 610 are performed in sequence for each received packet. In another embodiment, blocks 602-606 of classifier 503 are processed repeatedly (i.e., as each packet is received) independently and in parallel of blocks 608-610 of load balancer 504. In this case, load balancer 504 assigns a plurality of packets to queues in a “batch” mode, handling a plurality of packets at a time independently of classifier 503 classifying packets.
According to some examples, processing component 802 may execute processing operations or logic for instructions stored on storage medium 700. Processing component 802 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software elements may include software components, programs, applications, computer programs, application programs, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given example.
In some examples, other platform components 804 may include common computing elements, such as one or more processors, multi-core processors, co-processors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input/output (I/O) components (e.g., digital displays), power supplies, and so forth. Examples of memory units may include without limitation various types of computer readable and machine readable storage media in the form of one or more higher speed memory units, such as read-only memory (ROM), random-access memory (RAM), dynamic RAM (DRAM), Double-Data-Rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), types of non-volatile memory such as 3-D cross-point memory that may be byte or block addressable. Non-volatile types of memory may also include other types of byte or block addressable non-volatile memory such as, but not limited to, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level PCM, resistive memory, nanowire memory, FeTRAM, MRAM that incorporates memristor technology, STT-MRAM, or a combination of any of the above. Other types of computer readable and machine-readable storage media may also include magnetic or optical cards, an array of devices such as Redundant Array of Independent Disks (RAID) drives, solid state memory devices (e.g., USB memory), solid state drives (SSD) and any other type of storage media suitable for storing information.
In some examples, communications interface 806 may include logic and/or features to support a communication interface. For these examples, communications interface 806 may include one or more communication interfaces that operate according to various communication protocols or standards to communicate over direct or network communication links or channels. Direct communications may occur via use of communication protocols or standards described in one or more industry standards (including progenies and variants) such as those associated with the PCIe specification. Network communications may occur via use of communication protocols or standards such those described in one or more Ethernet standards promulgated by IEEE. For example, one such Ethernet standard may include IEEE 802.3. Network communication may also occur according to one or more OpenFlow specifications such as the OpenFlow Switch Specification.
The components and features of computing platform 800, including logic represented by the instructions stored on storage medium 700 may be implemented using any combination of discrete circuitry, ASICs, logic gates and/or single chip architectures. Further, the features of computing platform 800 may be implemented using microcontrollers, programmable logic arrays and/or microprocessors or any combination of the foregoing where suitably appropriate. It is noted that hardware, firmware and/or software elements may be collectively or individually referred to herein as “logic” or “circuit.”
It should be appreciated that the exemplary computing platform 800 shown in the block diagram of
Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASIC, programmable logic devices (PLD), digital signal processors (DSP), FPGA, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation.
Some examples may include an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.
Some examples may be described using the expression “in one example” or “an example” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The appearances of the phrase “in one example” in various places in the specification are not necessarily all referring to the same example.
Included herein are logic flows or schemes representative of example methodologies for performing novel aspects of the disclosed architecture. While, for purposes of simplicity of explanation, the one or more methodologies shown herein are shown and described as a series of acts, those skilled in the art will understand and appreciate that the methodologies are not limited by the order of acts. Some acts may, in accordance therewith, occur in a different order and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all acts illustrated in a methodology may be required for a novel implementation.
A logic flow or scheme may be implemented in software, firmware, and/or hardware. In software and firmware embodiments, a logic flow or scheme may be implemented by computer executable instructions stored on at least one non-transitory computer readable medium or machine readable medium, such as an optical, magnetic or semiconductor storage. The embodiments are not limited in this context.
Some examples are described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
It is emphasized that the Abstract of the Disclosure is provided to comply with 37 C.F.R. Section 1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single example for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed example. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively. Moreover, the terms “first,” “second,” “third,” and so forth, are used merely as labels, and are not intended to impose numerical requirements on their objects.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
