Patent Grant
7586467
The present invention relates to a load drive circuit and integrated circuit suitable for use in the scan driver and address driver of a plasma display, and to a plasma display using those circuits.
An example of the load drive circuit for use in the scan driver and address driver of the plasma display is a switching circuit disclosed in JP-A-06-120794. This load drive circuit has a high blocking voltage MOS transistor of which the gate voltage can be reduced to a lower value than the power source voltage. Thus, the semiconductor devices for this circuit can be produced at low cost. In this load drive circuit, in order to make the output level to the load “L” (low), a MOS transistor connected in parallel to the load is turned on, and in conjunction with the operation of that transistor, another MOS transistor connected at the high-potential side in series with the load is turned on. In order to turn on this high-potential side MOS transistor, it is necessary that an input signal be inverted by a level shift circuit that is formed of an input-purpose MOS transistor and input-purpose impedance and transmitted to the gate of the high-potential side MOS transistor. On the other hand, in order to make the output level to the load “H” (high), the MOS transistors are turned on/off contrary to the above.
Other examples of the load drive circuit are disclosed in, for example, JP-A-05-344719 and JP-A-09-200017. These drive circuits have, in addition to the main power source to the load, another power source for a flip-flop that is floated from the reference potential (for example, the ground potential) at one terminal of the load. This floating power source is used to drive the high-potential side MOS transistor. Specifically, the states of the flip-flop circuit are switched by the output from the above-given level shift circuit that has the switching element that is turned on/off by the pulse-shape input signal, and the gate (base) of the high-potential MOS transistor is controlled by one of the outputs of the flip-flop.
In the load drive circuit of JP-A-06-120794, when the output to the load is in “L” level period, a penetrating current flows from the power source terminal to the reference potential (the ground potential) through the impedance and MOS transistor. Therefore, when the “L” output period is long and when the voltage to the load is high, a problem of much loss occurs. In addition, since the penetrating current must be increased in order to switch at high speed, the loss increases.
In the load drive circuits of JP-A-05-344719 and JP-A-09-200017, even if the voltage to the load becomes “H” and the high-voltage side terminal potential of the floating power source is increased, the penetrating current is a pulse-like current and hence causes less loss. Therefore, even if the potential of the floating power source becomes high or when the switching speed is increased, the loss can be reduced. However, since a separate floating power source is necessary, the circuit arrangement becomes complicated. Particularly when the number of load drive circuits is increased because of necessity of a plurality of the output terminals, the number of the necessary floating power sources is the same as that of the output terminals, and hence it is difficult to integrate the load drive circuits. This problem is significant particularly in the plasma display that uses high source voltages and a large number of separate load drive circuits.
It is an object of the invention to provide a load drive circuit with a simple structure and low loss.
It is another object of the invention to provide a small-sized plasma display with low loss.
According to one aspect of the invention, there is provided a load drive circuit having a main circuit formed of first and second semiconductor switching elements that are connected in series with a main power source and of a load with which the second semiconductor switching element is connected in parallel, a switching command circuit that generates two pulse signals as switching commands to supply voltages to the load, a bistable circuit that receives the two pulse signals, switches between two stable states in response to the pulse signals, and holds the gate-emitter voltage of the first switching element at either one of the high and low voltages, and a control circuit that responds to the two pulse signals to control the second switching element to be turned on/off complementarily with the first switching element, wherein the power source to the bistable circuit is supplied from the main power source or another power source connected at the fixed potential point of the main power source, and the potential at the positive terminal of the power source to the bistable circuit is retained higher than that at the positive terminal of the main power source.
In a desirable embodiment of the invention, the power source to the switching command circuit that supplies the switching commands to the bistable circuit is also the same as that to the bistable circuit.
According to another aspect of the invention, there is provided a load drive circuit in which the power source to the bistable circuit is supplied through the switching command circuit from the main power source or another power source connected at the fixed potential point of the main power source.
According to still another aspect of the invention, there is provided a load drive circuit in which discharge blocking means is provided that blocks the voltage held within the bistable circuit and/or between the gate and emitter of the first main switching element from being discharged through the first main switching element when the reference potential of the bistable circuit is floated at the positive potential of the main power source.
A load drive circuit according to another preferred embodiment of the invention has first and second n-type IGBTs connected in series with a main power source, a load with which the second n-type IGBT is connected in parallel, a switching command circuit that includes p-type MOS transistors and generates two pulse voltages as switching commands to supply voltages to the load, a bistable circuit that switches between two stable states in response to the two pulse voltages as input power sources and that holds the gate-emitter voltage of the first n-type IGBT at either one of the high and low voltages, a control circuit that controls the second n-type IGBT to be turned on/off complementarily with the first n-type IGBT in synchronism with the two pulse voltages, and backflow blocking means that connect the source terminals of the p-type MOS transistors of the switching command circuit to the main power source.
According to desirable embodiments of the invention, it is possible to provide a low-loss and simple load drive circuit.
According to other desirable embodiments of the invention, it is possible to provide a small-sized and low-loss plasma display.
The other objects and features of the invention will be apparent in the following description of the embodiments.
Embodiments of the invention will be described in detail with reference to the accompanying drawings.
Next, a control circuit will be mentioned. First, the control circuit has a switching command circuit 4 that issues commands to supply a high or low voltage as the output voltage to the load 3, and a bistable circuit 5 of which the bistable states are switched by the pulse outputs from this switching command circuit 4 and one output of which is supplied to the gate-emitter path of the IGBT 21. This control circuit also has a gate drive circuit 6 that drives the IGBT 22 to turn on/off on a complementary basis relative to the IGBT 21.
The switching command circuit 4 is formed chiefly of a pulse circuit 41 for generating the switching command pulses, and a pair of switching elements, for example, n-type MOS transistors 421 and 422 that are turned on like a pulse shape by the command pulses. In addition, the switching command circuit 4 also has resistors 431 and 432 through which these switching elements 421 and 422 are connected to the power source terminal HVC, and Zener diodes 441 and 442 for clamping the voltages across them.
The bistable (flip-flop) circuit 5 has a pair of switching elements, for example, p-type MOS transistors 511 and 512 that are supplied with power from the power source positive pole HVC and turned on by the pulse signals from the switching command circuit 4. The bistable circuit 5 also has a pair of switching elements, for example, n-type MOS transistors 521 and 522 that are switched to either one of the bistable states by these signals. In addition, Zener diodes 531 and 532 are connected across the switching elements 521 and 522, respectively. Both ends of the switching element 521 that acts as one output terminal of the bistable circuit 5 are respectively connected to the gate and emitter of the main IGBT 21.
In addition, the bistable circuit 5 is connected through a discharge prevention circuit (discharge blocking means) 7, which will be described later, to the power source positive pole HVC. Specifically, this discharge prevention circuit 7 has diodes 71 and 72 for preventing the reverse current flow.
The operation will be described next. In this embodiment, a signal G1 from the pulse circuit 41 causes a high voltage to be applied to the load 3, and similarly a signal G2 causes the voltage across the load 3 to be switched to a low (zero) voltage. First, when the pulse circuit 41 generates the pulse signal G1, the switching element 421 is turned on for only a short time, thus causing a pulse-shaped voltage to produce across the resistor 431 of which the upper end is at the positive potential. Therefore, the switching element 511 of the bistable circuit 5 is turned on for only a short time, so that the bistable-switching element 521 is turned off while the switching element 522 is turned on. Thus, a voltage is applied between the base and emitter of the main switching element 21 to turn it on. On the other hand, the gate drive circuit 6 produces an output voltage of “L” in synchronism with the generation of the pulse signal G1, thus causing the main switching element 22 to be turned off. Consequently, the potential of the output terminal VO becomes “H”, and thus the main supply voltage is applied across the load 3.
When the voltage to the load 3 is switched to “L”, the pulse circuit 41 generates the pulse signal G2. At this time, the switching element 422 is turned on for only a short time, thus causing a pulse-shaped voltage to be developed across the resistor 432 of which the upper end is at the positive potential. Therefore, the switching element 512 of the bistable circuit 5 is turned on for only a short time, so that this time the switching element 522 is turned off while the switching element 521 is turned on. Consequently, the main switching element 21 has “L” across its base-emitter path, and thus switches to the off state. On the other hand, the gate drive circuit 6 produces an output voltage of “H” in synchronism with the generation of the pulse signal G2, thus causing the main switching element 22 to turn on. Consequently, the potential of the output terminal VO becomes “L”, or the reference potential VB, so that the supply voltage to the load 3 is zero.
The retaining operation of the bistable circuit 5 and so on under the condition in which the voltage of main power source 1 is applied to the load 3 will be now described. The switching command circuit 4 only causes the above-mentioned pulse-shaped voltage to be developed across the resistor 431, and hence the switching element 511 within the bistable circuit 5 is turned on for only a short time. Therefore, when the n-type MOS transistor 522 as one of the switching elements for the bistable purpose is turned on while the other n-type MOS transistor 521 is turned off, the voltage across the transistor 521 becomes “H”. This state can be maintained by the stray capacitance between the gate and source. In addition, this voltage is also applied between the base and emitter of the main IGBT 21, and maintained by the stray capacitance between the base and emitter of this main IGBT 21.
However, if a p-type LDMOS structure having a body diode between the source and drain electrodes were employed as the switching element 511 in place of the p-type MOS transistor, the following problem might occur in the absence of the discharge prevention circuit 7. That is, when the output terminal voltage VO is turned “H”, the electric charges on the gate of the main IGBT 21 would be discharged through the body diode of the p-type LDMOS structure 511 and main IGBT 21. In other words, the output terminal VO, or the reference potential of the bistable circuit 5 would be raised up to the positive terminal HVC of the main power source, thus the source voltage to the bistable circuit 5 being reduced to zero. Therefore, the main IGBT 21 would have its gate-emitter voltage lowered, and thus it would be made in the off state. Accordingly, the output voltage VO would be “H”, but become indefinite.
On the contrary, when the discharge prevention circuit 7 is provided as above, the above-mentioned discharge circuit is not formed, and one output voltage from the bistable circuit 5, namely, the gate-emitter voltage of the main IGBT 21 can be maintained, thus the on-state being retained. In other words, the bistable circuit functions as a latch circuit that holds the output state specified by the pulse-shaped signal G1 or G2 from the switching command circuit 4.
In this embodiment, the Zener diodes 531 and 532 prevent any excessive voltage from being applied between the gate and emitter of the main IGBT 21. Therefore, switching elements of which the gates have a low blocking voltage can be used to constitute this circuit arrangement. This suggests that it is possible to use thin gate oxides, increase the current driving ability of the main IGBT, reduce the areas of semiconductor elements, lower the cost and relatively simplify the manufacturing processes.
In addition, since the switching command circuit 4 operates to generate pulse-shaped signals, the loss due to the penetrating current flowing from the high voltage power HVC is less, and it can be kept low even if the voltage of main power source 1 is raised.
Moreover, the necessary power source is only the main power source 1 for driving the load 3. There is no need to provide the high-voltage floating power source as in the patent documents of JP-A-05-344719 and JP-A-09-200017. The load drive circuit can be simply formed of a small number of elements. Thus, a small-sized, low-loss load drive circuit can be produced at low cost.
The main IGBTs 21 and 22 may be, for example, MOSFETs as far as they are voltage drive type switching elements. In addition, the gate of the main IGBT 22 may be of course driven by the same circuit as that used in the main IGBT 21.
Since the main blocking voltage and gate blocking voltage of the transistors 521 and 522 of the bistable circuit 5 may be relatively as low as the gate blocking voltage of the main IGBTs 21 and 22, small-sized elements may be used for that circuit. In addition, since the element size of the high blocking voltage p-MOS transistors 511 and 512 within the bistable circuit 5 is relatively small, the n-type MOS transistors 421 and 422 within the switching command circuit 4 that directly drive these transistors may also be small-sized elements. Moreover, the element size of the high blocking voltage p-type MOS transistors 511 and 512, which is set according to the fixed rise time of the output terminal voltage VO, can be decreased sufficiently as compared with that of the main IGBTs 21 and 22. Therefore, when the load drive circuits are integrated, they can be produced to be small and at low cost.
In this embodiment, the potential of the power source common to the switching command circuit 4 and bistable circuit 5 is raised by the charge pump power circuit 8 of which the reference potential corresponds to the positive HVC of main power source 1. Therefore, even if the load drive circuits have a large number of output channels, or several to 100 output channels, the single charge pump power circuit 8 will suffice, and thus the number of elements used is small. Therefore, it is easy to integrate this circuit arrangement. Moreover, the charge pump power circuit 8 connected to the positive pole HVC as the fixed potential point of the main power source 1 causes the potential of the power source to the bistable circuit 5 and switching command circuit 4 to be kept higher than that of the positive terminal HVC of main power source 1. Thus, an external DC power source can be used in place of the charge pump power circuit 8.
Under the provision of discharge prevention elements 91 and 92, even if the output terminal voltage VO becomes “H”, the Zener diode 91 as a discharge prevention element counteracts, thus preventing the charges on the gate of the main IGBT 21 from flowing to the HVC side. Thus, the main IGBT 21 can be kept in the on state.
In addition, when the positive HVC of main power source 1 is being raised from 0 [V], the HVA terminal and output terminal VO are at 0 [V] and thus the main IGBT 21 is in the off state. Accordingly, the voltage HVC is increasing. At this time, there is the problem that the potential of the positive HVC of main power source 1 might be divided with a ratio of the off-state impedance of the main IGBT 21 and the load-3 impedance with the result that the output terminal voltage VO is developed across the load. The discharge prevention element 92 can solve this problem. That is, even if the power terminal HVC is being raised from 0 [V], the power terminal HVA is charged up to the potential of the power terminal VC via the discharge prevention element 92. Therefore, even at HVC=0 [V], the main IGBT 21 can be turned on in advance by the power from the power terminal VC. At this time, the discharge prevention element 91 prevents current from flowing from the power terminal VC to the positive HVC of the main power source. If the potential of positive HVC is raised after the main IGBT 21 is turned on, the discharge prevention element 92 counteracts, thus preventing current from flowing from the positive HVC of the main power source to the power source 10 for the pulse circuit 41. Since the main IGBT 21 is in the on state, the output terminal voltage VO can increase to a voltage that follows the positive HVC voltage minus the on-voltage drop in the main IGBT 21 due to the current flowing in the load 3, but finally increase up to the voltage of main power source 1. Therefore, there is no problem that the output voltage VO increases when the main power source 1 is rising up as described above. At this time, the gate voltage of the main IGBT 21 can be kept higher than the HVC potential by the counteraction of discharge prevention element 91, and the discharge prevention element 91 maintains its on state.
The discharge prevention element 91 can serve both as itself and an electrostatic breakdown prevention element, and thus suppress the increase of the element area. In addition, since the discharge prevention element 92 can be used as a single common element even if a plurality of load drive circuits are integrated as a semiconductor integrated circuit, the load drive circuits can be produced with the element area prevented from being increased, and at low cost.
At this time, when the charge pump power circuit 8 is not provided, it is desirable to set the pulse width so that the pulse signal G1 is turned “L” before the potential of the power terminal HVA exceeds the HVC potential when the output voltage VO is switched from “L” to “H”. If the pulse width were long enough that the pulse signal G1 continued “H” even after the HVA potential exceeded the HVC potential, current might flow from the terminal HVA through the resistor 431 and transistor 421, lowering the gate voltage of main IGBT 21 so that the on-voltage across the main IGBT 21 would increase.
In addition, if the pulse signal G1 is previously caused to be “H” for a much longer period when the HVC potential is being raised from 0 V, the main IGBT 21 can be turned off. Therefore, it is necessary, after the main IGBT 22 is turned on, to raise the HVC potential and then to turn on the main IGBT 21. Consequently, even if the charge pump power circuit 8 and discharge prevention elements 91 and 92 are not provided, the potential of the output terminal VO is not indefinite during the HVC potential rise, and thus the above problem does not occur. In other words, the main IGBT (the second semiconductor switching element) 22 is turned on before the voltage of main power source 1 is raised, and the main IGBT 21 is allowed to turn on after the voltage of main power source 1 has risen up to a predetermined voltage.
Incidentally, as indicated by the broken lines in
On the contrary, the embodiment shown in
The other points than this feature are exactly the same as those including the operations in the embodiment shown in
This array structure enables the wiring region to be minimized, and the stray capacitance between high-voltage elements to be reduced. In addition, since the insulating films are provided to isolate the elements, it is possible to reduce the stray capacitance and lower the current value when the pulses drive the elements. Thus, it is possible to further reduce the loss, element size and cost.
Integration of the load drive circuits according to the embodiments of the invention can produce the small-sized and low-loss driver IC 60 for plasma display.
According to this example, use of small-sized and low-loss load drive circuits enables the plasma display to reduce the loss. The simplification of IC's heat radiation leads to the small size, weight saving and low cost of drive circuits.
The present invention is not limited to the above embodiments, but of course can be variously changed without departing from the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-147964 | May 2005 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6496166 | Onozawa et al. | Dec 2002 | B1 |
| 7288856 | Thiery et al. | Oct 2007 | B2 |
| Number | Date | Country |
|---|---|---|
| 05-344719 | Dec 1993 | JP |
| 06-120794 | Apr 1994 | JP |
| 09-200017 | Jul 1997 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20060267408 A1 | Nov 2006 | US |
