Claims
- 1. A raster scan image-generating system comprising:
- graphic data generating means for generating graphic commands to define images for display;
- raster scan display means for visually displaying the graphic data in a series of parallel raster lines, each line including a series of pixels;
- processing means for transforming the graphic commands into pixel data including an address and a value of each pixel;
- frame buffer means including at least one plane of memory elements corresponding dimensionally to the raster lines and pixels of the display means for storing the pixel data and outputting the pixel values to the display means one raster line at a time and one pixel at a time in each line; and
- frame buffer control means connected to receive the pixel data from the processing means for controlling the manner in which the pixel data is stored in the frame buffer;
- the processing means including:
- means for generating a vector having at least a beginning point and a direction;
- means for generating first and second pixel data for said vector including at a first address for a first pixel corresponding to said beginning point and an incremental octal position and pixel value for a second pixel adjacent the beginning point pixel; and
- means for sending said first and second pixel data to the control means in a first word and a second word,
- the first word comprising said first address and a first bit defining a selected one of the X-axis and the Y-axis as a major axis and a second bit defining a direction along the selected axis from the first address toward the second pixel, and
- the second word comprising the pixel value for the second pixel and a minor axis bit defining whether or not the second pixel is positioned at a second address laterally adjacent the major axis on the non-selected, minor axis; and
- the control means including
- means responsive to the first word for addressing the first address location in the frame buffer in accordance with the first address and setting a direction of incremental movement along the selected major axis in accordance with the first and second bits;
- means responsive to the second word for moving incrementally from the first address location along the major axis in accordance with the set direction of incremental movement and along the minor axis in accordance with the minor axis bit to a second address location; and
- means for writing the second pixel value in the second address location.
- 2. A system according to claim 1 in which:
- the first word includes a third bit defining a direction along the non-selected, minor axis and the control means responsive to the first word is responsive to the third bit to set a direction for incremental movement along the minor axis; and
- the minor axis bit is a single bit indicating whether or not to increment along the minor axis and the control means responsive to the second word causes movement in accordance with the set minor axis direction and the minor axis bit.
- 3. A system according to claim 1 in which the processing and control means are operable to send, receive and write into the frame buffer means a pixel value for the first pixel in the first address location of the frame buffer means.
- 4. A system according to claim 1 in which the means for generating a vector having at least a beginning point and a direction is further operable to generate a second vector having a second beginning point corresponding to an endpoint of a preceding, first vector;
- the processing means being operable to send to the control means a pixel value for the first pixel corresponding to the beginning point of each said vector;
- the processing and control means including means for sending and receiving a hesitate bit; and
- the control means being responsive to the hesitate bit to determine whether or not to write the first pixel value in the first address location of the frame buffer means so as to control whether a first pixel value of the second vector overwrites a last pixel value corresponding to the endpoint of the first vector.
- 5. A system according to claim 1 in which the vector generating means is operable to generate a curve.
- 6. A system according to claim 5 in which the processing means is operable to interrupt sending said second word for points along a first line or curve in a first octant, to send another first word containing a second set of said first and second bits for changing one of said major axis or direction, and to resume sending said second words to generate a second line or curve in a second octant.
- 7. A system according to claim 1 including:
- off-screen memory means for storing the graphic images;
- means for reading pixel data from the frame buffer means into the off-screen memory means; and
- means for restoring pixel data from the off-screen memory means to the frame buffer means.
- 8. A system according to claim 7 in which the processing means and the control means are cooperative with at least one of the restoring means and the reading means for transferring pixel data between the frame buffer means and off-screen memory means by use of said first word and the minor axis bit portion of the second words.
- 9. A system according to claim 7 in which the processing means and the control means are cooperative with the restoring means and the reading means for transferring pixel data between the frame buffer means and off-screen memory means by use of said first word and the minor axis bit portion of the second words.
- 10. A system according to claim 1 including:
- off-display memory means for storing the graphic images; and
- means cooperative with the processing means and the control means for reading pixel data from the frame buffer means into the off-display memory means by use of said first word and the minor axis bit portion of the second words.
- 11. Apparatus for controlling a raster scan display device for visually displaying graphic images in a series of parallel raster lines, each line including a series of pixels, comprising:
- processing means for receiving and transforming graphic commands into pixel data including an address and a value of each pixel;
- frame buffer means for storing the pixel data and outputting the pixel values to the display device one raster line at a time and one pixel at a time in each line;
- multiplexed address/data bus means for transmitting pixel data between the processing means and the frame buffer means; and
- frame buffer means for controlling storage of the pixel data in the frame buffer means;
- the processing means including:
- means responsive to a predetermined graphic command for generating a vector having at least a beginning point and a direction;
- means for generating first and second pixel data for said vector including a first address for a first pixel corresponding to said beginning point and an incremental octal position and pixel value for a second pixel adjacent the beginning point pixel; and
- means for sending said first and second pixel data to the control means in a first word and a second word,
- the first word comprising said first address and a first bit defining a selected one of the X-axis and the Y-axis as a major axis, a second bit defining a direction along the X-axis and a third bit defining a direction along the Y-axis from the first address toward the second pixel, the axis non-selected by the first bit defining a minor axis and the corresponding one of the second and third bits defining a minor axis direction; and
- the second word comprising a single minor axis bit defining whether or not the second pixel is positioned along the non-selected, minor axis in said minor axis direction at a second address corresponding to the incremental octal position of the second pixel relative to the first pixel address; and
- the control means including
- means responsive to the first word for addressing the first address location in the frame buffer in accordance with the first address and setting a direction of incremental movement along the selected major axis in accordance with the one of the first and second bits that corresponds to the selected major axis; and
- means responsive to the second word for moving incrementally from the first address location along the major axis in accordance with the set direction of incremental movement and along the minor axis in the minor axis direction as determined by the minor axis bit to a second address location.
- 12. Apparatus according to claim 11 including means for selectably writing or reading pixel values into or out of the addressed frame buffer address locations successively upon receipt of each second word, the multiplexed bus means being operative for writing by including the pixel value for each pixel in the second word and operative for reading by omitting pixel values from the second word for pixel values read from the frame buffer to be transmitted to the processing means.
- 13. Apparatus according to claim 12 including means for generating and transmitting a hesitate bit from the processing means via the bus means, the frame buffer control means being selectively responsive to the hesitate bit to write or read a pixel value at the first address location.
- 14. Apparatus according to claim 12 including:
- off-display memory means in communication with the processing means for storing portions of the graphic images; and
- means cooperative with the processing means and the control means for reading pixel data via the bus means from the frame buffer means along a vector by use of said first and second words into the off-display memory means.
- 15. Apparatus according to claim 11 in which the processing means and frame buffer means are configured as successive pipe stages in a pipeline along the bus means, each pipe stage including distributed first-in first-out (FIFO) means responsive to a clock signal for transmitting said words through a first, upstream pipe stage to a second, downstream pipe stage and responsive jointly to the clock signal and a hold signal from the downstream stage for holding said words until the hold signal is removed, and means responsive to the clock signal for pipelining the hold signals from the downstream pipe stage to the upstream pipe stage.
- 16. A method for transmitting graphic data in the form of pixel data including an address and a value of each pixel between a picture processor and a frame buffer in a raster scan display, the frame buffer including at least one plane of memory elements for storing the pixel values at their respective addresses and for outputting the pixel data to the display one raster line at a time and one pixel at a time in each line, the method comprising:
- generating a vector having at least a beginning point and a direction;
- generating in the picture processor first and second pixel data for said vector including a first address for a first pixel corresponding to said beginning point and an incremental octal position and pixel value for a second pixel adjacent the beginning point pixel;
- encoding said first and second pixel data in a first word and a second word,
- the first word comprising said first address and a first bit defining a selected one of the X-axis and the Y-axis as a major axis and a second bit defining a direction along the selected axis from the first address toward the second pixel, and
- the second word comprising a minor axis bit which determines whether or not the second pixel is positioned at a second address laterally adjacent the major axis on the non-selected, minor axis;
- sending the first word and the second word to the frame buffer;
- decoding first word, addressing the first address location in the frame buffer in accordance with the first address, and setting a direction of incremental movement along the selected major axis in accordance with the first and second bits;
- decoding the second word and moving incrementally from the first address location along the major axis in accordance with the set direction of incremental movement and along the minor axis as determined by the minor axis bit to a second address location; and
- reading or writing a second pixel value in the second address location.
- 17. A method according to claim 16 in which:
- encoding the first word includes encoding a third bit defining a direction along the non-selected, minor axis and decoding the first word includes setting a direction for incremental movement along the minor axis in accordance with the third bit; and
- encoding the second word includes encoding the minor axis bit as a single bit indicating whether or not to increment along the minor axis and decoding the second word causes movement in accordance with the set minor axis direction as determined by the minor axis bit.
- 18. A method according to claim 16 including:
- encoding in the first word a hesitate bit which indicates whether or not to read or write a pixel value for the first pixel in the first address location of the frame buffer; and
- decoding the first word includes reading or writing the pixel value for the first pixel in the first address location or not as determined by the hesitate bit and writing the pixel value for the second pixel in the second address location.
- 19. A method according to claim 16 including;
- generating a first said vector which includes an endpoint and generating a second said vector having a second beginning point corresponding to the endpoint of the first vector and a different direction;
- encoding, sending and decoding the first said vector including the beginning point and a first direction in one said first words and successive points thereof including the endpoint in a plurality of said second words;
- subsequently encoding, sending and decoding the second said vector including the beginning point and a second direction in one said first words and successive points thereof in a plurality of said second words; and
- reading or writing a pixel value at each point along each vector.
- 20. A method according to claim 19 including:
- encoding in the first word a hesitate bit which indicates whether or not to write a pixel value for the first pixel in the first address location of the frame buffer; and
- encoding the hesitate bit of the first word for the second vector to indicate not to read or write the first pixel value in the first address location of the frame buffer so that the first pixel value of the second vector is not read or written over a last pixel value corresponding to the endpoint of the first vector.
- 21. A method according to claim 16 in which generating a vector includes generating a curve having a slope within one octant.
- 22. A method according to claim 16 including:
- reading pixel value data along the vector in the frame buffer in accordance with said first and second words;
- storing the pixel value data read from the frame buffer in an off-screen memory means;
- writing new pixel value data along the vector in the frame buffer in accordance with said first and second words; and
- restoring the stored pixel value data from the off-screen memory means to the frame buffer by writing same along the vector in the frame buffer in accordance with said first and second words.
- 23. A method according to claim 16 in which the vector has an endpoint, including:
- determining a magnitude of each of the X-axis and Y-axis components of the vector from beginning to end points;
- determining which component is larger and designating that component as the major axis in the first word;
- determining a sign of each of the X-axis and Y-axis components of the vector proceeding from beginning to end points and setting the direction of each in the first word; and
- determining the location of a second pixel along the vector and setting the minor axis bit in the second word depending on the second pixel's location relative to the major axis.
- 24. A raster scan image-generating system comprising:
- graphic data generating means for generating graphic commands to define images for display;
- raster scan display means for visually displaying the graphic data in a series of parallel raster lines, each line including a series of pixels;
- processing means for translating the graphic commands into pixel data including an address and a value of each pixel;
- frame buffer means including at least one plane of memory elements corresponding dimensionally to the raster lines and pixels of the display means for storing the pixel data and outputting the pixel data to the display means one raster line at a time and one pixel at a time in each line;
- frame buffer control means connected to receive the pixel data from the processing means for controlling the manner in which the pixel data is stored in the frame buffer means;
- means in the processing means for generating a vector having at least a beginning point and a direction and transmitting same to the frame buffer control means;
- means in the frame buffer control means for generating frame buffer addresses in accordance with the vector;
- off-screen memory means for storing portions of the graphic images;
- means for reading pixel data from the frame buffer means and storing the pixel data in the off-screen memory means in accordance with the frame buffer addresses determined by the vector;
- means in the processing means for encoding the vector in a first word and a second word, the first word including an address defined by the beginning point and a major and minor axis direction components, the second word including a minor axis bit defining a minor axis step; and
- addressing means in the frame buffer control means responsive to the first word to address the beginning point and set a direction of change of address for each axis, and responsive to each second word to incrementally change the major axis address and selectively responsive to the minor axis bit to incrementally change the minor axis address.
- 25. A system according to claim 24 in which the processing means and frame buffer means are configured as successive pipe stages in a pipeline along a bus means, each pipe stage including distributed first-in first-out (FIFO) means responsive to a clock signal for transmitting said words through a first, upstream pipe stage to a second, downstream pipe stage and responsive jointly to the clock signal and a hold signal from the downstream stage for holding said words until the hold signal is removed, and means responsive to the clock signal for pipelining the hold signals from the downstream pipe stage to the upstream pipe stage.
- 26. A method for operating a raster scan display system to display vector and vector-based graphic images, the system including a picture processor communicating with a frame buffer via a bus, the method comprising:
- providing off-screen memory in communication with the picture processor;
- generating graphic commands to define graphic images, including a graphic command for a vector having a beginning point and an endpoint;
- processing the graphic commands into pixel data including a pixel address for a beginning point of the vector and means for defining subsequent pixel addresses along the vector;
- addressing a series of memory locations in the frame buffer in accordance with the pixel addresses along the vector;
- reading or writing a value of each pixel at each pixel address along the vector in the frame buffer;
- transmitting the pixel values over the bus between the frame buffer and the picture processor for storage in the off-screen memory;
- encoding the vector in a first word and a second word, the first word including an address defined by the beginning point and major and minor axis direction components of the vector, the second word including a minor axis bit defining a minor axis step;
- in response to the first word, addressing the beginning point in the frame buffer and setting a direction of change of address for each axis; and
- in response to each second word, incrementally changing the major axis address in the direction set therefor and, in selective response to the minor axis bit, incrementally changing the minor axis address in the direction set therefor.
- 27. A method for operating a raster scan display system to display vector and vector-based graphic images, the system including a picture processor communicating with a frame buffer via a bus, the method comprising:
- providing off-screen memory in communication with the picture processor;
- generating graphic commands to define graphic images, including a graphic command for a vector having a beginning point and an endpoint;
- processing the graphic commands into pixel data including a pixel address for a beginning point of the vector and means for defining subsequent pixel addresses along the vector;
- addressing a series of memory locations in the frame buffer in accordance with the pixel addresses along the vector;
- reading or writing a value of each pixel at each pixel address along the vector in the frame buffer;
- transmitting the pixel values over the bus between the frame buffer and the picture processor for storage in the off-screen memory;
- configuring the picture processor and frame buffer as a series of successive pipe stages in a pipeline along the bus;
- providing at each pipe stage a distributed first-in first-out (FIFO) means responsive to a clock signal for transmitting said pixel data through a first, upstream pipe stage to a second, downstream pipe stage;
- jointly controlling each pipe stage with the clock signal and a hold signal from the downstream stage for holding up operation of the pipe stage until the hold signal is removed;
- pipelining the hold signals from the downstream pipe stage to the upstream pipe stage so that each upstream stage hold signal is controlled by the clock signal and is a logical OR of the hold signal from the downstream stage and of a busy signal from the upstream pipe stage; and
- controlling the FIFO of each upstream pipe stage with its respective pipe stage hold signal.
- 28. Apparatus for controlling a raster scan display for visually displaying the graphic data in a series of parallel raster lines, each line including a series of pixels, comprising:
- processing means for transforming graphic commands into pixel data including an address and a value of each pixel;
- frame buffer means for storing the pixel data and outputting the pixel data to the display one raster line at a time and one pixel at a time in each line;
- bus means for transmitting pixel data between the processing means and the frame buffer means; and
- frame buffer control means connected to receive the pixel data from the processing means via the bus means for controlling the manner in which the pixel data is read or written in the frame buffer;
- the processing means and frame buffer control means being configured as successive pipe stages in a pipeline along the bus means, each pipe stage including distributed first-in first-out (FIFO) means responsive to a clock signal for transmitting said pixel data through a first, upstream pipe stage to a second, downstream pipe stage and responsive jointly to the clock signal and a hold signal from the downstream stage for holding said pixel data until the hold signal is removed, and means responsive to the clock signal for pipelining the hold signals from the downstream pipe stage to the upstream pipe stage.
- 29. A system according to claim 28 including a Z buffer in communication with the bus means, the Z-buffer being configured as a pipe stage and including one of said FIFO means.
- 30. A system according to claim 28 including:
- off-screen memory means in communication with the processing means for storing portions of the graphic images; and
- means for reading pixel data from the frame buffer means and transmitting same via the bus means to the processing means for storage into the off-display memory means;
- the processing means and the frame buffer control means each including input and output sections configured as said pipes stages with said FIFO means.
- 31. A system according to claim 30 including means for restoring pixel data from the off-screen memory means to the frame buffer means via the bus means.
- 32. A system according to claim 28 which the but is a multiplexed address/data bus means for transmitting pixel data in the form of a first word including a pixel address in a first time interval and a second word including a pixel value between the processing means and the frame buffer means.
- 33. A system according to claim 32 in which the multiplexed address/data bus means is bidirectional for selectably writing pixel values from the processing means to the frame buffer means or reading pixel values from the frame buffer means to the processing means.
- 34. A method for transmitting graphic data in the form of pixel data including an address and a value of each pixel between a picture processor and a frame buffer in a raster scan display, the method comprising:
- configuring the picture processor and frame buffer as a series of successive pipe stages in a pipeline along a bus;
- providing at each pipe stage a distributed first-in first-out (FIFO) means responsive to a clock signal for transmitting said pixel data through a first, upstream pipe stage to a second, downstream pipe stage;
- jointly controlling each pipe stage with a clock signal and a hold signal from the downstream stage for holding up operation of the pipe stage until the hold signal is removed;
- pipelining the hold signals from the downstream pipe stage to the upstream pipe stage so that each upstream pipe stage hold signal is controlled by the clock signal and is a logical OR of the hold signal from the downstream stage and of a busy signal from the upstream pipe stage; and
- controlling the FIFO of each upstream pipe stage with its respective pipe stage hold signal.
- 35. A method according to claim 34 including:
- generating a vector;
- encoding the vector in the picture processor in a first word and a second word, the first word including an address defined by the beginning point and a major and minor axis direction components, the second word including a minor axis bit defining a minor axis step; and
- addressing the frame buffer in response to the first word to address the beginning point and setting a direction of change of address for each axis; and
- addressing the frame buffer in response to each second word by incrementally changing the major axis address and in selective response to the minor axis bit by incrementally changing the minor axis address.
Parent Case Info
This is a continuation of application Ser. No. 113,927 filed Oct. 26, 1987.
US Referenced Citations (11)
Non-Patent Literature Citations (1)
Entry |
IBM Technical Disclosure Bulletin, "Graphic Bit-BLT Copy Under Mask", vol. 28 No. 6, Nov. 1985. |
Continuations (1)
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Number |
Date |
Country |
Parent |
113927 |
Oct 1987 |
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