Patent Application
20140354262
Embodiments of the inventive subject matter generally relate to the field of communications, and, more particularly, to digital phase-locked loop communications.
A phase-locked loop or phase lock loop (PLL) is a common component in communication systems. A PLL is often used to maintain synchronization of transmitted signals. A PLL typically includes a control system that generates an output signal whose phase is related to the phase of an input “reference” signal. Some PLLs include an electronic circuit consisting of a variable frequency oscillator and a phase detector. The circuit compares the phase of the input signal with the phase of the signal derived from its output oscillator and adjusts the frequency of its oscillator to keep the phases matched. The signal from the phase detector is used to control the oscillator in a feedback loop.
Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to recover a signal from a noisy communication channel, generate stable frequencies at a multiple of an input frequency (frequency synthesis), or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz.
There are several variations of PLLs. Some terms that are used are analog phase-locked loop (APLL) also referred to as a linear phase-locked loop (LPLL), digital phase-locked loop (DPLL), all digital phase-locked loop (ADPLL). An analog or linear PLL (LPLL) typically includes an analog phase detector and a voltage-controlled oscillator (VCO). A digital PLL (DPLL) is similar to an analog PLL except that a DPLL utilizes a digital phase detector. All digital PLL (ADPLL) is a design in which the phase detector, filter and oscillator are all digital components. A conventional ADPLL utilizes a numerically controlled oscillator (NCO) (sometimes also referred to as a digital controlled oscillator, DCO). Conventional PLL lock detectors determine a lock condition by comparing an output clock signal with an input reference signal.
Various embodiments for are described for determining whether a digital phase-locked loop (PLL) circuit is locked in phase with a reference signal. A PLL lock detector provides a lock status based, at least in part, on an accumulation of phase errors from the phase comparator of the PLL circuit.
In one embodiment, a PLL circuit includes a phase comparator configured to periodically determine phase errors based, at least in part, on a comparison of a reference signal and a feedback signal of the PLL circuit. A PLL lock detector is configured to accumulate a sum of the phase errors and to determine whether the PLL circuit is locked in phase with the reference signal based, at least in part, on whether the sum of the phase errors is below a threshold value.
The present embodiments may be better understood, and numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The description that follows includes exemplary systems, methods, techniques, instruction sequences and computer program products that embody techniques of the present inventive subject matter. However, it is understood that the described embodiments may be practiced without these specific details. For instance, although examples refer to an all-digital phase locked loop circuit, embodiments of the present disclosure may be relevant to other types of digital phase locked loop circuits. In other instances, well-known instruction instances, protocols, structures and techniques have not been shown in detail in order not to obfuscate the description.
A PLL lock detector is a diagnostic circuitry that monitors the PLL control loop to tell if the loop is locked (sometimes also referred to as “settled”). In traditional analog PLLs, the voltage of the control line is monitored to determine if the PLL circuit is locked. In a traditional all-digital PLL, a similar approach may be implemented to monitor the digital control word of the digital-controlled oscillator (DCO). For example, a traditional lock detector for an all-digital PLL may observe a control signal of the oscillator (e.g. “control word”) to determine a lock status.
When the PLL is locked, the control word will be “settled” so the locked detection can be achieved by measuring the fluctuation of the control word. If the fluctuation is small, it represents a stable loop and the lock detector should signify “locked.” However, the digital control word may be a lengthy value (e.g. wide bit-width) to cover a large range of the control frequency. Monitoring fluctuations in the digital control words may be impractical or inefficient. To monitor the fluctuations in the digital control words, multiple adders with wide bit-width are needed to measure the average and delta calculations. Power consumption and space on the integrated circuit are considerations that motivate the use of fewer adders.
In accordance with some embodiments of the present disclosure, a PLL lock detector may be configured to observe the phase error signal from a phase comparator of the PLL circuit. In a locked state, the phase error is expected to be close to zero. Only small amounts of fluctuation may be present in the phase error when the PLL is nearly locked. Since the phase error is small when locked, a smaller bit width value may be used to determine whether the PLL is locked. Using the smaller bit width value may result in smaller adders or less complex circuitry. Therefore, in one embodiment, the lock detector may utilize a much smaller physical area in the circuit board and/or utilize less power than the traditional approach.
In another embodiment, the phase error signal may be modified to further reduce the bit width of the phase error signal while still providing sufficient data to determine whether the PLL circuit is locked in phase with a reference signal. For example, a clipping or truncating operation may reduce the bit width of the phase error signal. The abridged phase error signal may be used with an accumulator to maintain a sum of the phase errors. In one embodiment, the accumulator may be configured to act as a low-pass filter in conjunction with limiting the maximum value of the phase error sum. The phase error sum may be compared with a threshold value to determine whether the PLL is locked. For example, in one embodiment, if a magnitude of the phase error sum is not greater than a threshold value, the lock detector indicates that the PLL circuit is phase-locked. The lock detector output signal may comprise a single bit value to indicate whether the PLL circuit is locked.
The PLL circuit 101 includes a phase comparator 110 (sometimes also referred to as a phase detector). The phase comparator 110 receives the reference signal 105 and a feedback signal 155 and determines a phase error signal 115 based on a comparison of the reference signal 105 and the feedback signal 155. The phase error signal 115 carries information about how closely the feedback signal 155 aligns to the reference signal 105. The phase error signal 115 is sent to a loop filter 120 that generates a control word 125 based, at least in part, on the phase error signal 115. The control word 125 includes a configuration used by a digital-to-analog converter (DAC) 130 to control a controlled oscillator (OSC) 140. In some literature, the DAC 130 and OSC 140 may be referred together as a digitally controlled oscillator (DCO) 142. The DCO 142 generates the output signal 165 using oscillator circuitry.
In a phase locked loop circuit, a feedback mechanism is used to monitor or adjust the output of the oscillator circuitry to maintain a phase lock with the reference signal. In
A PLL lock detector 170 provides an indication to other components of an electronic device regarding whether the PLL circuit 101 is currently locked in phase with the reference signal 105. In traditional implementations, a PLL lock detector may monitor the output signal 145 or the feedback signal 155 to determine a comparison to the reference signal 105. However, additional phase comparator or signal shaping components were typically needed to compare the output or feedback signals to the reference signal. Complex circuitry to monitor zero cross boundaries and synchronization added complexity to the traditional PLL lock detector. In other traditional implementations, as stated previously, the control word 125 was used to determine lock status. However, in fine precision PLL circuits, the control word 125 may be a large signal (i.e., bit width) which typically required complex circuitry to manage calculations based, at least in part, on the control word 125.
In accordance with some embodiments of this disclosure, the PLL lock detector monitors the phase error signal 165 that is generated by the phase comparator 110. The phase error signal is already generated during normal operation of the PLL circuit 101, so the present disclosure does not require additional phase comparators to implement PLL lock detection. The PLL lock detector 170 manipulates the phase error signal 165 to determine whether the phase error signal indicates that the PLL circuit 101 is locked in phase with the reference signal 105. The PLL lock detector 170 generates a lock status signal 175 to indicate whether the PLL circuit 101 is phase locked. For example, the lock status signal 175 may be a binary signal that indicates a first value for locked or a second value for unlocked. Other components (not shown) of the electronic device may check the lock status signal 175 to determine whether the PLL circuit 101 is locked in phase with the reference signal 105.
This disclosure provides several examples (such as those described in
As described previously, the phase error signal 205 is received from a phase comparator that compares the feedback signal with the reference signal. Typically, the phase error signal 205 is a small value with positive or negative variations based, at least in part, on how well the feedback signal is in phase with the reference signal. Because the phase error signal 205 may include positive or negative values, the sum of the phase error signals 225 may be close to zero when the PLL circuit is locked in phase with the reference signal. As the phase error signal consistently includes more positive values, the control mechanisms of the PLL circuit should correct the oscillator, and eventually the phase error signal may include zero values or negative values. Therefore, in a locked (settled) PLL circuit the sum of the phase errors over a series of phase error signals should be near zero. The accumulator 220 may add a series of phase error signals to determine the sum of phase errors 225 over the series of phase error signals.
The magnitude of the phase error sum may be an indicator of how far out of phase the PLL circuit is in relation to the reference signal. Therefore, the PLL lock detector 200 includes a comparator 240 configured to compare the sum of phase errors 225 with a threshold value 237 to determine whether the PLL circuit is locked in phase. The threshold value 237 provides a hold down (e.g. hysteresis) type feature. For example, the threshold value 237 may be a numeric value (e.g. 10) that represents an acceptable amount of phase error for the PLL circuit to still be considered locked in phase. In the example, if the sum of the phase errors 225 is less than 10, then the comparator would generate a first lock status signal 245 indicating that the PLL circuit is locked in phase with the reference signal. In the example, if the sum of the phase errors 225 is greater than or equal to 10, then the comparator would generate a second lock status signal 245 indicating that the PLL circuit is not locked in phase with the reference signal. It should be understood that in some implementations the magnitude of the sum of phase errors 225 is utilized since large negative values and large positive values both indicate an out-of-phase condition. If only the magnitude of the sum of phase errors 225 is used, the example threshold value (10) provides a tolerance range for −10 to +10 of the phase error sum. In other examples, the threshold value may represent a range that includes both positive and negative values. If the sum of phase errors is within the range, the PLL circuit may be considered locked in phase, and if the sum of phase errors it outside the range, the PLL circuit may be considered out-of-phase.
By adjusting the threshold value 237, the PLL lock detector 200 may be configured for different phase error tolerance. For example, the threshold value 237 may be a configurable setting of the PLL lock detector 200. In one implementation, the threshold value 237 may be selected based on tolerance margin (such as 5% change in phase error sum) which is to be considered phase locked by the PLL lock detector 200.
The use of the phase error sum may allow the PLL lock detector 200 to utilize a smaller footprint in the physical circuit area because it needs fewer adder components. For example, the lock detector circuitry may be made up of three adder components—one adder in the accumulator 220 and two adders in the comparator 240. The fewer number of adder components and decreased complexity of the adders may allow the PLL lock detector of the present disclosure to be much less complex, be more power efficient and/or have a smaller physical area as compared to the traditional approach. For example, in one implementation, the PLL lock detector including features described in this disclosure may have a reduced area and lower power consumption of more than 70% over the traditional approach.
The phase error signal 305 is received from the phase comparator (not shown) of the PLL circuit. In
Referring to
Continuing with
The first transformation 310 and second transformation 330 are added features in the enhanced PLL lock detector 300 but may reduce the power and space requirements of the PLL lock detector 300 because of the use of fewer bit-width adders in the accumulator 320 and comparator 340.
In
In one implementation, the accumulator 420 can be implemented using a single 18-bit adder. Because the size of the accumulator 420 is capable of accumulating an 18-bit word value and the truncated phase error signal 415 is represented as a 10-bit word value, the accumulator 420 may not experience an overflow condition (with are further describe in relation to
It should be understood that other configurations of limiters, accumulators, truncating components, or comparators may be used. Furthermore, various selections of bit lengths or bits to truncate or compare may also be used in accordance with this disclosure.
In
At 550, the overflow indication may be used to determine that the PLL circuit is not phase locked. For example, if the sum of phase errors is so large that the accumulator 520 overflows, the overflow indicator may be used to determine that the PLL circuit is out of phase with the reference signal regardless of whether the sum of phase errors has been compared to the threshold value yet. Therefore, for example, when the accumulator 520 is configured to count a larger number of phase error signals, the overflow indication can also be used to reset the accumulator 520.
In a typical implementation, a positive value (e.g., binary “1”) may indicate an overflow condition. The overflow indication signal 555 may be used with an “OR” logic component 560. If either the lock comparison signal 545 or the overflow indication signal 555 indicate that the PLL circuit is not locked, then the OR logic component 560 will output a lock status signal 565 to indicate that the PLL circuit is not locked with the reference signal. Other variations in which a phase error signal is used in a lock detector circuit may be readily conceived based on the foregoing disclosure and example figures.
At 710, an operation may include receiving a plurality of phase error signals from a phase comparator a PLL circuit. The phase comparator may be an existing component already used in the PLL circuit for controlling the PLL circuit.
At 720, an operation may include truncating each of the plurality of phase error signals. At 730, an operation may include accumulating a phase error sum based, at least in part, on the plurality of truncated phase error signals. The accumulating may be performed by an accumulator component or components.
At 740, if the accumulator may be configured with an overflow capability, an operation may include detecting whether an overflow condition has occurred. For example, the overflow condition may be indicative that the phase error sum is beyond a capacity of the accumulator. If an overflow condition is detected, the flow continues to block 780. If an overflow condition is not detected, or if the overflow capability is not implemented, the flow continues to block 750.
At 750, an operation may include truncating the phase error sum. At 760, an operation may include comparing the truncated phase error sum to a configurable threshold value. The comparing may be performed by a comparator component or components. At 770, an operation may include determining a lock status of the PLL circuit based, at least in part, on said comparing.
At 780, an operation may include determining that the PLL circuit is not phase locked based, at least in part, on the overflow condition.
It should be understood that
As will be appreciated by one skilled in the art, aspects of the present inventive subject matter may be embodied as a system, method, or computer program product. Accordingly, aspects of the present inventive subject matter may take the form of an entirely hardware embodiment, a software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present inventive subject matter may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
Any combination of one or more non-transitory computer readable medium(s) may be utilized. Non-transitory computer-readable media comprise all computer-readable media, with the sole exception being a transitory, propagating signal. The non-transitory computer readable medium may be a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
Computer program code embodied on a computer readable medium for carrying out operations for aspects of the present inventive subject matter may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
Aspects of the present inventive subject matter are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the inventive subject matter. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
The electronic device 800 also includes the digital phase lock loop 812 and the PLL lock detector 816. As described above in
While the embodiments are described with reference to various implementations and exploitations, it will be understood that these embodiments are illustrative and that the scope of the inventive subject matter is not limited to them. In general, enhanced tone maps as described herein may be implemented with facilities consistent with any hardware system or hardware systems. Many variations, modifications, additions, and improvements are possible.
