Patent Application
20190138242
In order for a system to respond to events or inputs in “real-time” it must have execution times on the order of milliseconds, if not faster. Thus, portions of a real-time system must have access to data immediately and cannot spend processing cycles “idling” or waiting for data to become available. Often, a producer (or writer) is producing (writing) data and a consumer (or reader) is consuming (reading), i.e., operating on, this data in these real-time system. The consumer may not need all the data produced—it just needs to get the “latest” or most current data. In order to meet performance goals, however, neither the producer nor the consumer should be “blocked” or kept waiting for the other (or any other task) to complete before gaining access.
Most often, the gaining of access to data that has been written involves accessing memory in a computing environment. Known solutions include using a classic circular memory buffer. There are disadvantages to this approach as it requires the consumer to read and discard multiple items to get to the latest, i.e., the most relevant, data. This approach incurs a not insignificant performance hit. Further, the buffer must be sufficiently deep to allow the writer to always have room to write and this assumes the reader and writer run at a same fixed rate and not where one is significantly faster (or slower) than the other.
Another approach uses a semaphore or other mutual exclusion (mutex) construct. This method introduces latency necessary to obtain lock and does not allow for simultaneous access—which can also incur a performance hit.
What is needed, therefore, is a system that provides for a consumer to have access to data and a writer to write the data without incurring waiting penalties on real-time performance.
Embodiments of the present disclosure are directed to a system and method for sharing data between processes such that reading and writing operations occur asynchronously and without blocking. Advantageously, data can be read from one portion of buffer memory while being written to a different portion of buffer memory.
In one aspect of the present disclosure, a method of accessing a memory device is implemented in a computer. The computer comprises a processor and a tangible computer-readable medium storing a plurality of instructions executable by the processor to implement the method. The method of memory device accessing comprises: defining a plurality of memory buffers in the memory device, each memory buffer identified by MemBuff(X, Y) where each of X and Y is only either a first value or a second value, where the first value is not the same as the second value; maintaining a current pingPong variable PPC configured to flip between the first value and the second value; and maintaining a current Index IC=(XC, YC) where each of XC and YC is configured to flip between the first value and the second value. Data is written to the memory device by: retrieving the current pingPong variable PPC and current Index variable IC=(XC, YC); writing data to a memory buffer MemBuff(XC, PPC); and when writing to the memory buffer MemBuff(XC, PPC) is complete: flipping the XC value in the Index IC to the other of the first value or the second value and setting YC=PPC.
Further, reading from the memory comprises: retrieving the pingPong variable PPC and Index IC=(XC, YC); setting a temp variable Wtemp to a flipped value of XC; reading data located at a memory buffer MemBuff(Wtemp, PPC); and when reading from the memory buffer MemBuff(Wtemp, PPC) is complete, flipping the pingPong variable PPC to the other of the first value or the second value.
In another aspect of the present disclosure, a tangible computer-readable medium includes instructions for execution by a computer system to implement the methods above.
Various aspects of at least one embodiment of the present disclosure are discussed below with reference to the accompanying figures. It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn accurately or to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity or several physical components may be included in one functional block or element. Further, where considered appropriate, reference numerals may be repeated among the drawings to indicate corresponding or analogous elements. For purposes of clarity, not every component may be labeled in every drawing. The figures are provided for the purposes of illustration and explanation and are not intended as a definition of the limits of the disclosure. In the figures:
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be understood by those of ordinary skill in the art that these embodiments of the present disclosure may be practiced without some of these specific details. In other instances, well-known methods, procedures, components and structures may not have been described in detail so as not to obscure the embodiments of the present disclosure.
Prior to explaining at least one embodiment of the present disclosure in detail, it is to be understood that the disclosure is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the drawings. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description only and should not be regarded as limiting.
It is appreciated that certain features, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination.
Referring now to
In operation, the producer H1 is producing data that the consumer H2 is using, however, the consumer H2 may not have a need for all the data produced. The consumer H2 may only need the “latest” data, with respect to when the consumer H2 proceeds to retrieve data.
As will be described in more detail below, conceptually, the memory 102 is arranged as a two dimensional ping/pong buffer where the writing operation alternately swaps buffers in one dimension and the reading operation swaps buffers in the other dimension.
Accordingly, the producer H1 writes into either read-ping or read-pong buffer set, but each write alternates between the write Ping-Pong buffers. When new data is produced by H1, the consumer H2 switches the read ping-pong buffer before reading but reads from the one of the write ping-pong buffers that is not currently being written. The consumer H2 reads the last read buffer when no new data is produced by H1.
The buffer switching is coordinated by using commonly accessed variables, pingPong and index, described below in more detail, and advantageously implement a system that is lock-free, wait-free bounded as there is no need for a mutual exclusion (mutex) function. Accordingly, reads and writes are fast and deterministic as there is no complex synchronization, interrupt locking or searching/scanning. The size of the buffer is fixed and small, i.e., only four times the size of one data element, where the data element size is whatever amount of memory is needed.
Referring now to
The consumer H2 toggles, i.e., alternates, between the “read” ping-pong (rA and rB) buffers, i.e., the “rows”, if the writer has written since the last read. If this occurs, the consumer H2 reads from the write ping-pong (wA or wB) column that is not currently being written, i.e., is now reading from the most recently completely written data.
Advantageously, by operating in this manner, the buffer being read by the consumer H2 will never be simultaneously written to by the producer H1.
Two shared variables are used for synchronization:
These shared variables represent the “current” values as will be better understood below. Of course, the naming convention of these variables is arbitrary and merely used for explanatory purposes.
An example of operation, referring to
An initial state of the variables 302 is arbitrarily set such that pingPong=rA and index=(wA, rB). At some time T0, the producer H1 writes to the buffer (wA, rA) by taking the value rA from the pingPong variable and the value wA from the index variable. When writing is complete, the producer H1 then “ping-pongs” or “flips” the write-column buffer value and now the index=(wB, rA), that is, the write column changes from wA to wB. The state of the variables 304 is pingPong=rA and index=(wB, rA).
Next, at time T1, the producer H1 writes again, retrieving the current state of the variables 304 where pingPong=rA and index=(wB, rA) and writing to buffer (wB, rA) by taking the value rA from the pingPong variable and the value wB from the index variable. Once the write operation is completed, the producer H1 then “ping-pongs” the write-column buffer value and now index=(wA, rA). The variable state 306 is set such that pingPong=rA and index=(wA, rA). The states of the variables 302, 304, 306 have only changed with respect to the write value as only write operations, to this point in time, have occurred and the producer H1 only modifies the value of the write column value of the index variable.
At time T2, the consumer H2 initiates a read operation and retrieves the current state of the variables 306 where pingPong=rA and index=(wA, rA). The consumer H2 compares read-row buffers from pingPong and index and sets, i.e., flips, pingPong=rB in the variable state 308. The consumer H2 is now reading in read-row rA and the write-column wB, which is the “opposite” of the value retrieved from the index variable. In other words, because the index variable in state 306 indicates the write column that will be written to next, the write column that should be read from is the opposite of that value, i.e., the “flipped” or “other” value as there are only two values that it could be. Note that H2 does not change the index variable and, as understood by one of ordinary skill in the art, could use a temporary value for the column to read from. The consumer H2 thus commences reading the buffer(wB, rA), as above at time T1, as it is the most recently completely written buffer and, therefore, contains the most recent data.
At time T3, the producer H1 initiates a write operation using the variable state 308 where pingPong=rB and index=(wA, rA). The producer H1 completes writing buffer(wA, rB) and ping-pongs the write-column value and sets the index=(wB, rB). To write in the (wA, rB) buffer and set index=(wB, rB) as the current setting of pingPong=rB indicates that the consumer H2 is next reading from the rA row of buffers. It should be noted that the system does not need to consider whether the consumer H2 is still reading as the protocol assures that writing cannot occur where reading may be continuing.
When the producer H1 completes the write operation, the state of the variables 310 is pingPong=rB and index=(wB, rB).
As an example of reading and writing occurring at the same time without interfering or corrupting data, at time T4, the consumer H2 initiates a reading operation based on the variable state 310 where pingPong=rB and index=(wB, rB). Accordingly, at the beginning of the read operation, the consumer H2 updates to the variable state 312 such that pingPong=rA and index=(wB, rB) (unchanged) indicating that reading is taking place in the rB row of buffers as determined by the read-row value retrieved from the index variable. In this case the reading is taking place in buffer (wA, rB).
In this example, during the read operation of consumer H2 begun at time T4, and prior to its completion at time T6, the producer H1 starts a write operation at time T5 based on the variable state 312 where pingPong=rA and index=(wB, rB). Accordingly, per the foregoing, the producer H1 will not write in buffer read-row rB and writes, instead, in the buffer(wA, rA). Once the write is completed, the variable state 314 is updated to reflect pingPong=rA and index=(wB, rA) (unchanged).
In this example, the read operation that started at time T4 does not complete until time T6, after the producer H1 has written “new” data. Advantageously, the producer H1 was not stopped from writing the data while the consumer H2 was reading and vice-versa. Depending on the data requirements, the consumer H2 will be able to retrieve the data when next necessary per its operation.
The use of a two-dimensional array of ping-pong buffers (one dimension for reading, one dimension for writing) allows both functions to occur simultaneously as access to the data structure does not require locks and results in increased performance as neither the producer nor the consumer is blocked waiting for the other (or any other task).
Referring now to
Further, another approach to explaining the reading operation of embodiments of the present disclosure references
If it is determined at step 604 that the writer has written new data, control passes to step 608 where the reader retrieves and stores the current writer's “WI write-column” and “WI read-row” values and next, step 610, retrieves the reader's current “PP read-row” value, [PPtemp=PPc].
At step 612, it is determined if both read rows are the same, [Ystart≠PPtemp]. If not, control passes to step 614 indicating that the writer has not written since last flipped buffers and if memory device has not changed since last read, mark as not new data, step 616, [Updated=(Iprior≠Istart)]. The reader can then safely read the last buffer written and doesn't need to flip the buffers, step 618, [(Iprior=Istart)]. At step 620, the reader reads the memory device identified by the “WI read-row” value and the other value of “WI write-column,” [Write to (
Returning to step 612, if both read rows are the same, [Updated=true], control passes to step 622 indicating the writer has written since the system last flipped buffers and it is marked as there being new data. The reader's “PP read-row” value is flipped, step 624, [PP3c=
At step 628 it is determined if both read row values are the same, [Ystart==
Returning to step 628, if the read row values are not the same, control passes to step 634 indicating that the writer is still writing the current ping/pong value, [Iprior=Inew]. The system can safely read the buffer it has just written since before it writes to another buffer it will check the ping-pong flag and switch, which is executed at step 636 by reading the memory device identified by the “WI read-row” value and the other value of the newly read “WI write-column,” [Write to (wXnew, rYstart)].
Either of the producer H1 and the consumer H2, referring to
While the pair of the producer H1 and consumer H2 has been described above as writing and reading, respectively, from the memory, it is within the scope of this disclosure that a program, thread, etc., could be both a producer and a consumer. While the embodiment described herein operates in producer/consumer pairs another embodiment could include a series of interleaved pairs where a consumer in one pair is a producer in a next and vice-versa. Of course, each pair would have its own respective set(s) of memory buffers as arranged and described herein.
Various embodiments of the above-described systems and methods may be implemented in digital electronic circuitry, in computer hardware, firmware, and/or software. The implementation can be as a computer program product, i.e., a computer program embodied in a tangible information carrier. The implementation can, for example, be in a machine-readable storage device to control the operation of data processing apparatus. The implementation can, for example, be a programmable processor, a computer and/or multiple computers.
A computer program can be written in any form of programming language, including compiled and/or interpreted languages, and the computer program can be deployed in any form, including as a stand-alone program or as a subroutine, element, and/or other unit suitable for use in a computing environment. A computer program can be deployed to be executed on one computer or on multiple computers at one site.
While the above-described embodiments generally depict a computer implemented system employing at least one processor executing program steps out of at least one memory to obtain the functions herein described, it should be recognized that the presently described methods may be implemented via the use of software, firmware or alternatively, implemented as a dedicated hardware solution such as in a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) or via any other custom hardware implementation.
It is to be understood that the present disclosure has been described using non-limiting detailed descriptions of embodiments thereof that are provided by way of example only and are not intended to limit the scope of the disclosure. Features and/or steps described with respect to one embodiment may be used with other embodiments and not all embodiments of the disclosure have all of the features and/or steps shown in a particular figure or described with respect to one of the embodiments. Variations of embodiments described will occur to persons of skill in the art.
It should be noted that some of the above described embodiments include structure, acts or details of structures and acts that may not be essential to the disclosure and which are described as examples. Structure and/or acts described herein are replaceable by equivalents that perform the same function, even if the structure or acts are different, as known in the art, e.g., the use of multiple dedicated devices to carry out at least some of the functions described as being carried out by the processor of the present disclosure. Therefore, the scope of the disclosure is limited only by the elements and limitations as used in the claims.
Whereas many alterations and modifications of the disclosure will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that the particular embodiments shown and described by way of illustration are in no way intended to be considered limiting. Further, the subject matter has been described with reference to particular embodiments, but variations within the spirit and scope of the disclosure will occur to those skilled in the art. It is noted that the foregoing examples have been provided merely for the purpose of explanation and are in no way to be construed as limiting of the present disclosure.
Although the present disclosure has been described herein with reference to particular means, materials and embodiments, the present disclosure is not intended to be limited to the particulars disclosed herein; rather, the present disclosure extends to all functionally equivalent structures, methods and uses, such as are within the scope of the appended claims.
