Patent Application
20150061547
The present invention relates to a Hall-sensor based controller for locking and synchronizing independently driven motors.
In practice Hall-sensor driven motors are locked/synchronized using conventional control techniques. But independently driven motors are never truly locked/synchronized unless they are driven by the same magnetic field or physically connected to each other through shafts and/or gears. There are various techniques to address this problem electronically (such as running motors in a master-slave topology), but none of the proposed solutions truly lock/synchronize motors at an average speed with no one motor dictating speed of the locked/synchronized motors as a whole.
In this invention, we are using Hall-sensor signals of the motors to run them with a single average signal thereby locking their magnetic fields and running them at an average speed. The developed controller is fundamentally different from conventional methods; such as speed or position PI controllers, etc., in that both speed and position of the motors become locked/synchronized internally through corresponding magnetic fields of the participating machines. The proposed locking/synchronizing technique is novel, as the Hall signals have not been considered in the past for locking/synchronizing multiple motors.
Since Hall sensors are not positioned accurately in practice, the mentioned technique is further enhanced by processing/filtering the Hall-sensor signals. So to address this problem, we have also invented a filtering technique to correct poorly aligned sensors before using the signals for control/synchronization purposes. The filtering technique can also be used in other industrial applications for improving single and multiple Hall-sensor controlled motors.
In accordance with the present invention the developed Sync-Lock Controller (SLC) is based on filtering and averaging the Hall sensor signals and applying the same switching intervals to the participating motors. A control-level averaging approach is developed to lock/synchronize the operation of the driving motors and equalize their speed and position. In this approach a multi-stage digital filtering block is also added to remove the errors in the original Hall-sensor signals. Each stage of the filter is designed to cancel the undesirable harmonics due to one of the error sources, the unevenly magnetized reaction tablet and the misaligned Hall sensors. Furthermore an analog and a digital implementation of the proposed controller are developed and described in detail.
The digital implementation of the controller is realized using a microcontroller. The controller in the form of a standalone dongle-circuit is placed between the original Hall-sensors and the motor drive to process the signals and filter out all undesirable errors in the signals. A compact prototype of the proposed dongle is fabricated and texted on a number of typical industrial Direct Current (DC) motors and drivers. Due to its simplicity and effective implementation, the developed algorithm can be readily applied to a variety of systems that use DC motors and drivers. The performance of the locking algorithm has been demonstrated using DC motors (with Hall-sensor positioning errors) and is shown to be efficient and robust in steady state and transients studies. The performance of the SLC was evaluated under different conditions. It was shown that the SLC improves the performance of the system under certain conditions compared to the conventional PI speed control loops.
These and other features will become more apparent from the following description in which reference is made to the appended drawings, the drawings are for the purpose of illustration only and are not intended to be in any way limiting, wherein:
A Hall-sensor based controller for locking and synchronizing independently driven DC motors, will now be described with reference to
This following prior art publications are incorporated herein by reference in their entirety. Furthermore, where a definition or use of a term in a reference, which is incorporated by reference herein is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply
A Hall-sensor based controller for locking and synchronizing independently driven DC motors is provided in this invention. The developed controller electronically locks both position and speed of the active motors as if they were operating on a common “virtual” shaft.
The Sync-Lock controller (SLC), locks/synchronizes the DC motors via the corresponding Hall sensor signals. The developed technique drives both the motors with a set of “averaged” signals thereby locking speed and angle of both motors. This locking strategy is different from a soft lock approach based on a PI controller as the two motors are locked internally by coupling the respective magnetic fields by using Hall sensor signals. Therefore both the speed and position of the motors are synchronized/locked.
The SLC is implemented digitally using a programmable integrated circuit microcontroller. First, the Hall signals undergo a layer of filtering to mitigate the errors due to hall sensor misalignment. Then, the locking algorithm is implemented by averaging the filtered Hall sensor signals. Without loss of generality, two DC motors are assumed here, whereas the SLC concept (locking/synchronizing algorithm) is readily extended for any number of motors. The controller is realized in the form of a standalone dongle-circuit that can be easily placed between the original Hall-sensors and the DC motor driver. Operation of typical industrial DC motors with the developed controller is shown to outperform conventional controllers and lock both speed and angle of the motors.
The proposed controller block diagram is shown in
Given the system configuration of
To better understand how to lock/synchronize Hall-sensor signals, it is instructive to consider the diagram depicted in
The angular intervals between two successive switching events are denoted by θ(n). Durations of intervals θ(n) are denoted here by τ(n). Here, the angle φ denotes a possible delay or advance between rotors of the two motors [3]. These signals are used by inverter to provide the stator with desired voltages. Switching logic of the transistors in inverter is summarized in Table 2. Transistor numbers in this Table correspond to what is shown in
The SLC is based on constructing one set of Hall signals by appropriately modifying (averaging) signals from the actual sensors HM1{1,2,3} and HM2{1,2,3}, respectively. The controller method works by first finding the rising edge correction interval τrcorr(n) by means of averaging switching times t(n) as follows:
τrcorr(n)=½(trlog(n)−trlead(n)). (1)
Once the correction value τrcorr(n) is established, actual timing for commutating the inverter transistors for next cycle can be found as follows:
t
r
out(n+1)=trlead(n+1)+τrcorr(n), (2)
where trlead(n) the leading motors switching time, is defined as reference switching time of the system. Based on (1) and (2), period of the average signal can be calculated as
τ(n+1)=½((tflead(n)−trlead(n))+(tflag(n)−trlag(n))). 3)
In general, the SLC can be implemented using either an analog method (which is based on combination of logic gates, integrators, and a flip flop) or a digital method (which is based on a programmable integrated circuit microcontroller and digital signal processing). These approaches are briefly described below:
Analog implementation of the SLC is based on logic gates for processing signals, integrals for time measurements, sample and hold block for memory, and a flip flop as shown in
The analog implementation of SLC averages combined signals and creates a new set of averaged signals that is used to control the inverters. Average signal essentially delays leading motor and advances lagging motor, and therefore locking the two motors. It should be mentioned that this implementation operates regardless of relative positions of the two motors and there is no need to distinguish (differentiate) leading and lagging motor.
Here we present an implementation of the SLC that can easily be used with existing drive systems. The averaging algorithm is implemented using an interrupt-based approach that is suitable for digital signal processors (DSPs) or programmable microcontroller integrated circuits (PICs). The interrupt service routines (ISR) are triggered at switching points of the Hall signals. Here, each rising and falling edge ISR is considered to have a dedicated timer which is used to save last two time periods between the edges as shown in
In a typical design configuration of DC machines, Hall sensors are mounted on a printed circuit board (PCB) attached to rear end of the motor. For a two pole machine, Hall sensors must ideally be placed exactly 120 degrees apart to produce control signals necessary for the standard 120-degree switching logic to control the six-step voltage-source inverter [27], [25], and [9]. If this is true, then Hall sensor signals will have consecutive transitions spaced out by exactly 60 electrical degrees. Although this is a common assumption in most literature sources, this condition is difficult to achieve in practice particularly in many mass-produced motors due to manufacturing tolerances. Therefore, to utilize Hall sensor signals for control purpose, these signals have to be filtered first to mitigate the errors [24], [19]-[21].
In this invention, the digital implementation of the SLC takes into account Hall sensor misalignments. The implementation is based on typical three-phase DC motors [17] as shown in
Implementation of SLC with Correction for Hall Sensor Misalignment
The poorly aligned Hall sensors are quite common in mass-produced DC motors as has been described in literature [19]-[21], [24]. Since such motors are very likely to be found in industrial applications, this phenomenon has to be considered for the purpose of this invention.
The developed Sync-Lock Control strategy synchronizes DC motors via corresponding Hall sensor signals as depicted in
The mentioned filtering algorithm can be readily implemented on a microcontroller using the so-called software interrupt service routines (ISR). Using this method, switching of Hall sensors triggers the input ISR, at which time all necessary calculations (instructions) are done inside the microcontroller. With dedicated timers for the rising and falling edges, continuous operation of drive is enabled by resetting internal time counter of the microcontroller back to zero at either rising or falling edges of input signals. Hence, time intervals τ(n) are readily available simply as the timer counts between rising and falling edges of Hall-sensor signals. To switch transistors when the filter is enabled, software output ISR has to be invoked at a particular time to provide the inverter with modified Hall signals. This time of the next switching may be expressed as
t
next
sw
=
where
In order to minimize computational resources, a direct implementation of (4-7) cannot be considered as it requires continuous calculation of both the reference time
t
out(n+1)=tin(n)+τcorr(n) (4-8)
where τcorr(n) is the appropriate correction term. Equation (4-8) is very straightforward and computationally efficient as it requires a simple scheduling of the output ISR by offset correction time τcorr(n) without the need for reference time as in (4-7). In this implementation, the output ISR is scheduled by simply comparing value of the timer and correction term.
Calculation of correction time τcorr(n) is best understood by considering
τcorr(n)=tout(n+1)−tin(n)=
Computation of (4-9) requires knowledge of the reference time. This time may be obtained by averaging switching times of the three phases as depicted in
t
Here, t(n) is time of the last switching of input Hall signal, and t′(n) and t″(n) are the times extrapolated from the two preceding input Hall signal transition times, as follows:
t′(n)=tin(n−1)+
t″(n)=tin(n−2)+2
As can be seen in
Combining the results, reference time is calculated in terms of input interrupts as:
t
Since tin(n−1) and tin(n−2) refer to the previous input interrupt times, they can be expressed as:
t
in(n−1)=tin(n)−τ(n−1) (4-13)
t
in(n−2)=tin(n)−τ(n−2)−τ(n−1) (4-14)
Combining (4-12)-(4-14) and (4-9), the correction term is represented as:
τcorr(n)=⅓(−2τ(n−1)−τ(n−2))+2
Correction term τcorr(n) can now be used for whole range of different filters presented in [24], [19], and [20] by substituting the appropriate expression for
τa3corr(n)=⅓(τ(n−2)+2τ(n−3)) (4-16)
τa6corr(n)=⅓(−τ(n−1)+τ(n−3)+τ(n−4)+τ(n−5)+τ(n−6)) (4-17)
τlcorr(n)=⅓(2τ(n−1)+τ(n−2)+2τ(n−3)−2τ(n−4)) (4-18)
τqcorr(n)=⅓(4τ(n−1)−τ(n−2)+2τ(n−3)−4τ(n−4)+2τ(n−5)) (4-19)
Without loss of generality, here, we consider third order filter (4-16) to prove the SLC concept, but the proposed algorithm can readily be extended for higher order filters. Thus, the third order filter will be implemented using (4-3) and (4-16) which is computationally efficient and simple compared to [24].
The SLC is based on constructing one set of Hall signals by appropriately modifying (filtering/averaging) the signals from actual sensors HM1{1,2,3} and HM2{1,2,3}. Averaging is done by first finding the rising edge offset term which is
τdr(n)=trb(n)−tra(n). (4-20)
Once the offset value τdr(n) is established, actual timing for commutating the inverter transistors for next cycle can be found as follows:
t
r
out(n+1)=tra(n+1)+(½)τdr(n), (4-21)
where tra(n), the leading motors switching time, is defined as reference switching time of the system. A similar approach is used for falling edges of the signals resulting in period of the average signal:
τ(n+1)=½((tfa(n)−tra(n))+(tfb(n)−trb(n))). (4-22)
Averaging algorithm is also based on the software ISR triggered by rising and falling edges of the input signals. As before, for each rising and falling edge, the ISR has a dedicated timer which is used to save the last two time periods between the edges as shown in
It is essential to integrate the mentioned filtering and locking techniques efficiently and minimize computational resources as much as possible. The filtering and locking techniques are integrated using only two software ISRs with dedicated timers. One ISR and timer is devoted to rising edges of the input signals, while another ISR and timer pair is used for falling edges of the input signals. Finally, the third timer is utilized for scheduling output interrupt for both the rising and falling edges.
The algorithm can be explained by considering rising and falling edges of Hall signals separately.
τdr=τ0r+(τ(n)−τcorr(n))a−(τ(n)−τcorr(n))b. (4-23)
Here, subscript “a” denotes period difference of the leading motor; and subscript “b” is used to denote period difference of the lagging motor. It should be noted that either one of motors 1 and 2 could be leading or lagging.
Similar to the rising edge interrupt, the output falling edge interrupt is scheduled at input rising edge when τ0r>τ1r to be triggered at τcorr(n+3)+τdf/2, where τdf is the offset between two signals when τ0f<τ1f which can be calculated as
τdf=τ0f+(τ(n+1)−τcorr(n+1))a−(τ(n+1)−τcorr(n+1))b. (4-24)
As shown in
In order to have a robust and reliable controller, we developed an algorithm that is able to handle special cases such as rapid acceleration/deceleration, overlap of Hall signals of two motors, overlap of filtered and actual Hall signals, lagging or leading filtered Hall signals, etc. This Section describes the developed controller algorithm and the hardware prototype that satisfies stated requirements.
As mentioned previously, with one timer dedicated for rising edges and one for falling edges, the time interval between two edges of individual signals are recorded by reading the timer values at appropriate instances during the operation. After recording periods of the signals, filter conditions (i.e. not enough history terms, rapid acceleration/deceleration, deactivation of the filter by a manual switch, etc.) are verified as shown in
For filtering Hall signals, output filter interrupts may have to be switched before or after the next input interrupt (rising/falling edges) depending on many conditions. In first scenario, output software interrupt is invoked earlier making inverter switching happen before the actual Hall-sensor-signal-transition. This could happen for example when motor is under deceleration and/or when a given Hall sensor has an error in direction of rotation. Then, at the time of input ISR corresponding correction term τcorr(n) is calculated and used to schedule the next output software interrupt to make the inverter switch. In second scenario, actual Hall sensor signal comes ahead of what it should be in an ideal case. This may happen when the motor is accelerating and/or when a given Hall sensor has an error in opposite direction to the motor rotation. If this case, at the time of input ISR, when timer is reset to zero, next output software interrupt will be scheduled for the time determined by the difference τcorr(n−1)−τ(n−1). In addition to this, another filter output interrupt for next switching interval should be scheduled as well. This is simply done by calculating new correction term τcorr(n) and putting it as a second request for invoking the filter output interrupt.
For averaging Hall signals, in addition to period difference term, signal difference term (i.e. difference between the Hall signals of the two motors) is calculated. This term will only be available at the lagging signal interrupt. If it is the first time at lagging motor interrupt, the filtered Hall signals are just buffered through to the output but the output average interrupt is enabled. If it is not the first time at lagging motor interrupt, the average output interrupt is scheduled according to the signal difference term. Averaging of filtered Hall signals is also considered. Here, the two discussed scenarios (where the output filter interrupts may have to be switched before or after the next input interrupt) are taken care of inherently by defining the signal difference terms (4-23) and (4-24) with a positive leading motor period difference, (τ(n+1)−τcorr(n+1))a; and a negative lagging motor period difference, (τ(n+1)−τcorr(n+1))b.
The steps performed during the output ISR are shown in
The Sync-Lock Controller has been realized on a basic programmable integrated circuit microcontroller (dsPIC30f2020) [40]. This and similar microcontrollers are often used in many inexpensive DC drive systems [41].
Actual printed circuit board of the prototype and its simplified schematic are shown in
Hall sensors are simply connected with the DC driver through input and output ports provided on the board, thus enabling modification of Hall sensor signals according to the filtering and averaging methodologies. The filter equations (4-8) and (4-16) in conjunction with averaging equations (4-20)-(4-22) were programmed on the microcontroller according to the implementation approach summarized in previous section and the functional diagrams depicted in
An innovative approach is developed for synchronizing and locking multiple number of independently running DC motors. The new Sync-Lock Controller is based on filtering and averaging the Hall sensor signals and applying the same switching intervals to both motors. An analog and a digital implementation of the controller are developed and described in detail. As DC motors commonly have inaccurate Hall sensors, the hardware implementation also integrated filtering of the Hall sensor signals. Therefore by filtering and averaging the Hall sensor signals and applying the averaged switching intervals to both motors, we achieved desired locking/synchronizing.
The digital implementation of the controller is realized using a microcontroller. The controller is realized in the form of a standalone dongle-circuit that can be placed between the original Hall-sensors and the motor drive to process the signals. A compact prototype of the proposed dongle had been fabricated and texted on a number of typical industrial DC motors and drivers. Due to its simplicity and effective implementation, the developed algorithm can be readily applied to a variety of systems that use DC motors and drivers. The performance of the developed locking algorithm has been demonstrated using DC motors (with Hall-sensor positioning errors) and is shown to be efficient and robust in steady state and transients studies. The performance of developed SLC was evaluated under different conditions. It was shown that the SLC improves the performance of the system under certain conditions compared to the conventional PI speed control loops
In this patent document, the word “comprising” is used in its non-limiting sense to mean that items following the word are included, but items not specifically mentioned are not excluded. A reference to an element by the indefinite article “a” does not exclude the possibility that more than one of the element is present, unless the context clearly requires that there be one and only one of the elements.
The following claims are to be understood to include what is specifically illustrated and described above, what is conceptually equivalent, and what can be obviously substituted. Those skilled in the art will appreciate that various adaptations and modifications of the described embodiments can be configured without departing from the scope of the claims. The illustrated embodiments have been set forth only as examples and should not be taken as limiting the invention. It is to be understood that, within the scope of the following claims, the invention may be practiced other than as specifically illustrated and described.
