Patent Application
20210365239
The present invention relates to a logarithm calculation method.
In a conventional logarithm calculation circuit, a coordinate rotation digital computer (CORDIC) is usually used to achieve logarithm calculations. However, the above method needs to store a large parameter table, and also need to use many multipliers with complicated circuit designs. Therefore, it will increase the complexity and cost of the circuit design.
It is therefore an objective of the present invention to provide a logarithm calculation method and related circuits, which only need two addition operations and one shift operation in each iteration operation, so the circuit design can be greatly simplified to solve the problems in the prior art.
According to one embodiment of the present invention, a logarithm calculation method for performing a logarithm operation on an initial input value is disclosed. The logarithm calculation method comprises the steps of: (a) selecting a first parameter, a second parameter, a third parameter and a fourth parameter corresponding to an i-th iteration operation; (b) determining whether an input value is greater than the third parameter, or smaller than the fourth parameter, or between the third parameter and the fourth parameter, wherein the input value is obtained by the initial input value; (c) if the input value is greater than the third parameter, updating the input value by multiplying the first parameter, and updating an output value by subtracting a logarithmic value of the first parameter; if the input value is less than the fourth parameter, updating the input value by multiplying the second parameter, and updating the output value by subtracting a logarithmic value of the second parameter; and if the input number is between the third parameter and the fourth parameter, not changing the input value and output value; (d) adding one to the value ‘i’ and return to step (a) until the value ‘i’ is equal to a predetermined value; and (e) when the value ‘i’ is equal to the predetermined value, using the current output value as a calculation result of the logarithm operation of the initial input value.
According to one embodiment of the present invention, a logarithm calculation circuit for performing a logarithm operation on an initial input value is disclosed. The logarithm calculation circuit comprises an iteration operation circuit, for performing multiple iteration operations in sequence, wherein for any iteration operation performed by the iteration operation circuit, the iteration operation circuit performs the following operations: (a) selecting a first parameter, a second parameter, a third parameter and a fourth parameter corresponding to an i-th iteration operation; (b) determining whether an input value is greater than the third parameter, or smaller than the fourth parameter, or between the third parameter and the fourth parameter, wherein the input value is obtained by the initial input value; (c) if the input value is greater than the third parameter, updating the input value by multiplying the first parameter, and updating an output value by subtracting a logarithmic value of the first parameter; if the input value is less than the fourth parameter, updating the input value by multiplying the second parameter, and updating the output value by subtracting a logarithmic value of the second parameter; and if the input number is between the third parameter and the fourth parameter, not changing the input value and output value; (d) using the updated input value and the updated output value as the input value and the output value of the next iteration operation; wherein the output value generated by the last iteration operation of the iteration operation circuit is used as a calculation result of the logarithm operation of the initial input value.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
It should be noted that since the above parameters xa(1) and xb(1) satisfy the conditions of 1−2{circumflex over ( )}(−1) and 1+2{circumflex over ( )}(−1) respectively, therefore, the calculation x*xa(1) in Step 108 can be implemented by a shift register and an adder in a circuit design, that is, x*xa(1)=x*(1−2{circumflex over ( )}(−1))=x−x>>1, where “>>” is a shift operator. Similarly, the calculation x*xb(1) in Step 110 can be implemented by a shift register and an adder in a circuit design, that is, x*xb(1)=x*(1+2{circumflex over ( )}(−1))=x+x>>1, where “>>” is the shift operator.
In the second iteration operation, the parameters xa(2), xb(2), limit_up(2), limit_low(2) included in the second group of parameters and selected in Step 104 are (3/4), (5/4), (8)/7), (8/9), respectively. In Step 106, it is determined that if the initial input value x is larger than the parameter limit_up(2) or smaller than the parameter limit_low(2). If the initial input value x is greater than the parameter limit_up(2), the flow enters Step 108; if the initial input value x is less than the parameter limit_low(2), the flow enters Step 110; and if the initial input value x is between the parameters limit_up(2) and limit_low(2), the flow enters Step 112. In Step 108, the input value x is updated by multiplying the parameter xa(2), and the output value y is updated by subtracting ln(xa(2)), that is x=x*xa(2), and y=y−ln(xa(2)). In Step 110, the input value x is updated by multiplying the parameter xb(2), and the output value y is updated by subtracting ln(xb(2)), that is, x=x*xb(2) and y=y−ln(xb(2)).
Because the above parameters xa(2) and xb(2) satisfy the conditions of 1−2{circumflex over ( )}(−2) and 1+2{circumflex over ( )}(−2) respectively, the calculation x*xa(2) in Step 108 can be implemented by a shift register and an adder in a circuit design, that is, x*xa(2)=x*(1−2{circumflex over ( )}(−2))=x−x>>2. Similarly, the calculation x*xb(2) in Step 110 can be implemented by a shift register and an adder in a circuit design, that is, x*xb(2)=x*(1+2{circumflex over ( )}(−2))=x+x>>2.
Then, the third iteration operation, the fourth iteration operation, . . . , are executed until a predetermined value of the system, for example, after the eighth iteration operation is completed, the calculated output value y is used as a final calculation result, that is, the logarithm calculation result of the initial input value.
In one embodiment, the parameters xa(i), xb(i), limit_up(i), limit_low(i) used in each iteration operation are designed as shown in Table 1 and Table 2.
By using the parameters of the above table, the input value x after the first iteration operation is between (2/3) and (4/3), the input value x after the second iteration operation is between (5/6) and (8/7), the input value x after the third iteration operation is between (14/15) and (16/15), the input value x after the fourth iteration operation is between (30/31) and (32/31), and the input value x after the fifth iteration operation is between (62/63) and (64/63), the input value x after the sixth iteration operation is between (126/127) and (128/127), . . . , and so on. That is, as the number of the iteration operations increases, the value of the input value x will approach one, thus making the output value y closer to the ideal value. In an example, if sixteen iteration operations are performed, the error between the output value y and the ideal value is 7.6*10{circumflex over ( )}(−6).
As mentioned in the above table, since the parameters xa(i) and xb(i) satisfy the conditions of 1−2{circumflex over ( )}(−i) and 1+2{circumflex over ( )}(−i), the calculation of the input value x can be implemented by a shift register and an adder for each iteration operation. In addition, since the parameters xa(i), xb(i), limit_up(i), and limit_low(i) are all constants, the logarithmic values of these parameters can be calculated in advance for establishing a lookup table, for use of the calculation of the output value y in each iteration operation, that is, the calculation of the output value y in each iteration operation can be implemented by only one adder. In summary, each iteration operation requires only one shift operation, two addition operations and two comparison operations. Therefore, the complexity in the logarithm calculation process can be effectively reduced, and the manufacturing and design costs of the circuit can also be reduced.
Briefly summarized, in the logarithm calculation method and related circuits of the present invention, by designing special parameters and iteration operations, each iteration operation can be achieved through only one shift register and two adders. Therefore, the complexity in the logarithm calculation process can be effectively reduced, and the manufacturing and design costs of the circuit can also be reduced.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202010446312.0 | May 2020 | CN | national |
