LOGARITHMIC CURRENT TO VOLTAGE CONVERTERS WITH EMITTER RESISTANCE COMPENSATION

Abstract

Logarithmic current-to-voltage converters with emitter resistance compensation are disclosed herein. In certain embodiments, a logarithmic current-to-voltage converter includes a logarithmic bipolar transistor that converts an input current to a logarithmic voltage, and an emitter resistance compensation circuit that includes a replica of the logarithmic bipolar transistor. The emitter resistance compensation circuit processes a copy of the input current to generate an emitter resistance compensation signal that adjusts the logarithmic voltage to correct for an error introduced by an emitter resistance of the logarithmic bipolar transistor. By providing emitter resistance compensation in this matter, logarithmic current-to-voltage conversion with high accuracy and low log error is achieved.

Description

FIELD OF THE DISCLOSURE

Embodiments of the invention relate to electronic systems, and more particularly to, electronic circuits for logarithmic conversion or detection.

BACKGROUND

Logarithmic converters or detectors provide an output signal that changes in relation to a logarithm of an applied input signal.

One type of logarithmic detector is a trans-linear logarithmic detector that uses the trans-linear properties of a bipolar transistor to provide logarithmic conversion. In one example, a collector and a base of an NPN bipolar transistor are directly connected to a gate and a source, respectively, of an n-type metal-oxide-semiconductor (NMOS) transistor. Additionally, an input current is applied to the collector of NPN bipolar transistor and the base of the NPN bipolar transistor generates a log voltage. Although such a circuit can provide logarithmic detection, the collector-to-base voltage of the NPN bipolar transistor is not very close to zero, leading to undesirable performance characteristics such as poor log-linear dynamic range for small input currents.

In another example of a trans-linear logarithmic detector, a collector and an emitter of an NPN bipolar transistor are directly connected to an inverting input and an output, respectively, of an operational amplifier (op-amp). Additionally, a base of the NPN bipolar transistor and a non-inverting input of the op-amp are grounded, while an input current is applied to the collector of NPN bipolar transistor such that the emitter of the NPN bipolar transistor generates a log voltage. By using the op-amp, the collector-to-base voltage of the NPN bipolar transistor can be controlled close to zero.

In certain applications, a second copy of a logarithmic detector is included and driven by a reference current, with a difference between the pair of logarithmic detectors taken to cancel the saturation current of the NPN bipolar transistor.

SUMMARY OF THE DISCLOSURE

Logarithmic current-to-voltage converters with emitter resistance compensation are disclosed herein. In certain embodiments, a logarithmic current-to-voltage converter includes a logarithmic bipolar transistor that converts an input current to a logarithmic voltage, and an emitter resistance compensation circuit that includes a replica of the logarithmic bipolar transistor. The emitter resistance compensation circuit processes a copy of the input current to generate an emitter resistance compensation signal that adjusts the logarithmic voltage to correct for an error introduced by an emitter resistance of the logarithmic bipolar transistor. By providing emitter resistance compensation in this matter, logarithmic current-to-voltage conversion with high accuracy and low log error is achieved.

In one aspect, a logarithmic current to voltage converter includes an input terminal configured to receive an input current, a logarithmic bipolar transistor having a collector connected to the input terminal and an emitter configured to generate a logarithmic output voltage, and an emitter resistance compensation circuit comprising a replica of the logarithmic bipolar transistor. The emitter resistance compensation circuit is configured to receive a copy of the input current and to generate a compensation signal operable to adjust the logarithmic voltage to correct for an error arising from an emitter resistance of the logarithmic bipolar transistor.

In another aspect, a photocurrent detection system includes a photodetector configured to generate an input current, and a semiconductor die including a logarithmic converter. The logarithmic converter includes an input terminal configured to receive the input current, a logarithmic bipolar transistor having a collector connected to the input terminal and an emitter configured to generate a logarithmic output voltage, and an emitter resistance compensation circuit comprising a scaled replica of the logarithmic bipolar transistor. The emitter resistance compensation circuit is configured to receive a scaled copy of the input current and to generate a compensation signal operable to adjust the logarithmic voltage to correct for an error arising from an emitter resistance of the logarithmic bipolar transistor.

In another aspect, a method of logarithmic current to voltage conversion is provided. The method includes providing an input current from an input terminal to a collector of a bipolar transistor, providing a logarithmic output voltage from an emitter of the logarithmic bipolar transistor, and generating a compensation signal using an emitter resistance compensation circuit that includes a scaled replica of the logarithmic bipolar transistor. Generating the compensation circuit includes receiving a scaled copy of the input current as an input to the emitter resistance compensation circuit and adjusting the logarithmic voltage to correct for an error arising from an emitter resistance of the logarithmic bipolar transistor using the compensation signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic diagram of one embodiment of a logarithmic converter.

FIG. 1B is a schematic diagram of one embodiment of a logarithmic conversion system.

FIG. 2 is a schematic diagram of one embodiment of a logarithmic conversion system with emitter resistance compensation.

FIG. 3 is a schematic diagram of one embodiment of an emitter resistance compensation circuit.

FIG. 4 is a graph of one example of logarithmic output voltage versus input current.

FIG. 5 is a schematic diagram of one example of a bipolar differential pair.

FIG. 6 is a graph of one example of an emitter resistance compensation simulation.

FIG. 7 is a graph of one example of base-to-emitter voltage change versus differential voltage.

FIG. 8 is a graph of one example of logarithmic conformance error versus input current.

DETAILED DESCRIPTION

The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to drawings. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.

FIG. 1A is a schematic diagram of one embodiment of a logarithmic converter 105.

In the illustrated embodiment, the logarithmic converter 105 includes a FET transistor (NMOS, in this example), a first bipolar transistor NPN_LOG (n-type, in this example), a second bipolar transistor NPN_LV (n-type, in this example), a first DC current source I_DC1, a second DC current source I_DC2, a capacitor C, and a resistor R.

The NMOS transistor includes a drain that receives a power supply voltage +Vc, and a gate connected to a collector of the first bipolar transistor NPN_LOG and to an input terminal. The input terminal receives an input current I_IN and has an input voltage VIN. The NMOS transistor further includes a source connected to a base of the second bipolar transistor NPN_LV and to the first DC current source I_DC1. Additionally, a base of the first bipolar transistor NPN_LOG receives a reference voltage V_REF and an emitter of the first bipolar transistor NPN_LOG is connected to an output terminal that provides a logarithmic voltage V_LOG. The emitter of the first bipolar transistor NPN_LOG is also connected to the second DC current source I_DC2 and to a collector of the second bipolar transistor NPN_LV. The resistor R is connected between an emitter of the second bipolar transistor NPN_LV and ground, and the capacitor C is connected in parallel with the resistor R.

As shown in FIG. 1A, the input current I_IN received from the input terminal is provided to the collector of the first bipolar transistor NPN_LOG. Additionally, the logarithmic converter 105 converts the input current I_IN into the logarithmic voltage V_LOG, which is provided at the output terminal.

In the illustrated embodiment, the capacitor C operates to extend the bandwidth of the collector current over base voltage while the resistor R reduces the loop gain at high levels of the input current I_IN. In certain implementations, the capacitor C and/or the resistor R are controllable (for example, by using a capacitor array that is programmable to control a capacitance value and/or a resistor array that is programmable to control a resistance value).

The logarithmic converter 105 can achieve a higher speed relative to a configuration using an op-amp to provide feedback. For example, when an op-amp is included in the feedback loop, the additional components introduce extra phase shift that moves the second-order pole downwards in frequency. Although high value compensation capacitors can be added to keep such a feedback loop stable, high capacitance slows the circuit down.

Furthermore, the logarithmic converter 105 has superior noise performance at low levels of the input current I_IN relative to an implementation with an op-amp in the feedback loop. For example, when an op-amp provides feedback at low input current levels, the bandwidth of the circuit reduces considerably, resulting in the loop gain to drop below 0 dB at a frequency below the baseband bandwidth of the rest of the circuit. This results in the loop not cancelling the bias noise sources in a significant manner. In that case, any noise voltage present on the reference voltage will be amplified significantly by the op-amp.

In contrast, any noise on the reference voltage V_REF in FIG. 1A will be amplified much less since the amplification at the base of the first bipolar transistor NPN_LOG (which is connected as a common-base stage) is much lower.

FIG. 1B is a schematic diagram of one embodiment of a logarithmic conversion system 120. The logarithmic conversion system 120 includes a first logarithmic converter 105a, a second logarithmic converter 105b, a reference current source I_REF, and a reference voltage source 106 that includes a third logarithmic converter 105c, a DC current source I_DC, a reference voltage source V_REF2, an adder 111, an offset trim circuit 112, and a buffer 113. The logarithmic conversion system 120 is also depicted with an input current source I_IN, which represents a photodiode or other input current source to the system 120.

As shown in FIG. 1B, multiple instantiations or replicas of the logarithmic converter 105 of FIG. 1A have been arranged to provide logarithmic current to voltage conversion with enhanced performance. In particular, the first logarithmic converter 105a serves as an input channel, the second logarithmic converter 105b serves as a reference channel, and the third logarithmic converter 105c serves as a DC channel.

In the illustrated embodiment, the DC current from the DC current source I_DC is provided as an input to the third logarithmic converter 105c, which is biased by the reference voltage source V_REF2. Additionally, the buffer 113 buffers the input voltage to the third logarithmic converter 105c. The buffered voltage from the buffer 113 is trimmed by the offset trim circuit 112 to generate a reference voltage V_REF for the first logarithmic converter 105a and the second logarithmic converter 105b.

By implementing the logarithmic conversion system 120 in this manner, high dynamic range is achieved by setting the voltage reference V_REF in such a manner that the collector-to-emitter voltages (of bipolar transistors NPN_LOG within the converters 105a and 15b) are close to zero. In particular, the logarithmic conversion system 120 applies a DC current to the third logarithmic converter 105c, which is biased with the reference voltage source V_REF2. The precision of the reference voltage source V_REF2 can be relaxed compared to a precision of the reference voltage V_REF since the DC current from the DC current source I_DC can be scaled to be much higher than a minimum value of the input current I_IN.

With continuing reference to FIG. 1B, the input channel (the first logarithmic converter 105a), the reference channel (the second logarithmic converter 105b), and the DC channel (the third logarithmic converter 105c) can be scaled in size to provide enhanced performance. In one implementation, the input channel and the reference channel have a scaling factor 8 while the DC channel has a scaling factor 2. Although one example of scaling factors is provided, other scaling factors can be used.

Since the DC current from the DC current source I_DC can be chosen to be in the middle of the dynamic range of the input current source I_IN (for instance, 10 μA), larger deviations around zero of the collector-base voltage of bipolar transistor NPN_LOG has little to no impact on accuracy.

As shown in FIG. 1B, the log voltage V_{LOG 2} is taken differentially between the V_LOG outputs of the first logarithmic converter 105a and the second logarithmic converter 105b. By using a differential voltage between the input channel and the reference channel, the saturation current of the bipolar transistors (NPN_LOG transistors within converters 105a and 105b) is canceled.

In the illustrated embodiment, the buffer 113 is a voltage buffer with unity gain (+1). The buffer 113 is applied to the input voltage of the DC channel to bias the input and reference channels (V_REF voltages). The offset trim circuit 112 can be used to correct for mismatches and/or for the difference between the DC current in the DC channel and the lowest input current in the input channel.

Moreover, in certain embodiments, the offset trim circuit 112 applies a correction voltage, such as a proportional to temperature (PTAT) voltage (for instance, around 50 mV) which is added to the reference voltage V_REF to correct for low input current I_IN and/or high temperature deviations.

Absent compensation, the logarithmic conversion circuits of FIGS. 1A and 1B can suffer from logarithmic error introduced by the emitter resistance (RE) of the transistor used for logarithmic current-to-voltage conversion.

For example, an optical log converter uses the logarithmic relationship between the base-emitter voltage (V_BE) and the collector current (I_C) of a bipolar junction transistor. Additionally, a log amp that employs this property of a bipolar transistor is referred to as a logarithmic trans-impedance amplifier.

With reference back to FIGS. 1A and 1B, the bipolar transistor of an input channel (the first logarithmic converter 105a of FIG. 1B) can have a first emitter resistance RE1, and the bipolar transistor of a reference channel (the second logarithmic converter 105b of FIG. 1B) can have a second emitter resistance RE2. If RE1≠0 and RE2≠0 an error is introduced causing the V_LOG curve to change at the higher end of the input current range.

Logarithmic current-to-voltage converters with emitter resistance compensation are disclosed herein. In certain embodiments, a logarithmic current-to-voltage converter includes a logarithmic bipolar transistor that converts an input current to a logarithmic voltage, and an emitter resistance compensation circuit that includes a replica of the logarithmic bipolar transistor. The emitter resistance compensation circuit processes a copy of the input current to generate an emitter resistance compensation signal that adjusts the logarithmic voltage to correct for an error introduced by an emitter resistance of the logarithmic bipolar transistor.

By providing emitter resistance compensation in this matter, logarithmic current-to-voltage conversion with high accuracy and low log error is achieved.

FIG. 2 is a schematic diagram of one embodiment of a logarithmic conversion system 130 with emitter resistance compensation. The logarithmic conversion system 130 includes an input channel 125a (receiving an input current I(INP)), a reference chancel 125b, a reference voltage source V_REF, a reference current source I_REF (provided to the reference channel 125b), and an output amplifier (OA1, which can be an operational amplifier) for processing a differential logarithmic voltage provided across the output nodes (E and Eref) of the input channel 125a and the reference chancel 125b.

The output amplifier OA1 is biased by various current sources (IB1, IB2, and I_PTLS+I_Re) as shown, and includes input resistors (of resistance R1) at each of the positive and negative inputs, a feedback resistor (of resistance R1) from output to negative input, and a bias resistor (of resistance R1) from the positive input to ground. The output amplifier OA1 serves to output the difference voltage between E and Eref plus an offset to generate a unipolar logarithmic signal, which in certain implementations is processed by an analog temperature compensation circuit to compensate for absolute temperature T.

The input channel 125a and the reference channel 125b have a configuration similar to that of FIG. 1A, except that particular example resistance values are depicted and the parasitic emitter resistances of the bipolar transistors NPN_LOG 1 and NPN_LOG 2 are shown. In particular, the input channel 125a includes logarithmic bipolar transistor NPN_LOG 1 with a first emitter resistance RE1, while the reference channel 125b includes reference bipolar transistor NPN_LOG 2 with a second emitter resistance RE2.

If RE1≠0 and RE2≠0 an error is introduced causing the V LOG curve to change at the higher end of the input current range. This is caused by a voltage drop over RE1 that lowers the E node voltage at high input currents and thus increases V (Eref−E) by a value of V_Re=RE1·I(INP). Typically, RE2 doesn't introduce a significant error because the internal reference current is sufficiently low not to affect V(Eref−E) much. However, if the reference current is sourced externally, for example in current-ratio applications, RE2 can introduce a significant error as well if I(IREF) is high.

The logarithmic conversion system 130 includes the emitter resistance compensation circuit 126 to compensate for this effect. In the illustrated embodiment, the emitter resistance compensation circuit 126 includes a scaled replica or copy of the logarithmic bipolar transistor NPN_LOG 1. The scaled replica processes a copy 127 of the input current (IINP), which can be scaled down in value to reduce power dissipation. The emitter resistance compensation circuit 126 processes the input current copy 127 to generate an emitter resistance compensation signal for compensating the logarithmic voltage of the logarithmic conversion system 130.

In the illustrated embodiment, the emitter resistance compensation signal corresponds to a correction current IRE that is provided to a positive input of the output amplifier OA1 to provide a correction to the logarithmic voltage. However, other types of correction signal schemes can be used.

Any suitable circuit (for example, any suitable current mirror) can provide the scaled replica of the input current to the emitter resistance compensation circuit 126.

FIG. 3 is a schematic diagram of one embodiment of an emitter resistance compensation circuit. In this example, the emitter resistance compensation circuit includes two replica transistors (replicas of the logarithmic bipolar transistor NPN_LOG 1 of FIG. 2) with a large current density ratio driven by a scaled down copy of the input current compensated by the natural logarithm of the current density ratio multiplied by a thermal voltage. By implementing the emitter resistance compensation circuit in this manner, a compensation signal (IRE, in this example) proportional with the emitter resistance times the input current is generated.

Because the replica transistor's emitter resistance is matching the logging transistor's emitter resistance with a scaling factor, the accuracy of the compensation versus process and temperature is improved as compared to using a discrete resistor in the compensation circuit.

Thus, a lower scaled copy of the input current I(INP) is provided by the collector current of NPN_MON1. NPN_LOG 1 is the same device in both FIGS. 2 and 3.

The circles in FIG. 3 indicate that the emitter resistance (fraction) is part of the transistor itself, not a separate component.

NPN3 receives a collector current of I(INP)/32 plus a PTAT current 2·I_PTAT. Additionally, the current density in NPN3 is 4 times the current density in NPN_LOG 1 at high input currents I(INP). Furthermore, NPN4 receives a collector current of I(INP)/64 plus a current I_PTAT.

With continuing reference to FIG. 3, a PTAT voltage V_R4 equal to the natural logarithm of the ratio of the current densities of NPN3 and NPN4 times a thermal voltage

$V_T=\frac{k·T}{q}$

is added to the NPN4 base-emitter voltage.

Furthermore, a PNP differential pair receives the NPN3 base-emitter voltage and the NPN4 base-emitter voltage+V_R4 as an input.

The PTAT current is given by:

$I_{PTAT}=\frac{k·T}{q·4·R_1}LN\left(A\right)$

with A=8 the emitter ratio and 4·R1 the resistor that sets the current in the bandgap of the PTAT current generator.

For I(INP)=0 the differential pair input voltage V_N is given by

$V_N=\frac{k·T}{q}·\mathrm{LN}\left(\frac{I\left(\mathrm{INP}\right)/16+2·I_{\mathrm{PT}\mathrm{AT}}}{I_S}\right)+R_e·\left(2·I_{\mathrm{PT}\mathrm{AT}}+I\left(\mathrm{INP}\right)/16\right).$

This can be expressed as

$V_N=\frac{k·T}{q}·\mathrm{LN}\left(\frac{I\left(\mathrm{INP}\right)/16+2·I_{\mathrm{PT}\mathrm{AT}}}{4·I_S}\right)+\frac{k·T}{q}·\mathrm{LN}\left(4\right)+2·R_e·\left(I_{\mathrm{PT}\mathrm{AT}}+I\left(\mathrm{INP}\right)/32\right),$ $\mathrm{or}$ $V_N=\mathrm{term}1n+\mathrm{term}2n+\mathrm{term}3n.$

Assuming base currents for T₁₀ and T₁₁ are zero, the voltage drop over R₄ is

$V_{R4}=I_{\mathrm{PT}\mathrm{AT}}·R_4=\frac{k·T}{q·4·R_1}\mathrm{LN}\left(8\right)·4·R_1=\frac{k·T}{q}·\mathrm{LN}\left(8\right).$

For I(INP)=0 the differential pair input voltage V_P is given by

$V_P=\frac{k·T}{q}·\mathrm{LN}\left(\frac{I\left(\mathrm{INP}\right)/32+I_{\mathrm{PT}\mathrm{AT}}}{4·I_S}\right)+\frac{k·T}{q}·\mathrm{LN}\left(8\right)+0\text{.25}·R_e·\left(I_{\mathrm{PT}\mathrm{AT}}+I\left(\mathrm{INP}\right)/32\right).$

This can be expressed as

$V_P=\frac{k·T}{q}·\mathrm{LN}\left(\frac{I\left(\mathrm{INP}\right)/16+2·I_{\mathrm{PT}\mathrm{AT}}}{4·I_S}\right)+\frac{k·T}{q}·\mathrm{LN}\left(0.5\right)+\frac{k·T}{q}·\mathrm{LN}\left(A\right)+0\text{.25}·R_e·\left(I_{\mathrm{PT}\mathrm{AT}}+I\left(\mathrm{INP}\right)/32\right)$

or V_P=term1p+term2p+term3p+term4p, where term1p−term1n=0.

With continuing reference to FIG. 3,

$\mathrm{term}2p+\mathrm{term}3p-\mathrm{term}2n=\frac{kT}{q}·\mathrm{LN}\left(0.5\right)+\frac{k·T}{q}·\mathrm{LN}\left(8\right)-\frac{k·T}{q}·\mathrm{LN}\left(4\right)=\frac{k·T}{q}·\mathrm{LN}\left(1\right)=0.$

Additionally, rm4p−term3n=0.25·R_e·(I_PTAT+I(INP)/32)−2·R_e·(I_PTAT+I(INP)/32), and V_P−V_N=term4p−term3n=−1.75·R_e·(I_PTAT+I(INP)/32).

Accordingly, transistors T₁₅ to T₂₂ and resistors Rk, Rn and R₃ are for base current compensation. Additionally, the differential pair output current can drive the positive input of the amplifier OA1 of FIG. 2.

The output voltage of the input stage and level shifter with R_e=64·RE1 is given by

$\mathrm{dV}\mathrm{BE}=V\left(\mathrm{Eref}-E\right)+I\left(\mathrm{INP}\right)·R_e/64+I_{\mathrm{Re}}·R_1+I_{\mathrm{PTLS}0}·\frac{T}{T_0}·R_1,$

where I_PTLS0 is the PTAT level-shift current I_PTLS at temperature T=T₀ and R_e=64·RE1 and RE2·I(IREF)<<1 mV.

Furthermore,

$I_{\mathrm{Re}}=I_{\mathrm{PT}\mathrm{AT}}·\tanh \left(\frac{V_P-V_N}{2·V_T}\right)$ $\mathrm{for}$ $❘V_N-V_P❘<V_T:I_{\mathrm{Re}}\approx \frac{q·\left(V_P-V_N\right)}{2·k·T}·I_{\mathrm{PT}\mathrm{AT}}.$

Additionally,

$I_{\mathrm{PT}\mathrm{AT}}=\frac{k·T}{q·4·R_1}LN\left(8\right)\approx \frac{k·T}{q·2·R_1}$ $\mathrm{and}$ $I_{\mathrm{Re}}\approx \frac{q·\left(V_P-V_N\right)}{2·k·T}·\frac{k·T}{q·2·R_1}=\frac{V_P-V_N}{4·R_1}.$

With continuing reference to FIG. 3,

$V_P-V_N=-1\text{.75}·R_e·(I_{\mathrm{PTAT}}+I\left(\mathrm{INP}\right)/32=-1.75·R_e·I_{\mathrm{PT}\mathrm{AT}}-7/128·R_e·I\left(\mathrm{INP}\right).$

Additionally,

$I_{\mathrm{Re}}·R_1=\frac{V_P-V_N}{4}=-7/16·R_e·\left(I_{\mathrm{PT}\mathrm{AT}}+I\left(\mathrm{INP}\right)/32\right)=-7/16·R_e·I_{\mathrm{PT}\mathrm{AT}}-7/512·R_e·I\left(\mathrm{INP}\right)$ $\mathrm{and}$ $I\left(\mathrm{INP}\right)·R_e/64+I_{\mathrm{Re}}·R_1=\left(8/512-7/512\right)·R_e·I\left(\mathrm{INP}\right)-0.4375·R_e·I_{\mathrm{PT}\mathrm{AT}}.$

Thus, with emitter resistance compensation I(INP)·R_e/64+I_Re·R₁=( 8/512− 7/512)·R_e·I(INP)−0.4375·R_e·I_PTAT, and

$\mathrm{dVBE}=V\left(\mathrm{Eref}-E\right)+1/512·R_e·I\left(\mathrm{INP}\right)-0.4375·R_e·I_{\mathrm{PT}\mathrm{AT}}+I_{\mathrm{PTLS}0}·\frac{T}{T_0}·R_1.$

Compared to dVBE without compensation, error due to R_e is reduced by a factor of 512/64=8.

With reference to FIGS. 2 and 3, without emitter resistance compensation, the input stage output voltage of FIG. 2 is given by

$\mathrm{dV}\mathrm{BE}=V\left(\mathrm{Eref}-E\right)+1/64·R_e·I\left(\mathrm{INP}\right)+I_{\mathrm{PTLS}0}·\frac{T}{T_0}·R_1.$

Due to the R_e compensation, an offset is introduced with value V_OS=− 7/16·R_e·I_PTAT.

Additionally,

$\mathrm{dBx}=20·{\mathrm{Log}}_{10}\left(\frac{I\left(\mathrm{INP}\right)}{I\left(\mathrm{IREF}\right)}\right)=\frac{20·q}{k·T·\mathrm{LN}\left(10\right)}·V\left(\mathrm{Eref}-E\right)$ $\mathrm{and}$ $I_{\mathrm{PTAT}}=\frac{k·T}{q·4·R_1}LN\left(8\right)\approx \frac{k·T}{q·2·R_1}\text{=>}{V}_{\mathrm{OS}}=-7/16·R_e·\frac{k·T}{q·2·R_1}.$

A dB value dBxos can be assigned to this offset to be

$\mathrm{dBxos}=\frac{20·q}{k·T·\mathrm{LN}\left(10\right)}·-7/16·\frac{k·T}{q·2·R_1}·R_E=\frac{-35}{8·\mathrm{LN}\left(10\right)}·\frac{R_e}{R_1}\approx -1.9·\frac{R_e}{R_1}.$

For typical values for R_e=64 and R₁=4000, the offset will be −0.03 dB. This offset is temperature independent as long as R_e is temperature independent and can be reduced or eliminated by calibration.

Moreover, by changing the shared bias current of T₁₀ and T₁₁ from I_PTAT to

$\frac{16}{7·\mathrm{LN}\left(8\right)}·I_{\mathrm{PTAT}}\approx 1.1·I_{\mathrm{PTAT}},$

the R_e·I(INP) term would be zero. The shared bias current of T₁₀ and T₁₁ can be chosen less than PTAT which reduces the effect of more pronounced peaking at cold and high input currents.

By including the emitter resistance compensation circuit of FIG. 3, the output voltage of the input stage of FIG. 2 is now given by

$\mathrm{dVBE}=V\left(\mathrm{Eref}-E\right)+1/512·R_e·I\left(\mathrm{INP}\right)-0.4375·R_e·I_{\mathrm{PTAT}}+I_{\mathrm{PTLS}0}·\frac{T}{T_0}·R_1.$

Accordingly, the error introduced by emitter resistance is decreased by a factor of 8.

Moreover, a new factor of −0.4375·R_e·I_PTAT introduces an offset in dB of

$\mathrm{dBxos}\approx -1.9·\frac{R_e}{R_1}\left[\mathrm{dB}\right],$

which typically is small and can be eliminated by calibration.

With reference back to FIG. 2, we can define

$\mathrm{dBx}=20·{\mathrm{Log}}_{10}\left(\frac{I\left(\mathrm{INP}\right)}{I\left(\mathrm{REF}\right)}\right)=\frac{20·q}{k·T·\mathrm{LN}\left(10\right)}·V\left(\mathrm{Eref}-E\right)$

[hereinafter Equation 1] with dBx the ratio in dB between I(INP) and/(IREF), assuming RE1=0 and RE2=0 and LN(x)=Log_e(x).

In log ratio applications, both I(INP) and I(IREF) may each vary over the full specified range of 1 nA to 10 mA. However, in default operation, the reference current is generated internally. It is defined as I_REF if this current is internally generated. I_REF is trimmed for best V LOG vs I(INP) logarithmic conformance. Thus,

$\begin{array}{cc}V\left(\mathrm{Eref}-E\right)=\frac{\mathrm{dBx}·k·T·\mathrm{LN}\left(10\right)}{20·q}.& \left[\mathrm{hereinafter}\mathrm{Equation}2\right]\end{array}$

Equation 2 shows that the V(Eref−E) is still proportional-to-absolute-temperature (PTAT) and temperature variation of k·T/q is subsequently eliminated by temperature compensation circuitry that essentially puts a variable proportional to absolute temperature underneath the T in Equation 2 and raising the magnitude to a stable value of 10 mV/dB or 200 mV/decade. Therefore, for photodiode applications, using this correction the relationship between a photodiode current, I_PD, applied to the INP pin, and the voltage appearing at the output at V LOG is given by V LOG=V_Y·Log₁₀(I_PD/I_NT) [hereinafter Equation 3]. Here, V_Y is the log slope voltage (and, for the case of base-10 logarithms, it is also the volts per decade) and I_INT is the extrapolated log X-axis intercept.

The output at V LOG can also be expressed as

$\begin{array}{cc}\mathrm{VLOG}=0.01·\mathrm{dBx}=\frac{0.2·q}{k·T·\mathrm{LN}\left(10\right)}·V\left(\mathrm{Eref}-E\right).& \left[\mathrm{hereinafter}\mathrm{Equation}4\right]\end{array}$

The relationship between V_Y and V(Eref−E) is 3.33 at T=302.4K in the default configuration. For a factor of 10 between I(INP) and I_REF, V(Eref−E)=60 mV at T=302.4K, resulting in a slope of 0.2 V/decade.

In certain implementations, during fabrication, V_Y is set to 0.2 V/decade (10 mV/dB) and I_INT=10 pA by factory trim.

The output at V LOG can further be expressed as V LOG=0.2 V·Log₁₀(I_PD/10 pA) [hereinafter Equation 5]. The output for the value of I_PD can be calculated using Equation 5. For example, for I_PD=10 nA, the output V LOG has a value of 0.6 V. When I_PD=100 pA, the output V LOG has a value of 0.2 V.

FIG. 4 is a graph of one example of logarithmic output voltage versus input current. The graph shows the input/output relation of an ideal log-amp. Horizontal scale is logarithmic and spans a wide dynamic range. Output passes through zero at I_INP=I_INT.

The emitter resistance compensation schemes herein correct errors in the input/output relation of a log-amp arising from emitter resistance.

For example, if RE1≠0 and RE2≠0, an error is introduced causing the V LOG curve to change at the higher end of the input current range. This is caused by a voltage drop over RE1 that lowers the ‘E’ node voltage at high input currents and thus increases V(Eref−E) by a value of V_Re= 1/64·R_e·I(INP), with R_e=64·RE1.

$\begin{array}{cc}\mathrm{Thus},\mathrm{dVBE}=V\left(\mathrm{Eref}-E\right)+1/64·R_e·I\left(\mathrm{INP}\right)+I_{\mathrm{PTLS}0}·\frac{T}{T_0}·R_1.& \left[\mathrm{hereinafter}\mathrm{Equation}6\right]\end{array}$

Typically, RE2 doesn't introduce a significant error because the internal reference current is low enough not to affect V(Eref−E) much. If the reference current is sourced externally, for example in current-ratio applications, RE2 can introduce a significant error as well if (IREF) is high.

From Equation 1 above, at T=302.4K the logarithmic error is 0.333 dB/mV drop over RE1.

FIG. 5 is a schematic diagram of one example of a bipolar differential pair, in which T1/T2 are equal area and T3/T4 are equal area.

With reference to FIG. 5,

$I_{C1}\approx I_S·e^{\frac{V_E-V_N}{V_T}}$

and

$I_{C2}\approx I_S·e^{\frac{V_E-V_P}{V_T}}$

for I_C1, I_C2>>I_S, where

$V_T=\frac{k·T}{q}$

with Boltzmann's constant k, electron charge q and absolute temperature T.

Thus,

$I_{C1}\approx I_S·e^{\frac{V_E-V_N}{V_T}}$

and

$I_{C2}\approx I_S·e^{\frac{V_E-V_P}{V_T}}$

for I_C1, I_C2>>I_S. Additionally,

$I_{C1}+I_{C2}=I_{\mathrm{PTAT}}\mathrm{and}{I}_{C1}-I_{C2}=I_{\mathrm{Re}},$ $I_{C1}=\frac{I_{\mathrm{PTAT}}}{1+e^{\frac{V_E-V_N}{V_T}}}\mathrm{and}{I}_{C2}=\frac{I_{\mathrm{PTAT}}}{1+e^{\frac{V_P-V_E}{V_T}}}.$

Furthermore,

$I_{\mathrm{Re}}=I_{\mathrm{PTAT}}·\frac{e^{\frac{V_P-V_E}{V_T}}-1}{e^{\frac{V_P-V_N}{V_T}}+1}=I_{\mathrm{PTAT}}·\tanh \left(\frac{V_P-V_N}{2·V_T}\right),\mathrm{and}$ $\frac{d}{\mathrm{dx}}\tanh \left(x\right)=1/{\cosh }^2\left(x\right)\mathrm{for}x=0,1/{\cosh }^2\left(x\right)=1.$ $\mathrm{For}❘V_P-V_N❘<V_T:I_{\mathrm{Re}}\approx \frac{V_P-V_N}{2·V_T}.$

FIG. 6 is a graph of one example of an emitter resistance compensation simulation. The simulation simulates one implementation of emitter resistance compensation for different temperature values. Simulations with and without emitter resistance compensation are enabled are shown.

FIG. 7 is a graph of one example of dVBE voltage change versus differential voltage V_P−V_N. The graph uses a PTAT tail current for the differential pair T10 and T11 in FIG. 3 with value

$I_{\mathrm{PTAT}}=\frac{k·T}{q·4·R_1}\mathrm{LN}\left(8\right)$

and K₁ around OA1 in FIG. 2. For small input voltages for the T10 & T11 differential pair up to 20 mV, the dVBE output voltage change is independent with temperature. The gain is chosen 0.25 because the current density of NPN3 is 4× the current density in NPN_LOG 1. An accurate compensation can be achieved up to 5 mV dVBE. With an emitter resistance RE1 of for example 1Ω, about up to 5 mA can be compensated accurately.

FIG. 8 is a graph of one example of logarithmic conformance error versus input current. The dashed line is with Re compensation off. The graph uses a tail current for the differential pair T10 and T11 in FIG. 3 with value closer to constant vs temperature (ZTAT) than PTAT.

As shown in FIG. 8, the difference between Re Compensation On and Off is larger at cold temperature. Additionally, Re Compensation is not cause of downward slope at −40° C.

CONCLUSION

The foregoing description may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and/or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.

Although the claims presented here are in single dependency format for filing at the USPTO, it is to be understood that any claim may depend on any preceding claim of the same type except when that is clearly not technically feasible.

Claims

1. A logarithmic current to voltage converter comprising: an input terminal configured to receive an input current;a logarithmic bipolar transistor having a collector connected to the input terminal and an emitter configured to generate a logarithmic output voltage; andan emitter resistance compensation circuit comprising a replica of the logarithmic bipolar transistor, wherein the emitter resistance compensation circuit is configured to receive a copy of the input current and to generate a compensation signal operable to adjust the logarithmic voltage to correct for an error arising from an emitter resistance of the logarithmic bipolar transistor.

2. The logarithmic current to voltage converter of claim 1, wherein the compensation signal is proportional to the emitter resistance.

3. The logarithmic current to voltage converter of claim 1, wherein the emitter resistance compensation circuit comprises a pair of bipolar transistors configured to sense a difference voltage that changes based on the emitter resistance of the logarithmic bipolar transistor times a scaled copy of the input current.

4. The logarithmic current to voltage converter of claim 3, wherein the difference voltage is sensed between a pair of scaled replica transistors with a current density ratio of at least four to one.

5. The logarithmic current to voltage converter of claim 4, wherein the difference voltage is corrected by a voltage that is proportional to a natural logarithm of the current density ratio times a thermal voltage.

6. The logarithmic current to voltage converter of claim 3, wherein the pair of bipolar transistors is biased by a current that is proportional to absolute temperature (PTAT).

7. The logarithmic current to voltage converter of claim 1, wherein the copy of the input current is scaled down in size relative to the input current.

8. The logarithmic current to voltage converter of claim 1, wherein the replica of the logarithmic bipolar transistor is scaled down in size relative to the logarithmic bipolar transistor.

9. The logarithmic current to voltage converter of claim 1, further comprising a logarithmic bipolar transistor having a collector configured to receive a reference current, wherein the logarithmic output voltage is taken differentially between the emitter of logarithmic bipolar transistor receiving the input current and an emitter of the logarithmic bipolar transistor receiving the reference current.

10. The logarithmic current to voltage converter of claim 9, further comprising an output amplifier configured to receive the logarithmic output voltage between a first input and a second input.

11. The logarithmic current to voltage converter of claim 9, wherein the compensation signal is a compensation current provided to the first input of the output amplifier.

12. The logarithmic current to voltage converter of claim 1, further comprising a bipolar transistor having a collector connected to the emitter of the logarithmic bipolar transistor.

13. The logarithmic current to voltage converter of claim 12, further comprising a resistor connected between an emitter of the bipolar transistor and a ground voltage.

14. The logarithmic current to voltage converter of claim 12, further comprising a field-effect transistor having a gate connected to the collector of the logarithmic bipolar transistor and a source connected to a base of the bipolar transistor.

15. The logarithmic current to voltage converter of claim 1, further comprising an input current source that generates the input current.

16. A photocurrent detection system comprising: a photodetector configured to generate an input current; anda semiconductor die comprising a logarithmic converter, wherein the logarithmic converter comprises: an input terminal configured to receive the input current;a logarithmic bipolar transistor having a collector connected to the input terminal and an emitter configured to generate a logarithmic output voltage; andan emitter resistance compensation circuit comprising a scaled replica of the logarithmic bipolar transistor, wherein the emitter resistance compensation circuit is configured to receive a scaled copy of the input current and to generate a compensation signal operable to adjust the logarithmic voltage to correct for an error arising from an emitter resistance of the logarithmic bipolar transistor.

17. The photocurrent detection system of claim 16, wherein the compensation signal is proportional to the emitter resistance.

18. The photocurrent detection system of claim 16, wherein the emitter resistance compensation circuit comprises a pair of bipolar transistors configured to sense a difference voltage that changes based on the emitter resistance of the logarithmic bipolar transistor times a scaled copy of the input current.

19. A method of logarithmic current to voltage conversion, the method comprising: providing an input current from an input terminal to a collector of a bipolar transistor;providing a logarithmic output voltage from an emitter of the logarithmic bipolar transistor; andgenerating a compensation signal using an emitter resistance compensation circuit that comprises a scaled replica of the logarithmic bipolar transistor, including receiving a scaled copy of the input current as an input to the emitter resistance compensation circuit, and adjusting the logarithmic voltage to correct for an error arising from an emitter resistance of the logarithmic bipolar transistor using the compensation signal.

20. The method of claim 19, wherein the compensation signal is proportional to the emitter resistance.