Claims
- 1. A method for forming a logic circuit by using a computer, comprising the steps of:inputting a first data of a first logic circuit which is described by a first set of CMOS cells and connecting relationships of the first set of CMOS cells; generating a second data which describes a first logic function of the first logic circuit by a first set of selectors and connecting relationships of said first set of selectors; replacing a part of the first set of selectors and connecting relationships relating to the part of the first set of selectors into a second set of selectors and connecting relationships relating to the second set of selectors, so that a third data is generated; wherein the third data is able to use to generate second data of a second logic circuit which is described by a second set of CMOS cells and connecting relationships of the second set of CMOS cells.
- 2. A method of forming a logic circuit according to claim 1,wherein at least a delay time of a first path from a first input terminal of one of the first set of selectors and a first output terminal of another of the first set of selectors is longer than a delay time of second path corresponding to the first path from a second input terminal of one of the second set of selectors and a second output terminal of another of the second set of selectors, wherein the second input terminal is corresponding to the first input terminal and the second out put terminal is corresponding to the first output terminal.
- 3. A method of forming a logic circuit according to claim 2,wherein the first path has the longest delay time from any of input terminals of one of the first set of selectors and any of output terminal of another of the first set of selectors.
- 4. A method of forming a logic circuit according to claim 1,wherein each of the first and second set of selectors has two input terminals and one output terminal.
- 5. A method of forming a logic circuit according to claim 1,wherein the first set of selectors has at least two selectors.
Priority Claims (1)
Number |
Date |
Country |
Kind |
9-327536 |
Nov 1997 |
JP |
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Parent Case Info
This is a continuation application of U.S. Ser. No. 09/906,264, filed Jul. 17, 2001, which is a continuation application of U.S. Ser. No. 09/610,697, filed Jul. 5, 2000, now U.S. Pat. No. 6,323,690, which is a continuation application of U.S. Ser. No. 09/197,465, filed Nov. 23, 1998, now U.S. Pat. No. 6,124,736.
US Referenced Citations (12)
Non-Patent Literature Citations (3)
Entry |
IEEE 1994 Custom Integrated Circuits Conference, pp. 603-606. |
IEEE Journal of Solid-State Circuits. vol. 25, No. 2, pp. 388-395. |
IEEE 1993 International Solid-State Circuits Conference, Digest of Technical Papers, pp. 90-91. |
Continuations (3)
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Number |
Date |
Country |
Parent |
09/906264 |
Jul 2001 |
US |
Child |
10/122385 |
|
US |
Parent |
09/610697 |
Jul 2000 |
US |
Child |
09/906264 |
|
US |
Parent |
09/197465 |
Nov 1998 |
US |
Child |
09/610697 |
|
US |