Claims
- 1. A semiconductor integrated circuit device comprising:a pass transistor circuit including first and second field-effect transistors, said first field-effect transistor having a source-drain path connected between a first node and a second node, and said second field-effect transistor having a source-drain path connected between a third node and said second node; and a multi-input CMOS logic circuit having first and second input nodes, first and second p-channel transistors and first and second n-channel transistors for producing a control signal, said first p-channel transistor being connected to said first n-channel transistor serially, said second p-channel transistor being connected to said second n-channel transistor serially, said first input node being connected to gates of said first p-channel transistor and said first n-channel transistor and second input node being connected to gates of said second p-channel transistor and said second n-channel transistor; wherein said control signal is applied to a gate of said first field-effect transistor and an inverted version of said control signal is applied to a gate of said second field-effect transistor.
- 2. A semiconductor integrated circuit device according to claim 1, wherein said inverted version of said control signal is generated by an inverter circuit.
- 3. A semiconductor integrated circuit device according to claim 1, further comprising a pass transistor cell including said pass transistor circuit and a CMOS cell including said multi-input CMOS logic circuit, said pass transistor cell and said CMOS cell being arranged along a power supply line, said pass transistor cell having a width as viewed in a direction perpendicular to said power supply line equal to a width of said CMOS cell as viewed in the direction perpendicular to said power supply line.
- 4. A semiconductor integrated circuit device comprising:a pass transistor circuit including first and second field-effect transistors, said first field-effect transistor having a source-drain path connected between a first node and a second node, and said second field-effect transistor having a source-drain path connected between a third node and said second node; and a multi-input CMOS logic circuit having first and second input nodes, first and second p-channel transistors and first and second n-channel transistors ,said first p-channel transistor being connected to said first n-channel transistor serially, said second p-channel transistor being connected to said second n-channel transistor serially, and first input node being connected to gates of said first p-channel transistor and said first n-channel transistor and said second input node being connected to gates of said second p-channel transistor and said second n-channel transistor; wherein an output of said multi-input CMOS logic circuit is applied to said first node, a control signal is applied to a gate of said first field-effect transistor, and an inverted version of said control signal is applied to a gate of said second field-effect transistor.
- 5. A semiconductor integrated circuit device according to claim 4, wherein said inverted version of said control signal is generated by an inverter circuit.
- 6. A semiconductor integrated circuit device according to claim 4, further comprising a pass transistor cell including said pass transistor circuit and a CMOS cell including said multi-input CMOS logic circuit, said pass transistor cell having a width as viewed in a direction perpendicular to said power supply line equal to a width of said CMOS cell as viewed in the direction perpendicular to said power supply line.
- 7. A semiconductor integrated circuit device comprising:a pass transistor circuit including first and second field-effect transistors, said first field-effect transistor having a source-drain path connected between a first node and a second node, and said second field-effect transistor having a source-drain path connected between a third node and said second node; an inverter circuit having an input connected to said second node; and a multi-input CMOS logic circuit having first and second input nodes, first and second p-channel transistors and first and second n-channel transistors, said first p-channel transistor being connected to said first n-channel transistor serially, said second p-channel transistor being connected to said second n-channel transistor serially, said first input node being connected to gates of said first p-channel transistor and said first n-channel transistor and said second input node being connected to gates of said second p-channel transistor and said second n-channel transistor; wherein an output of said inverter circuit is applied to one of said first and second input nodes of said multi-input CMOS logic circuit, a control signal is applied to a gate of said first field-effect transistor, and an inverted version of said control signal is applied to a gate of said second field-effect transistor.
- 8. A semiconductor integrated circuit device according to claim 7, wherein said inverted version of said control signal is generated by said inverter circuit.
- 9. A semiconductor integrated circuit device according to claim 7, further comprising a pass transistor cell including said pass transistor circuit and a CMOS cell including said multi-input CMOS logic circuit, said pass transistor cell and said CMOS cell being arranged along a power supply line, said pass transistor cell having a width as viewed in a direction perpendicular to said power supply line equal to a width of said CMOS cell as viewed in the direction perpendicular to said power supply line.
Priority Claims (1)
Number |
Date |
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Kind |
9-000548 |
Jan 1997 |
JP |
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CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. application Ser. No. 09/331,780, filed on Jun. 24, 1999, now U.S. Pat. No. 6,313,666, which is a continuation-in-part of international patent application No. PCT/JP96/1104, filed Apr. 24, 1996, the disclosure of which is incorporated in its entirety herein by reference. The international patent application No. PCT/JP96/1104 is, in turn, which is a continuation-in-part of earlier U.S. Ser. No. 08/633,053, filed Apr. 16, 1996, now U.S. Pat. No. 5,923,189, the disclosure of which is incorporated in its entirety herein by reference and earlier U.S. Ser. No. 08/633,486, filed Apr. 17, 1996.
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Continuations (1)
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Number |
Date |
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Parent |
09/331780 |
Jun 1999 |
US |
Child |
09/940597 |
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US |
Continuation in Parts (2)
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Number |
Date |
Country |
Parent |
PCT/JP96/01104 |
Apr 1996 |
US |
Child |
09/331780 |
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US |
Parent |
08/633053 |
Apr 1996 |
US |
Child |
PCT/JP96/01104 |
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US |