Logical super block mapping for NAND flash memory

Abstract

Increased capacity of a NAND flash memory may be achieved by increasing the availability of non-defective physical blocks by allowing logical super blocks to have physical blocks with different associated position numbers within the physical blocks' respective planes. A flash memory module has one or more flash memory integrated circuits (ICs), each having multiple physical blocks. The physical blocks are grouped into planes characterized in that only physical blocks from different planes can be erased simultaneously. Embodiments of the invention include a method of managing the physical blocks of the flash memory, a flash memory system for managing data transfer between a host and the flash memory ICs, and a machine readable storage medium containing instructions for a controller in the management of physical blocks of flash memory.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described below in the appended claims which are read in view of the accompanying description including the following drawings, wherein:

FIG. 1 illustrates a prior art memory management system;

FIG. 2 depicts a prior art flash memory module, which may be used in the system of FIG. 1;

FIG. 3 represents the prior art flash memory module of FIG. 2 with the physical block addresses indicated for each memory block;

FIG. 4 shows a prior art grouping of the physical blocks of FIG. 3 into super blocks;

FIG. 5 shows a prior art super block grouped from physical blocks of a single flash memory module having multiple planes;

FIGS. 6 a and 6b illustrate the effects of defective physical blocks on prior art super blocks;

FIG. 7 illustrates a flash memory system according to one an embodiment of the invention;

FIG. 8 presents a flow chart representing an algorithm according to one embodiment of the invention;

FIG. 9 presents a comparison of the results of using the memory management of the prior art and the memory management of the embodiment represented in FIG. 8; and

FIG. 10 presents a flow chart representing an algorithm according to an alternate embodiment of the invention.

DETAILED DESCRIPTION

The invention summarized above and defined by the claims below will be better understood by referring to the present detailed description of embodiments of the invention. This description is not intended to limit the scope of claims but instead to provide examples of the invention. Described first is a flash memory system that manages data transfer between a host and flash memory ICs. Included are descriptions of exemplary algorithms that instruct the controller in managing the data transfer. Also presented is a comparison of super block mapping of the prior art with super block mapping of the present invention.

Reference is now made to FIG. 7, which illustrates an exemplary embodiment of a flash memory system 20 that manages data transfer between a host and flash memory ICs. Flash memory system 20 has a flash memory module 24 and a controller 26. Flash memory module 20 may be part of a portable data storage assembly, for example, a USB flash drive. Controller 26 may also be part of the portable data assembly, or it may reside instead in the host. For example, controller 26 may be implemented by software executable by the host.

Flash memory module 24 has one or more flash memory ICs, and each flash memory IC has multiple physical blocks, which are identified by their physical block addresses 11, 12, 13, . . . , 45. Specifically, in this embodiment, physical blocks 11, 12, 13, . . . , 45 are grouped into planes 24₁, 24₂, 24₃, and 24₄. Two physical blocks from a common plane cannot be erased simultaneously, but two physical blocks from different planes can be erased simultaneously. Physical blocks 11, 12, 13, . . . , 45 have associated position numbers within their respective planes such that a position number indicates a block's physical location within its plane.

Controller 26 is operative to manage data transfer between flash memory module 24 and a host by defining logical super blocks as groups of multiple physical blocks, each logical super blocks having no more than one physical block from a common plane to allow all physical blocks within a super block to be erased simultaneously. Unlike the super blocks of the prior art, however, a logical super block of the present invention may have physical blocks with different associated position numbers within their respective planes, and designation of logical super blocks accordingly can enable greater usage of the non-defective physical blocks of a NAND flash memory.

Controller 26 accesses a machine readable storage medium containing instructions that, when executed, cause the controller to perform as described herein. One exemplary algorithm executable by controller 26 is represented by the flow chart 30 in FIG. 8. This algorithm will be explained with reference to flash memory module 24. The defective physical blocks therein are physical blocks 31, 22, 24, and 44, which FIG. 7 indicates by shading.

Controller 26 begins by obtaining the position numbers associated with all physical blocks 11, 12, 13, . . . , 45 and then defines initial groups of the physical blocks, each initial group having no more than one physical block from a common plane. [Step S1.] Applying this logic to flash memory module 24 yields the initial groups such as {11, 21, 31, 41}, {12, 22, 32, 42}, {13, 23, 33, 43}, {14, 24, 34, 44}, and {15, 25, 35, 45}.

Next, controller 26 determines whether any initial groups have no defective blocks. [Step S2.] For each initial group having no defective physical blocks, controller 26 designates the physical blocks as a logical super block. [Step S3.] Applying this logic to the initial groups flash memory module 24 yields logical super groups such as {13, 23, 33, 43} and {15, 25, 35, 45}.

Then, controller 26 determines if there are initial groups that have defective physical blocks. [Step S4.] When no such initial groups remain, the algorithm ends.

For the example application of this algorithm to flash memory module 24, controller 26 determines that the following three such initial groups remain: {11, 21, 31, 41}, {12, 22, 32, 42}, and {14, 24, 34, 44}. The defective physical blocks are noted in underscore.

For such applications in which initial groups are found that have defective physical blocks, controller 26 selects one of such initial groups and then selects a defective physical block from that group. [Step S5.] For the present example, controller 26 might select initial group {11, 21, 31, 41} and then physical block 31.

Next, controller 26 determines whether the plane of the selected physical block includes a non-defective physical block that is not yet designated as part of a logical super block. [Step S6.] For the present example, controller 26 can identify either physical block 32 or physical block 34 as available. If no such physical blocks are available from the plane of the selected defective physical block, the algorithm ends.

For applications such as the present example, in which non-defective physical blocks are available, controller 26 redefines the selected initial group by replacing the selected defective physical block with an available non-defective physical block. [Step S7.] For the present example, controller 26 may redefine the selected initial group by replacing defective physical block 31 with non-defective physical block 32.

Then, controller 26 determines whether the selected initial group has another defective physical block. [Step S8.] When the selected initial group does not have another defective physical block, controller 26 designates the physical blocks of the redefined initial group as a logical super block. [Step S9.] For the present example of flash memory module 24, controller 26 may designate physical blocks 11, 21, 32, and 41 as a logical super block. For applications in which the selected initial group does have another defective physical block, the process flow continues to Step S6 to determine whether another non-defective physical block is available for use in a logical super block.

After Step S9, when a logical super block is designated, controller 26 determines whether another initial group having at least one defective physical block exists. [Step S110.] If no such initial group exists, as in the case of the example flash memory module 24, the process flow ends. If at least one such initial group exists, the process flow continues to Step S6 and controller 26 repeats the above-described logic to determine whether another logical super block can be designated. When the algorithm ends, the logical super blocks are determined, and multiple physical blocks corresponding to a common logical super block may be erased substantially simultaneously.

The present invention enables greater usage of the non-defective physical blocks of a NAND flash memory. In the prior art described above, only forty percent of flash memory module 14c is available for use in super blocks. (See, in particular, FIG. 6b.) However, in the embodiment described immediately above, the controller 26 would designate sixty percent of the same flash memory module as available for use in logical super blocks. This increase in available memory is shown graphically in FIG. 9 with dashed lines indicating super blocks.

As is evident from FIG. 9, the available memory can be increased by allowing logical super blocks to have physical blocks with different associated position numbers within their respective planes. For the embodiment of the invention discussed above, the third logical super block has three physical blocks having associated position numbers 1 (physical blocks 11, 21, and 41) and one physical block having position number 2 (physical blocks 32).

To the best knowledge of the inventors, the only situations in which the present embodiment would not increase the capacity of a NAND flash memory would be: (1) when every initial group of physical blocks having defective blocks has a deflective block in the same plane; and (2) when the initial groups of physical blocks have no deflective physical blocks at all. Both scenarios are regarded as rare. Only in those situations would all logical super blocks of a memory each have all physical blocks with the same associated position numbers. Nonetheless, if the disclosed embodiment were applied to such a situation, the same amount of memory would be available for use, instead of less memory being available for use. That is, implementation of the present embodiment is not anticipated to have the risk of providing less memory for use than what would be provided using the prior art discussed above.

FIG. 10 illustrates an alternative embodiment of the invention in which flow chart 32 represents another algorithm executable by a controller to increase usage of NAND flash memory beyond the usage of prior art algorithms. The controller begins by determining whether each plane of the flash memory includes at least one non-defective physical block that is not yet designated as part of a logical super block. [Step S1.] The determination is negative if one or more planes do not have an available non-defective super block, and the algorithm ends.

If the determination of Step S1 is positive, that is, if each plane of the flash memory includes at least one available block, the controller selects one of such available blocks from each plane. [Step S2.] Then, the selected blocks are designated as a new logical super block. [Step S3.]

Next, the process flow continues to Step S1, and the controller determines again whether each plane of the flash memory module includes at least one non-defective physical block that is not yet designated as part of a logical super block. This process repeats until at least one plane does not include a non-defective physical block that is not yet designated to a logical super block. When the algorithm ends, the logical super blocks are determined, and multiple physical blocks corresponding to a common logical super block may be erased substantially simultaneously.

As with the embodiment represented in FIG. 8, the present embodiment enables greater usage of the non-deflective physical blocks of a NAND flash memory. By allowing logical super blocks to have physical blocks with different associated position numbers, the available memory can be increased.

Having thus described exemplary embodiments of the invention, it will be apparent that various alterations, modifications, and improvements will readily occur to those skilled in the art. Alternations, modifications, and improvements of the disclosed invention, though not expressly described above, are nonetheless intended and implied to be within spirit and scope of the invention. Accordingly, the foregoing discussion is intended to be illustrative only; the invention is limited and defined only by the following claims and equivalents thereto.

Claims

1. A method of managing physical blocks of flash memory, the method comprising: providing one or more flash memory ICs such that each flash memory IC has multiple physical blocks, said physical blocks being grouped into planes wherein two physical blocks from a common plane cannot be erased simultaneously, and wherein two physical blocks from different planes can be erased simultaneously, said physical blocks having associated position numbers within said planes such that a position number indicates a block's physical location within its plane; anddefining logical super blocks as groups of multiple physical blocks, each of said logical super blocks having no more than one physical block from a common plane to allow all physical blocks within a super block to be erased simultaneously,wherein at least one of said logical super blocks has at least two physical blocks with different associated position numbers within their respective planes.

2. The method of claim 1, wherein said logical super blocks are defined by implementing the following process: defining initial groups of physical blocks, each of said initial groups having no more than one physical block from a common plane;for each initial group having no defective physical blocks, designating said physical blocks of such initial group as a logical super block; andfor each initial group having at least one defective physical block: for each defective physical block in said initial group, when the plane of said defective physical block includes a non-defective physical block that is not yet designated as part of a logical super block, redefining said initial group of physical blocks by replacing said defective physical block with said non-defective and not-yet-designated physical block; andafter said replacing occurs for each defective block in said initial group, designating the physical blocks of said redefined group as a logical super block.

3. The method of claim 1, wherein said logical super blocks are defined by implementing the following process: when each plane includes at least one non-defective physical block that is not yet designated as part of a logical super block, designating one of said not-yet-designated non-defective physical blocks from each plane as a new logical super block; andrepeating said designating until at least one plane does not include a non-defective physical block that is not yet designated to a logical super block.

4. The method of claim 1, further comprising: erasing, substantially simultaneously, multiple physical blocks corresponding to a common logical super block.

5. A flash memory system for managing data transfer between a host and flash memory ICs, the flash memory system comprising: a flash memory module, having one or more flash memory ICs with each flash memory IC having multiple physical blocks, said physical blocks grouped into planes such that two physical blocks from a common plane cannot be erased simultaneously and that two physical blocks from different planes can be erased simultaneously, said physical blocks having associated position numbers within said planes such that a position number indicates a block's physical location within its plane;a controller operative to manage data transfer between said flash memory module and the host by defining logical super blocks as groups of multiple physical blocks, each of said logical super blocks having no more than one physical block from a common plane to allow all physical blocks within a super block to be erased simultaneously,wherein at least one of said logical super blocks has at least two physical blocks with different associated position numbers within their respective planes.

6. The flash memory system of claim 5, wherein said controller is further operative to erase, substantially simultaneously, multiple physical blocks corresponding to a common logical super block.

7. The flash memory system of claim 5, wherein said flash memory module and said controller are part of a portable data storage assembly.

8. The flash memory system of claim 7, wherein said portable data storage assembly is a USB flash drive.

9. The flash memory system of claim 5, wherein said flash memory module is part of a portable data storage assembly and said controller resides in the host.

10. The flash memory system of claim 9, wherein said controller is implemented by software executable by the host

11. The flash memory system of claim 9, wherein said portable data storage assembly is a USB flash drive.

12. The flash memory system of claim 5, wherein said controller is operative to define said logical super blocks by implementing the following process: defining initial groups of physical blocks, each of said initial groups having no more than one physical block from a common plane;for each initial group having no defective physical blocks, designating said physical blocks of such initial group as a logical super block; andfor each initial group having at least one defective physical block: for each defective physical block in said initial group, when the plane of said defective physical block includes a non-defective physical block that is not yet designated as part of a logical super block, redefining said initial group of physical blocks by replacing said defective physical block with said non-defective and not-yet-designated physical block; andafter said replacing occurs for each defective block in said initial group, designating the physical blocks of said redefined group as a logical super block.

13. The flash memory system of claim 5, wherein said controller is operative to define said logical super blocks by implementing the following process: when each plane includes at least one non-defective physical block that is not yet designated as part of a logical super block, designating one of said not-yet-designated non-defective physical blocks from each plane as a new logical super block; andrepeating said designating until at least one plane does not include a non-defective physical block that is not yet designated to a logical super block.

14. A machine readable storage medium containing instructions for a controller to organize physical blocks of flash memory, said flash memory having one or more flash memory ICs with each flash memory IC having multiple physical blocks, said physical blocks grouped into planes such that two physical blocks from a common plane cannot be erased simultaneously and that two physical blocks from different planes can be erased simultaneously, said physical blocks having associated position numbers within said planes such that a position number indicates a block's physical location within its plane, wherein when executed said instructions cause said controller to perform the following: define logical super blocks as groups of multiple physical blocks, each of said logical super blocks having no more than one physical block from a common plane to allow all physical blocks within a super block to be erased simultaneously, at least one of said logical super blocks having at least two physical blocks with different associated position numbers within their respective planes; anderase, substantially simultaneously, multiple physical blocks corresponding to a common logical super block.

15. The machine readable storage medium of chain 14, wherein said instructions for defining said logical super blocks include the following: defining initial groups of physical blocks, each of said initial groups having no more than one physical block from a common plane;for each initial group having no defective physical blocks, designating said physical blocks of such initial group as a logical super block; andfor each initial group having at least one defective physical block: for each defective physical block in said initial group, when the plane of said defective physical block includes a non-defective physical block that is not yet designated as part of a logical super block, redefining said initial group of physical blocks by replacing said defective physical block with said non-defective and not-yet-designated physical block; andif said replacing occurs for each defective block in said initial group, designating the physical blocks of said redefined group as a logical super block.

16. The machine readable storage medium of claim 14, wherein said instructions for defining said logical super blocks include the following: when each plane includes at least one non-defective physical block that is not yet designated as part of a logical super block, designating one of said net-yet-designated non-defective physical blocks from each plane as a new logical super block; andrepeating said designating until at least one plane does not include a non-defective physical block that is not yet designated to a logical super block.