LONG SHORT-TERM MEMORY USING A SPIKING NEURAL NETWORK

Abstract

A method for configuring long short-term memory (LSTM) in a spiking neural network includes decoding input spikes into analog values within the LSTM. The method further includes implementing the LSTM based on an encoded representation of the analog values. The implementing can include encoding the analog values using base expansive coding, rate coding, latency coding or synaptic weight coding.

Description

BACKGROUND

1. Field

Certain aspects of the present disclosure generally relate to neural system engineering and, more particularly, to systems and methods for providing long short-term memory.

2. Background

An artificial neural network, which may comprise an interconnected group of artificial neurons (i.e., neuron models), is a computational device or represents a method to be performed by a computational device. Artificial neural networks may have corresponding structure and/or function in biological neural networks. However, artificial neural networks may provide innovative and useful computational techniques for certain applications in which traditional computational techniques are cumbersome, impractical, or inadequate. Because artificial neural networks can infer a function from observations, such networks are particularly useful in applications where the complexity of the task or data makes the design of the function by conventional techniques burdensome.

SUMMARY

In an aspect of the present disclosure, a method for configuring long short-term memory (LSTM) in a spiking neural network is presented. The method includes decoding input spikes into analog values within the LSTM. The method further includes implementing the LSTM based on an encoded representation of the analog values.

In another aspect of the present disclosure, an apparatus for configuring long short-term memory (LSTM) in a spiking neural network is presented. The apparatus includes a memory and one or more processors coupled to the memory. The processor(s) is(are) configured to decode input spikes into analog values within the LSTM. The processor(s) is(are) further configured to implement the LSTM based on an encoded representation of the analog values.

In yet another aspect of the present disclosure, an apparatus for configuring long short-term memory (LSTM) in a spiking neural network is presented. The apparatus includes means for decoding input spikes into analog values within the LSTM. The apparatus further includes means for implementing the LSTM based on an encoded representation of the analog values.

In still another aspect of the present disclosure, a computer program product for configuring long short-term memory (LSTM) in a spiking neural network is presented. The computer program product includes a non-transitory computer readable medium having encoded thereon program code. The program code includes program code to decode input spikes into analog values within the LSTM. The program code further includes program code to implement the LSTM based on an encoded representation of the analog values.

This has outlined, rather broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, nature, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.

FIG. 1 illustrates an example network of neurons in accordance with certain aspects of the present disclosure.

FIG. 2 illustrates an example of a processing unit (neuron) of a computational network (neural system or neural network) in accordance with certain aspects of the present disclosure.

FIG. 3 illustrates an example of spike-timing dependent plasticity (STDP) curve in accordance with certain aspects of the present disclosure.

FIG. 4 illustrates an example of a positive regime and a negative regime for defining behavior of a neuron model in accordance with certain aspects of the present disclosure.

FIG. 5 illustrates an example implementation of designing a neural network using a general-purpose processor in accordance with certain aspects of the present disclosure.

FIG. 6 illustrates an example implementation of designing a neural network where a memory may be interfaced with individual distributed processing units in accordance with certain aspects of the present disclosure.

FIG. 7 illustrates an example implementation of designing a neural network based on distributed memories and distributed processing units in accordance with certain aspects of the present disclosure.

FIG. 8 illustrates an example implementation of a neural network in accordance with certain aspects of the present disclosure.

FIG. 9 illustrates a multi-layer network in accordance with an aspect of the present disclosure.

FIG. 10 illustrates differences between binary expansive coding and logarithmic temporal coding in accordance with an aspect of the present disclosure.

FIGS. 11 and 12 illustrate a network and corresponding spike timing dependent plasticity (STDP) curve in accordance with an aspect of the present disclosure.

FIGS. 13 and 14 illustrate a network and corresponding spike timing dependent plasticity (STDP) curve in accordance with another aspect of the present disclosure.

FIG. 15 illustrates a network having an orchestrator neuron in accordance with an aspect of the present disclosure.

FIGS. 16 and 17 are block diagrams illustrating exemplary long short-term memories in accordance with aspects of the present disclosure.

FIG. 18 is a flow diagram illustrating a method for configuring long short-term memory in a spiking neural network in accordance with an aspect of the present disclosure.

DETAILED DESCRIPTION

The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

Based on the teachings, one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth. In addition, the scope of the disclosure is intended to cover such an apparatus or method practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth. It should be understood that any aspect of the disclosure disclosed may be embodied by one or more elements of a claim.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

Although particular aspects are described herein, many variations and permutations of these aspects fall within the scope of the disclosure. Although some benefits and advantages of the preferred aspects are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different technologies, system configurations, networks and protocols, some of which are illustrated by way of example in the figures and in the following description of the preferred aspects. The detailed description and drawings are merely illustrative of the disclosure rather than limiting, the scope of the disclosure being defined by the appended claims and equivalents thereof.

An Example Neural System, Training and Operation

FIG. 1 illustrates an example artificial neural system 100 with multiple levels of neurons in accordance with certain aspects of the present disclosure. The neural system 100 may have a level of neurons 102 connected to another level of neurons 106 through a network of synaptic connections 104 (i.e., feed-forward connections). For simplicity, only two levels of neurons are illustrated in FIG. 1, although fewer or more levels of neurons may exist in a neural system. It should be noted that some of the neurons may connect to other neurons of the same layer through lateral connections. Furthermore, some of the neurons may connect back to a neuron of a previous layer through feedback connections.

As illustrated in FIG. 1, each neuron in the level 102 may receive an input signal 108 that may be generated by neurons of a previous level (not shown in FIG. 1). The signal 108 may represent an input current of the level 102 neuron. This current may be accumulated on the neuron membrane to charge a membrane potential. When the membrane potential reaches its threshold value, the neuron may fire and generate an output spike to be transferred to the next level of neurons (e.g., the level 106). In some modeling approaches, the neuron may continuously transfer a signal to the next level of neurons. This signal is typically a function of the membrane potential. Such behavior can be emulated or simulated in hardware and/or software, including analog and digital implementations such as those described below.

In biological neurons, the output spike generated when a neuron fires is referred to as an action potential. This electrical signal is a relatively rapid, transient, nerve impulse, having an amplitude of roughly 100 mV and a duration of about 1 ms. In a particular embodiment of a neural system having a series of connected neurons (e.g., the transfer of spikes from one level of neurons to another in FIG. 1), every action potential has basically the same amplitude and duration, and thus, the information in the signal may be represented only by the frequency and number of spikes, or the time of spikes, rather than by the amplitude. The information carried by an action potential may be determined by the spike, the neuron that spiked, and the time of the spike relative to other spike or spikes. The importance of the spike may be determined by a weight applied to a connection between neurons, as explained below.

The transfer of spikes from one level of neurons to another may be achieved through the network of synaptic connections (or simply “synapses”) 104, as illustrated in FIG. 1. Relative to the synapses 104, neurons of level 102 may be considered presynaptic neurons and neurons of level 106 may be considered postsynaptic neurons. The synapses 104 may receive output signals (i.e., spikes) from the level 102 neurons and scale those signals according to adjustable synaptic weights w₁^(i,i+1), . . . , w_P^(i,i+1) where P is a total number of synaptic connections between the neurons of levels 102 and 106 and i is an indicator of the neuron level. In the example of FIG. 1, i represents neuron level 102 and i+1 represents neuron level 106. Further, the scaled signals may be combined as an input signal of each neuron in the level 106. Every neuron in the level 106 may generate output spikes 110 based on the corresponding combined input signal. The output spikes 110 may be transferred to another level of neurons using another network of synaptic connections (not shown in FIG. 1).

Biological synapses can mediate either excitatory or inhibitory (hyperpolarizing) actions in postsynaptic neurons and can also serve to amplify neuronal signals. Excitatory signals depolarize the membrane potential (i.e., increase the membrane potential with respect to the resting potential). If enough excitatory signals are received within a certain time period to depolarize the membrane potential above a threshold, an action potential occurs in the postsynaptic neuron. In contrast, inhibitory signals generally hyperpolarize (i.e., lower) the membrane potential. Inhibitory signals, if strong enough, can counteract the sum of excitatory signals and prevent the membrane potential from reaching a threshold. In addition to counteracting synaptic excitation, synaptic inhibition can exert powerful control over spontaneously active neurons. A spontaneously active neuron refers to a neuron that spikes without further input, for example due to its dynamics or a feedback. By suppressing the spontaneous generation of action potentials in these neurons, synaptic inhibition can shape the pattern of firing in a neuron, which is generally referred to as sculpturing. The various synapses 104 may act as any combination of excitatory or inhibitory synapses, depending on the behavior desired.

The neural system 100 may be emulated by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, a software module executed by a processor, or any combination thereof. The neural system 100 may be utilized in a large range of applications, such as image and pattern recognition, machine learning, motor control, and alike. Each neuron in the neural system 100 may be implemented as a neuron circuit. The neuron membrane charged to the threshold value initiating the output spike may be implemented, for example, as a capacitor that integrates an electrical current flowing through it.

In an aspect, the capacitor may be eliminated as the electrical current integrating device of the neuron circuit, and a smaller memristor element may be used in its place. This approach may be applied in neuron circuits, as well as in various other applications where bulky capacitors are utilized as electrical current integrators. In addition, each of the synapses 104 may be implemented based on a memristor element, where synaptic weight changes may relate to changes of the memristor resistance. With nanometer feature-sized memristors, the area of a neuron circuit and synapses may be substantially reduced, which may make implementation of a large-scale neural system hardware implementation more practical.

Functionality of a neural processor that emulates the neural system 100 may depend on weights of synaptic connections, which may control strengths of connections between neurons. The synaptic weights may be stored in a non-volatile memory in order to preserve functionality of the processor after being powered down. In an aspect, the synaptic weight memory may be implemented on a separate external chip from the main neural processor chip. The synaptic weight memory may be packaged separately from the neural processor chip as a replaceable memory card. This may provide diverse functionalities to the neural processor, where a particular functionality may be based on synaptic weights stored in a memory card currently attached to the neural processor.

FIG. 2 illustrates an exemplary diagram 200 of a processing unit (e.g., a neuron or neuron circuit) 202 of a computational network (e.g., a neural system or a neural network) in accordance with certain aspects of the present disclosure. For example, the neuron 202 may correspond to any of the neurons of levels 102 and 106 from FIG. 1. The neuron 202 may receive multiple input signals 204₁-204_N, which may be signals external to the neural system, or signals generated by other neurons of the same neural system, or both. The input signal may be a current, a conductance, a voltage, a real-valued, and/or a complex-valued. The input signal may comprise a numerical value with a fixed-point or a floating-point representation. These input signals may be delivered to the neuron 202 through synaptic connections that scale the signals according to adjustable synaptic weights 206₁-206_N (W₁-W_N), where N may be a total number of input connections of the neuron 202.

The neuron 202 may combine the scaled input signals and use the combined scaled inputs to generate an output signal 208 (i.e., a signal Y). The output signal 208 may be a current, a conductance, a voltage, a real-valued and/or a complex-valued. The output signal may be a numerical value with a fixed-point or a floating-point representation. The output signal 208 may be then transferred as an input signal to other neurons of the same neural system, or as an input signal to the same neuron 202, or as an output of the neural system.

The processing unit (neuron) 202 may be emulated by an electrical circuit, and its input and output connections may be emulated by electrical connections with synaptic circuits. The processing unit 202 and its input and output connections may also be emulated by a software code. The processing unit 202 may also be emulated by an electric circuit, whereas its input and output connections may be emulated by a software code. In an aspect, the processing unit 202 in the computational network may be an analog electrical circuit. In another aspect, the processing unit 202 may be a digital electrical circuit. In yet another aspect, the processing unit 202 may be a mixed-signal electrical circuit with both analog and digital components. The computational network may include processing units in any of the aforementioned forms. The computational network (neural system or neural network) using such processing units may be utilized in a large range of applications, such as image and pattern recognition, machine learning, motor control, and the like.

During the course of training a neural network, synaptic weights (e.g., the weights w₁^(i,i+1), . . . , w_P^(i,i+1) from FIG. 1 and/or the weights 206₁-206_N from FIG. 2) may be initialized with random values and increased or decreased according to a learning rule. Those skilled in the art will appreciate that examples of the learning rule include, but are not limited to the spike-timing-dependent plasticity (STDP) learning rule, the Hebb rule, the Oja rule, the Bienenstock-Copper-Munro (BCM) rule, etc. In certain aspects, the weights may settle or converge to one of two values (i.e., a bimodal distribution of weights). This effect can be utilized to reduce the number of bits for each synaptic weight, increase the speed of reading and writing from/to a memory storing the synaptic weights, and to reduce power and/or processor consumption of the synaptic memory.

Synapse Type

In hardware and software models of neural networks, the processing of synapse related functions can be based on synaptic type. Synapse types may be non-plastic synapses (no changes of weight and delay), plastic synapses (weight may change), structural delay plastic synapses (weight and delay may change), fully plastic synapses (weight, delay and connectivity may change), and variations thereupon (e.g., delay may change, but no change in weight or connectivity). The advantage of multiple types is that processing can be subdivided. For example, non-plastic synapses may not use plasticity functions to be executed (or waiting for such functions to complete). Similarly, delay and weight plasticity may be subdivided into operations that may operate together or separately, in sequence or in parallel. Different types of synapses may have different lookup tables or formulas and parameters for each of the different plasticity types that apply. Thus, the methods would access the relevant tables, formulas, or parameters for the synapse's type.

There are further implications of the fact that spike-timing dependent structural plasticity may be executed independently of synaptic plasticity. Structural plasticity may be executed even if there is no change to weight magnitude (e.g., if the weight has reached a minimum or maximum value, or it is not changed due to some other reason)s structural plasticity (i.e., an amount of delay change) may be a direct function of pre-post spike time difference. Alternatively, structural plasticity may be set as a function of the weight change amount or based on conditions relating to bounds of the weights or weight changes. For example, a synapse delay may change only when a weight change occurs or if weights reach zero but not if they are at a maximum value. However, it may be advantageous to have independent functions so that these processes can be parallelized reducing the number and overlap of memory accesses.

Determination of Synaptic Plasticity

Neuroplasticity (or simply “plasticity”) is the capacity of neurons and neural networks in the brain to change their synaptic connections and behavior in response to new information, sensory stimulation, development, damage, or dysfunction. Plasticity is important to learning and memory in biology, as well as for computational neuroscience and neural networks. Various forms of plasticity have been studied, such as synaptic plasticity (e.g., according to the Hebbian theory), spike-timing-dependent plasticity (STDP), non-synaptic plasticity, activity-dependent plasticity, structural plasticity and homeostatic plasticity.

STDP is a learning process that adjusts the strength of synaptic connections between neurons. The connection strengths are adjusted based on the relative timing of a particular neuron's output and received input spikes (i.e., action potentials). Under the STDP process, long-term potentiation (LTP) may occur if an input spike to a certain neuron tends, on average, to occur immediately before that neuron's output spike. Then, that particular input is made somewhat stronger. On the other hand, long-term depression (LTD) may occur if an input spike tends, on average, to occur immediately after an output spike. Then, that particular input is made somewhat weaker, and hence the name “spike-timing-dependent plasticity.” Consequently, inputs that might be the cause of the postsynaptic neuron's excitation are made even more likely to contribute in the future, whereas inputs that are not the cause of the postsynaptic spike are made less likely to contribute in the future. The process continues until a subset of the initial set of connections remains, while the influence of all others is reduced to an insignificant level.

Because a neuron generally produces an output spike when many of its inputs occur within a brief period (i.e., being cumulative sufficient to cause the output), the subset of inputs that typically remains includes those that tended to be correlated in time. In addition, because the inputs that occur before the output spike are strengthened, the inputs that provide the earliest sufficiently cumulative indication of correlation will eventually become the final input to the neuron.

The STDP learning rule may effectively adapt a synaptic weight of a synapse connecting a presynaptic neuron to a postsynaptic neuron as a function of time difference between spike time t_pre of the presynaptic neuron and spike time t_post of the postsynaptic neuron (i.e., t=t_post−t_pre). A typical formulation of the STDP is to increase the synaptic weight (i.e., potentiate the synapse) if the time difference is positive (the presynaptic neuron fires before the postsynaptic neuron), and decrease the synaptic weight (i.e., depress the synapse) if the time difference is negative (the postsynaptic neuron fires before the presynaptic neuron).

In the STDP process, a change of the synaptic weight over time may be typically achieved using an exponential decay, as given by:

$\begin{array}{cc}\Delta w\left(t\right)=\{\begin{array}{c}{a}_{+}{}^{-t/k_{+}}+\mu ,t>0\\ a_{-}{}^{t/k_{-}},t<0\end{array},& \left(1\right)\end{array}$

where k₊ and k₋τ_sign(Δt)τ_sign(Δt) are time constants for positive and negative time difference, respectively, a₊ and a₋ are corresponding scaling magnitudes, and μ is an offset that may be applied to the positive time difference and/or the negative time difference.

FIG. 3 illustrates an exemplary diagram 300 of a synaptic weight change as a function of relative timing of presynaptic and postsynaptic spikes in accordance with the STDP. If a presynaptic neuron fires before a postsynaptic neuron, then a corresponding synaptic weight may be increased, as illustrated in a portion 302 of the graph 300. This weight increase can be referred to as an LTP of the synapse. It can be observed from the graph portion 302 that the amount of LTP may decrease roughly exponentially as a function of the difference between presynaptic and postsynaptic spike times. The reverse order of firing may reduce the synaptic weight, as illustrated in a portion 304 of the graph 300, causing an LTD of the synapse.

As illustrated in the graph 300 in FIG. 3, a negative offset μ may be applied to the LTP (causal) portion 302 of the STDP graph. A point of cross-over 306 of the x-axis (y=0) may be configured to coincide with the maximum time lag for considering correlation for causal inputs from layer i−1. In the case of a frame-based input (i.e., an input that is in the form of a frame of a particular duration comprising spikes or pulses), the offset value μ can be computed to reflect the frame boundary. A first input spike (pulse) in the frame may be considered to decay over time either as modeled by a postsynaptic potential directly or in terms of the effect on neural state. If a second input spike (pulse) in the frame is considered correlated or relevant to a particular time frame, then the relevant times before and after the frame may be separated at that time frame boundary and treated differently in plasticity terms by offsetting one or more parts of the STDP curve such that the value in the relevant times may be different (e.g., negative for greater than one frame and positive for less than one frame). For example, the negative offset μ may be set to offset LTP such that the curve actually goes below zero at a pre-post time greater than the frame time and it is thus part of LTD instead of LTP.

Neuron Models and Operation

There are some general principles for designing a useful spiking neuron model. A good neuron model may have rich potential behavior in terms of two computational regimes: coincidence detection and functional computation. Moreover, a good neuron model should have two elements to allow temporal coding: arrival time of inputs affects output time and coincidence detection can have a narrow time window. Finally, to be computationally attractive, a good neuron model may have a closed-form solution in continuous time and stable behavior including near attractors and saddle points. In other words, a useful neuron model is one that is practical and that can be used to model rich, realistic and biologically-consistent behaviors, as well as be used to both engineer and reverse engineer neural circuits.

A neuron model may depend on events, such as an input arrival, output spike or other event whether internal or external. To achieve a rich behavioral repertoire, a state machine that can exhibit complex behaviors may be desired. If the occurrence of an event itself, separate from the input contribution (if any), can influence the state machine and constrain dynamics subsequent to the event, then the future state of the system is not only a function of a state and input, but rather a function of a state, event, and input.

In an aspect, a neuron n may be modeled as a spiking leaky-integrate-and-fire neuron with a membrane voltage v_n(t) governed by the following dynamics:

$\begin{array}{cc}\frac{v_n\left(t\right)}{t}=\alpha v_n\left(t\right)+\beta \sum _mw_{m,n}y_m\left(t-\Delta t_{m,n}\right),& \left(2\right)\end{array}$

where α and β are parameters, w_m,nw_m,n is a synaptic weight for the synapse connecting a presynaptic neuron m to a postsynaptic neuron n, and y_m(t) is the spiking output of the neuron m that may be delayed by dendritic or axonal delay according to Δt_m,n until arrival at the neuron n's soma.

It should be noted that there is a delay from the time when sufficient input to a postsynaptic neuron is established until the time when the postsynaptic neuron actually fires. In a dynamic spiking neuron model, such as Izhikevich's simple model, a time delay may be incurred if there is a difference between a depolarization threshold v_t and a peak spike voltage v_peak. For example, in the simple model, neuron soma dynamics can be governed by the pair of differential equations for voltage and recovery, i.e.:

$\begin{array}{cc}\frac{v}{t}=\left(k\left(v-v_t\right)\left(v-v_r\right)-u+I\right)/C,& \left(3\right)\\ \frac{u}{t}=a\left(b\left(v-v_r\right)-u\right),& \left(4\right)\end{array}$

where v is a membrane potential, u is a membrane recovery variable, k is a parameter that describes time scale of the membrane potential v, a is a parameter that describes time scale of the recovery variable u, b is a parameter that describes sensitivity of the recovery variable u to the sub-threshold fluctuations of the membrane potential v, v_r is a membrane resting potential, I is a synaptic current, and C is a membrane's capacitance. In accordance with this model, the neuron is defined to spike when v>v_peak.

Hunzinger Cold Model

The Hunzinger Cold neuron model is a minimal dual-regime spiking linear dynamical model that can reproduce a rich variety of neural behaviors. The model's one- or two-dimensional linear dynamics can have two regimes, wherein the time constant (and coupling) can depend on the regime. In the sub-threshold regime, the time constant, negative by convention, represents leaky channel dynamics generally acting to return a cell to rest in a biologically-consistent linear fashion. The time constant in the supra-threshold regime, positive by convention, reflects anti-leaky channel dynamics generally driving a cell to spike while incurring latency in spike-generation.

As illustrated in FIG. 4, the dynamics of the model 400 may be divided into two (or more) regimes. These regimes may be called the negative regime 402 (also interchangeably referred to as the leaky-integrate-and-fire (LIF) regime, not to be confused with the LIF neuron model) and the positive regime 404 (also interchangeably referred to as the anti-leaky-integrate-and-fire (ALIF) regime, not to be confused with the ALIF neuron model). In the negative regime 402, the state tends toward rest (v₋) at the time of a future event. In this negative regime, the model generally exhibits temporal input detection properties and other sub-threshold behavior. In the positive regime 404, the state tends toward a spiking event (v_s). In this positive regime, the model exhibits computational properties, such as incurring a latency to spike depending on subsequent input events. Formulation of dynamics in terms of events and separation of the dynamics into these two regimes are fundamental characteristics of the model.

Linear dual-regime bi-dimensional dynamics (for states v and u) may be defined by convention as:

$\begin{array}{cc}{\tau }_{\rho }\frac{v}{t}=v+q_{\rho }& \left(5\right)\\ -{\tau }_u\frac{u}{t}=u+r,& \left(6\right)\end{array}$

where q_ρ and r are the linear transformation variables for coupling.

The symbol ρ is used herein to denote the dynamics regime with the convention to replace the symbol ρ with the sign “−” or “+” for the negative and positive regimes, respectively, when discussing or expressing a relation for a specific regime.

The model state is defined by a membrane potential (voltage) v and recovery current u. In basic form, the regime is essentially determined by the model state. There are subtle, but important aspects of the precise and general definition, but for the moment, consider the model to be in the positive regime 404 if the voltage v is above a threshold (v₊) and otherwise in the negative regime 402.

The regime-dependent time constants include τ₋ which is the negative regime time constant, and τ₊ which is the positive regime time constant. The recovery current time constant τ_u is typically independent of regime. For convenience, the negative regime time constant τ₋ is typically specified as a negative quantity to reflect decay so that the same expression for voltage evolution may be used as for the positive regime in which the exponent and τ₊ will generally be positive, as will be τ_u.

The dynamics of the two state elements may be coupled at events by transformations offsetting the states from their null-clines, where the transformation variables are:

q _ρ=−τ_ρβu−v_ρ  (7)

r=δ(v+ε),  (8)

where δ, ε, β and v₋, v₊ are parameters. The two values for v_ρ are the base for reference voltages for the two regimes. The parameter v₋ is the base voltage for the negative regime, and the membrane potential will generally decay toward v₋ in the negative regime. The parameter v₊ is the base voltage for the positive regime, and the membrane potential will generally tend away from v₊ in the positive regime.

The null-clines for v and u are given by the negative of the transformation variables q_ρ and r, respectively. The parameter δ is a scale factor controlling the slope of the u null-cline. The parameter ε is typically set equal to −v₋. The parameter β is a resistance value controlling the slope of the v null-clines in both regimes. The τ_ρ time-constant parameters control not only the exponential decays, but also the null-cline slopes in each regime separately.

The model may be defined to spike when the voltage v reaches a value v_s. Subsequently, the state may be reset at a reset event (which may be one and the same as the spike event):

v={circumflex over (v)}  (9)

u=u+Δu  (10)

where {circumflex over (v)}₋ and Δu are parameters. The reset voltage {circumflex over (v)}₋ is typically set to v₋.

By a principle of momentary coupling, a closed form solution is possible not only for state (and with a single exponential term), but also for the time to reach a particular state. The close form state solutions are:

$\begin{array}{cc}v\left(t+\Delta t\right)=\left(v\left(t\right)+q_{\rho }\right){}^{\frac{\Delta t}{{\tau }_{\rho }}}-q_{\rho }& \left(11\right)\\ u\left(t+\Delta t\right)=\left(u\left(t\right)+r\right){}^{-\frac{\Delta t}{{\tau }_u}}-r.& \left(12\right)\end{array}$

Therefore, the model state may be updated only upon events, such as an input (presynaptic spike) or output (postsynaptic spike). Operations may also be performed at any particular time (whether or not there is input or output).

Moreover, by the momentary coupling principle, the time of a postsynaptic spike may be anticipated so the time to reach a particular state may be determined in advance without iterative techniques or Numerical Methods (e.g., the Euler numerical method). Given a prior voltage state v₀, the time delay until voltage state v_f is reached is given by:

$\begin{array}{cc}\Delta t={\tau }_{\rho }\log \frac{v_f+q_{\rho }}{v_0+q_{\rho }}.& \left(13\right)\end{array}$

If a spike is defined as occurring at the time the voltage state v reaches v_s, then the closed-form solution for the amount of time, or relative delay, until a spike occurs as measured from the time that the voltage is at a given state v is:

$\begin{array}{cc}\Delta t_S=\{\begin{array}{cc}{\tau }_{+}\log \frac{v_S+q_{+}}{v+q_{+}}& \mathrm{if}v>{\hat{v}}_{+}\\ \infty & \mathrm{otherwise}\end{array},& \left(14\right)\end{array}$

where {circumflex over (v)}₊ is typically set to parameter v₊, although other variations may be possible.

The above definitions of the model dynamics depend on whether the model is in the positive or negative regime. As mentioned, the coupling and the regime p may be computed upon events. For purposes of state propagation, the regime and coupling (transformation) variables may be defined based on the state at the time of the last (prior) event. For purposes of subsequently anticipating spike output time, the regime and coupling variable may be defined based on the state at the time of the next (current) event.

There are several possible implementations of the Cold model, and executing the simulation, emulation or model in time. This includes, for example, event-update, step-event update, and step-update modes. An event update is an update where states are updated based on events or “event update” (at particular moments). A step update is an update when the model is updated at intervals (e.g., 1 ms). This does not necessarily utilize iterative methods or Numerical methods. An event-based implementation is also possible at a limited time resolution in a step-based simulator by only updating the model if an event occurs at or between steps or by “step-event” update.

Long Short-Term Memory in a Spiking Neural Network

Long short-term memory (LSTM) is a microcircuit composed of multiple neurons used in analog neural networks to store values in memory using gating functions and multipliers. LSTMs are able to hold a value in memory for an arbitrary length of time. As such, LSTMs may be useful in learning, classification systems (e.g., handwriting and speech recognition systems), and other applications.

Aspects of the present disclosure are directed to providing long short-term memory using a spiking neural network.

FIG. 5 illustrates an example implementation 500 of the aforementioned long short-term memory (LSTM) in a spiking neural network using a general-purpose processor 502 in accordance with certain aspects of the present disclosure. Variables (neural signals), synaptic weights, system parameters associated with a computational network (neural network), delays, frequency bin information encoding and/or threshold information may be stored in a memory block 504, while instructions executed at the general-purpose processor 502 may be loaded from a program memory 506. In an aspect of the present disclosure, the instructions loaded into the general-purpose processor 502 may comprise code for decoding input spikes into analog values within an LSTM and/or implementing the LSTM based on an encoded representation of the analog values.

FIG. 6 illustrates an example implementation 600 of the aforementioned long short-term memory in a spiking neural network where a memory 602 can be interfaced via an interconnection network 604 with individual (distributed) processing units (neural processors) 606 of a computational network (neural network) in accordance with certain aspects of the present disclosure. Variables (neural signals), synaptic weights, system parameters associated with the computational network (neural network) delays, frequency bin information, encoding and/or threshold information may be stored in the memory 602, and may be loaded from the memory 602 via connection(s) of the interconnection network 604 into each processing unit (neural processor) 606. In an aspect of the present disclosure, the processing unit 606 may be configured to decode input spikes into analog values within an LSTM and to implement the LSTM based on an encoded representation of the analog values.

FIG. 7 illustrates an example implementation 700 of the aforementioned long short-term memory in a spiking neural network. As illustrated in FIG. 7, one memory bank 702 may be directly interfaced with one processing unit 704 of a computational network (neural network). Each memory bank 702 may store variables (neural signals), synaptic weights, and/or system parameters associated with a corresponding processing unit (neural processor) 704 delays, frequency bin information, encoding and/or threshold information. In an aspect of the present disclosure, the processing unit 704 may be configured to decode input spikes into analog values within an LSTM and to implement the LSTM based on an encoded representation of the analog values.

FIG. 8 illustrates an example implementation of a neural network 800 in accordance with certain aspects of the present disclosure. As illustrated in FIG. 8, the neural network 800 may have multiple local processing units 802 that may perform various operations of methods described herein. Each local processing unit 802 may comprise a local state memory 804 and a local parameter memory 806 that store parameters of the neural network. In addition, the local processing unit 802 may have a local (neuron) model program (LMP) memory 808 for storing a local model program, a local learning program (LLP) memory 810 for storing a local learning program, and a local connection memory 812. Furthermore, as illustrated in FIG. 8, each local processing unit 802 may be interfaced with a configuration processor unit 814 for providing configurations for local memories of the local processing unit, and with a routing connection processing unit 816 that provide routing between the local processing units 802.

In one configuration, a neuron model is configured for decoding input spikes into analog values within an LSTM and/or implementing the LSTM based on an encoded representation of the analog values. The neuron model includes decoding means and implementing means. In one aspect, the decoding means and/or implementing means may be the general-purpose processor 502, program memory 506, memory block 504, memory 602, interconnection network 604, processing units 606, processing unit 704, local processing units 802, and or the routing connection processing units 816 configured to perform the functions recited. In another configuration, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

According to certain aspects of the present disclosure, each local processing unit 802 may be configured to determine parameters of the neural network based upon desired one or more functional features of the neural network, and to develop the one or more functional features towards the desired functional features as the determined parameters are further adapted, tuned and updated.

Encoding Analog Values

FIG. 9 illustrates a multi-layer network in accordance with an aspect of the present disclosure. A network 900 in accordance with an aspect of the present disclosure includes input neurons 902, 904, and 906, which may be referred to as input neuron 908 or input x. Each of the input neurons 902-906 has an output coupled to an input of one or more hidden neurons 910-916, which may be collectively referred to as hidden neurons 918. For example, the input neuron 902 has an output 920 coupled to the hidden neuron 910 and an output 922 coupled to the hidden neuron 916. Other outputs from the input neurons 908 may exist, but are not shown for ease of explanation.

In a similar fashion, the hidden neurons 918 are coupled to one or more output neurons 924-928, collectively referred to as output neurons 930. The relationship between the input neurons 908 and the hidden neurons 918 is given by:

h=f ₁(Wx),  (15)

where h is the hidden neuron output, x is the input neurons' input to the hidden neurons 918, W is a matrix of weightings for the input neurons 908, and f₁ is a function, typically a non-linear function.

Similarly, the relationship between the hidden neurons 918 and the output neurons 930 is given by:

y=f ₂(Uh),  (16)

where y is the output neuron output, h is the hidden neurons' input to the output neurons 930, U is a matrix of weightings for the hidden neurons 918, and f₂ is a function, typically a non-linear function. The matrices W and U manipulate the activation energies of the input (x), hidden (h), and output (y) neurons within a neural network.

In aspects of the present disclosure, the problem of realizing a pre-trained network is addressed by encoding values, which may be non-binary values, using spikes (which encode binary values), using exponential dynamics in spiking neurons to achieve matrix multiplication, alterations to the neuron model, and/or connecting spiking neurons to achieve the “maximum” function in the neural network.

To realize the pre-trained neural network, the present disclosure may employ a classifier, which may be a linear classifier, with leaky integrate and fire (LIF) neurons. This classifier may use different types of coding, such as logarithmic temporal coding or base expansive coding, for example. The classifier, which may be a linear classifier, may also be extended to assist in realizing multilayer artificial neural networks (more specifically multilayer perceptrons), including deep convolutional networks (DCNs). Perceptron training using STDP rules and realizing polynomial transformations using spikes are also considered.

Binary Input Data

To realize a linear classifier for binary input data x (i.e., xε{0, 1}ⁿ), m input neurons may be connected to one output neuron with synaptic weights given by the vector w. The input neurons will spike if the corresponding input is 1 and will not spike if it is 0. An orchestrator neuron may also be connected to the output neuron with a synaptic weight of w_t to ensure that the output neuron does not spike without any input.

The input current into the output neuron is equal to w^Tx+wt, which is added to the output neuron's membrane potential. The output neuron spikes by comparing its membrane potential with the threshold, where ŷ is the output spike from the classifier and x is the input:

ŷ=w ^T x+wt>vt.  (17)

If the weight (wt) from the orchestrator neuron is matched to the threshold voltage (vt), then the following relation is obtained:

ŷ=sign(w^Tx).  (18)

Because the input is binary, the output neuron may be without dynamics (i.e., h_m=0, where h_m is a voltage multiplication factor). Therefore, whether the output neuron spikes or not, the membrane potential is reset to 0 and the output neuron is ready to classify a new input instance. Therefore, for binary input data, a linear classifier may be realized with binary (spike/no-spike) encoding and an orchestrator neuron to control the output spikes.

Orchestrator Neuron

The orchestrator neuron plays a more significant role when working with non-binary input data. Artificial neural networks (ANNs), of which a linear classifier is an example, are synchronous (i.e., ANNs process data as frames). Spiking neural networks (SNNs) are asynchronous, where spikes and data can be processed at any time. There is no “frame” or time baseline in SNNs.

One approach for SNNs is to design asynchronous processes and work with asynchronous sensors. Another concept, according to an aspect of the present disclosure, introduces the concept of frames into SNNs, which may be implemented with the orchestrator neuron.

The orchestrator neuron may signal an event in the network, such as the end of frame. When a neuron is processing a frame, it may operate in the sub-threshold regime, making sure it does not spike. Once the neuron processes the entire frame, it receives a signal from the orchestrator neuron and gets pushed to the regime where it can spike.

Non-Binary Input Data

Spiking neurons may naturally represent binary data (i.e., a 0 for a “no spike” condition and a 1 for a “spike” condition). To realize a linear classifier with non-binary input data, the present disclosure, in an aspect, implements an encoding scheme to represent a non-binary number using binary spikes. Although there are many ways to perform this encoding, which are within the scope of the present disclosure, the present disclosure will describe two different methods for ease of explanation: base expansive coding and logarithmic temporal coding.

Base Expansive Coding

In the following explanation, an input vector will have a dimension m=2 (i.e., x=[a b]^T is a two-dimensional vector). However, the present disclosure will work with arbitrary input vector dimensions without departing from the scope of the present disclosure.

A possible binary representation of non-binary numbers a, bε[0, 1] is a binary expansion. In base expansive coding, an analog number may expand via a series of ratios. For example, to encode a value “a” between 0 and 1, the following expansion may be used:

$\begin{array}{cc}\alpha =0·{\alpha }_1{\alpha }_{2}\dots {\alpha }_m=\frac{{\alpha }_1}{\beta }+\frac{{\alpha }_2}{{\beta }^2}+\dots +\frac{{\alpha }_m}{{\beta }^m},& \left(19\right)\end{array}$

where α₁, α₂, . . . α_m are binary spikes and β, β2, βm are delay factors for the spikes in the network and m represents a desired bit width for each element in the input vector. It is noted that higher values of m improve the approximation. Although β is two in this example, it is not limited to such a value.

Given this binary expansion, each non-binary input value may be encoded using one input neuron through a sequence of spikes. The spikes may be expanded with either the most significant bit (MSB) first (i.e., α₁) or the least significant bit (LSB) first, because it is an additive series. Because the bits may be sent in either order, the number of bits in a base expansive coding approach may be limited to any number of bits in an MSB approach or an LSB approach. For example, and not by way of limitation, if there are fifteen spikes in the input layer, the encoding may be limited to the most significant eight or nine spikes, if desired.

For an LSB first approach, the input vector x=[a b]^T is received at time t=0. The input neurons spike at time t=1 if the corresponding LSB is equal to 1. The input neurons spike at time t=2 if the second LSB is equal to 1, etc., up to time t=m when the input neurons spike if the MSB is equal to 1.

In an exemplary aspect where all of the synapses have a unit delay, the input current starts arriving into the output neuron starting at time t=2. If a LIF model output neuron is employed with h_m=0.5, then the output neuron, which may be configured as a bit-shift neuron computes w^Tx. That is, the bit-shift neuron may generate spikes that represent the non-binary value f(w^Tx) according to base expansive coding, where f(.) is an arbitrary activation function. Using its LIF/ALIF dynamics, the bit-shift neuron may accumulate synaptic current and may be configured such that its membrane potential v is equal to the linear combination w^Tx. The membrane potential may in turn be compared to a threshold to realize a linear classifier.

Accordingly, in the example above where all of the synapses have a unit delay, t=2, and h_m=5, w^Tx may be computed as follows:

v(1)=0

v(2)=w₁a_m+w₂b_m

v(3)=v(2)/2+w₁a_m-1+w₂b_m-1

v(m+1)=v(m)/2+w₁a₁+w₂b₁  (20)

Summing the terms gives:

$\begin{array}{cc}v\left(m+1\right)=w_1\sum _{t=1}^ma_t/2^{t-1}+w_2\sum _{t=1}^mb_t/2^{t-1}=2\left(w_1a+w_2b\right)=2w^Tx.& \left(21\right)\end{array}$

Similar to the scenario with binary inputs, an orchestrator neuron ensures that the output neuron does not spike until t=m+2. The orchestrator neuron is connected to the output neuron with a synaptic weight of w_t. The orchestrator neuron spikes at time m+1, signaling the end of frame. The orchestrator spike arrives at the output neuron at time t=m+2, and the output neuron's membrane potential is updated to:

v(m+2)=v(m+1)/2+v_t=w^Tx+w_t  (22)

The output neuron spikes at time t=m+2 depending on:

$\begin{array}{cc}\hat{y}=v\left(m+2\right)>v_t=w^Tx+w_t>v_t.& \left(23\right)\end{array}$

Matching the weight from the orchestrator neuron to the threshold voltage yields:

ŷ=sign(w^Tx)  (24)

For an aspect of the present disclosure employing an MSB first approach (or binary coding), an ALIF output neuron is placed in the network with h_m=2 instead of h_m=0.5. The synaptic weights between input and output neurons are set to w/2^m instead of w.

On the other hand, for an aspect employing binary expansive coding, the voltage multiplication factor h_m may, for example be provided as h_m=β or h_m=1/β.

Again, the output neuron (e.g., bit-shift neuron) essentially computes w^Tx:

v(1)=0

v(2)=w₁a₁+w₂b₁)/2^m

v(3)=2*v(2)+(w₁a₂+w₂b₂)/2^m

v(m+1)=2*v(m)+(w₁a_m+w₂b_m)/2^m,  (25)

Summing the terms gives:

$\begin{array}{cc}v\left(m+1\right)=w_1\sum _{t=1}^ma_t/2^t+w_2\sum _{t=1}^mb_t/2^t=w_1a+w_2b=w^Tx.& \left(26\right)\end{array}$

An orchestrator neuron ensures that the output neuron does not spike until t=m+2. The orchestrator neuron is connected to the output neuron with a synaptic weight of w_t. The orchestrator neuron spikes at time m+1, signaling the end of frame. The orchestrator spike arrives at the output neuron at time t=m+2, and the output neuron's membrane potential is updated to:

v(m+2)=2*v(m+1)+v_t=2w^tx+v_t,  (27)

The output neuron spikes at time t=m+2 depending on:

$\begin{array}{cc}\hat{y}=v\left(m+2\right)>w_t=2w^Tx+w_t>v_t.& \left(28\right)\end{array}$

Matching the weight from the orchestrator neuron to the threshold voltage gives:

ŷ=sign(w^Tx)  (29)

An output neuron in the above explanations has LIF/ALIF dynamics, which may cause the network to not be immediately ready to process a new input instance. In an aspect of the present disclosure, a reset orchestrator neuron, which could signal either input arrival or end of a frame, may be employed to allow output neurons to always be ready to process a new input instance. This reset orchestrator neuron can reset the output neuron's voltage to 0, by first inhibiting the voltage to and then bringing the voltage back to 0 through an excitatory synapse.

Logarithmic Temporal Coding

In logarithmic temporal coding, a binary number may also be expanded via a series of ratios. For example, to encode a value “a” between 0 and 1, the following expansion may be used:

$\begin{array}{cc}\alpha =0·{\alpha }_1{\alpha }_{2}\dots {\alpha }_m=\frac{{\alpha }_1}{\beta }+\frac{{\alpha }_2}{{\beta }^2}+\dots +\frac{{\alpha }_m}{{\beta }^m}& \left(30\right)\end{array}$

In logarithmic temporal coding, only the first non-zero MSB is retained, and other bits are set to zero. The binary values α₁, α₂, . . . α_m, are input as spikes. In an MSB first approach, upon receiving a non-zero value for one of the spikes, the remaining spikes are set to zero. In an LSB first approach, spikes are sent until a zero spike is reached, and the last non-zero spike is retained.

Binary expansive coding (base expansive coding) may be employed at input neurons where spikes are fed through extrinsic axons, which allow the use of an arbitrary coding scheme. However, this may indicate modifications to the neuron model(s), and output neurons in such a network may not be able to operate using a similar coding scheme.

Logarithmic temporal coding, which is a variant of binary expansive coding, may be used as a coding method by intermediate and output neurons. In logarithmic temporal coding, an additional constraint of having a single spike for each frame is added to the base expansive coding scheme. With a frame length of m, a spike at position i represents a value of 1/β_i for i=1, 2, . . . m.

FIG. 10 illustrates differences between binary expansive coding and logarithmic temporal coding in accordance with an aspect of the present disclosure. A table 1000 illustrates a value 1002 that is to be encoded in a base expansive code 1004 (also known as a binary expansive code) and in a logarithmic temporal code 1006. In the example of FIG. 10, the frame length of the code is 3 (i.e., m=3). Column 1004 illustrates an MSB first base expansive code output for each of the values 1002, and column 1006 illustrates a logarithmic temporal code output for each of the values 1002.

At certain instances of the value 1002, the output for both codes is the same. For example, for the value of 0.25, both the base expansive code 1004 and the logarithmic temporal code 1006 output a value of “010.” However, at other values, the codes are different values. For example, at the value of 0.75 the base expansive code 1004 outputs a value of “110” while the logarithmic temporal code 1006 outputs a value of “100.” Depending on the neuron model(s) in the network, one code may be preferable over another.

Perceptron Training Process

Given some input data x_iε[0, 1]ⁿ and the corresponding labels y_iε{0, 1}, a linear classifier of:

ŷ=sign(w^Tx),  (31)

may be trained as follows.

A perceptron training process is an “online” training process that may learn a linear separating hyper-plane if the input data is linearly separable. The process starts with random initial weights w, and iteratively updates the weights if a training sample (x, y) is misclassified:

w←w+η(y−ŷ)x  (32)

where η is the learning rate of the process.

Spike Timing Dependent Plasticity

With respect to training the neural network using STDP rules, the present disclosure alters and/or designs the STDP curves to realize perceptron training, which may be used in a single-layer artificial neural network (ANN). Neural networks that produce analog or other non-binary outputs, such as an ANN, may be generally referred to as non-binary neural networks.

FIGS. 11 and 12 illustrate aspects of the present disclosure. FIG. 11 illustrates a series of outputs 1100, which may be referred to as spikes, occurring at time t=1, time t=2, and time t=3. Although a single layer ANN is shown, with only two inputs 1108 coupled to a single output 1110, the network may be expanded to additional inputs 1108, additional outputs 1110, and additional layers within the scope of the present disclosure. To train such a base expansion coded network, where the LSB is transmitted first, FIG. 12 illustrates a STDP graph 1200. The graph 1200 describes the post-neuron firing value minus the pre-neuron firing value on the x-axis versus a weighting value (the STDP value) on the y-axis.

The graph 1200 of FIG. 12 allows the network to classify inputs 1108. In an aspect of the present disclosure, the graph 1200 allows the network to classify the inputs 1108 in a linear fashion.

FIGS. 13 and 14 illustrate a network in accordance with an aspect of the present disclosure. FIG. 13 illustrates a series of spikes 1300, occurring at time t=1, time t=2, and time t=3. For simplicity of explanation, only two inputs 1308 are shown coupled to a single output 1310. To train such a base expansion coded network, where the MSB is transmitted first, FIG. 14 illustrates a STDP graph 1400. The graph 1400 describes the post-neuron firing value minus the pre-neuron firing value on the x-axis versus a weighting value (the STDP value) on the y-axis.

The graph 1400 of FIG. 14 allows the network to classify inputs 1308. In an aspect of the present disclosure, the graph 1400 allows the network to linearly classify the inputs 1308.

In another aspect of the present disclosure, realization of a pre-trained neural network may use exponential dynamics within the spiking neurons to achieve matrix multiplication. As with the coding approach chosen, this aspect of the present disclosure may use either the most significant bit (MSB) or least significant bit (LSB) first in an expansive coding. Depending on the neuron model used, the MSB or LSB approach may be desired. For example, and not by way of limitation, in the LIF neuron model, the LSB may be used first in the expansive coding, while in the ALIF model, the MSB may be used first in the expansive coding.

In an MSB approach, the STDP curve may take the form:

$\begin{array}{cc}\mathrm{STDP}\mathrm{Value}=\{\begin{array}{cc}\eta /{\beta }^{-\Delta t}& \mathrm{if}-m\le \Delta t\le -1,\\ -\eta /{\beta }^{m-\Delta t+1}& \mathrm{if}1\le \Delta t\le m,\\ 0,& \mathrm{otherwise}.\end{array}& \left(33\right)\end{array}$

In an LSB approach, the STDP curve may take the form:

$\begin{array}{cc}\mathrm{STDP}\mathrm{Value}=\{\begin{array}{cc}\eta /{\beta }^{m+\Delta t+1}& \mathrm{if}-m\le \Delta t\le -1,\\ -\eta /{\beta }^{\Delta t}& \mathrm{if}1\le \Delta t\le m,\\ 0,& \mathrm{otherwise}.\end{array}& \left(34\right)\end{array}$

These expansive codings are combined with neuron model(s) to achieve matrix multiplication. The voltage multiplication factor “h_m” in the neuron models is chosen to match with the base parameter beta (β) of the base expansive encoding or the logarithmic temporal coding methods. In an aspect of the present disclosure, the parameter h_m is chosen as β or 1/β, to achieve matrix multiplication.

Orchestrator Neurons

FIG. 15 illustrates a network 1500 having an orchestrator neuron 1506 in accordance with an aspect of the present disclosure. Input neurons 1502 are coupled to an output neuron 1504. In the network 1500, an orchestrator neuron 1506 is also coupled to the output neuron 1504. Voltages generated by the input neurons 1502 are given by v=w^Tx, where w is the matrix transformation and the weighting of each of the synapses coupling the input neurons 1502 and the output neuron 1504.

The STDP curve 1508 for the orchestrator neuron 1506 shows that the orchestrator neuron 1506 fires before the input neurons 1502. Because the orchestrator neuron 1506 may be used in an asynchronous network, such as a spiking neural network (SNN), there are no time intervals shown in the graph 1510. Further, an output 1512 from the orchestrator neuron 1506, when followed by an output 1514 from an input neuron 1502, enables or makes possible the output 1516 from output neuron 1504. As such, the use of the orchestrator neuron 1506 may simulate the response of a synchronous network, such as an artificial neural network (ANN).

The orchestrator neuron 1506 may also signal an event within the network 1500. The event may be an end of a data frame or a beginning of a data frame. The event may occur in an artificial neural network when the artificial neural network is constructed from one or more spiking neural networks. This approach may be realized by coupling the orchestrator neuron 1506 to other neurons, such as the output neuron 1504 shown in FIG. 15, which have input synapses (such as the input synapses from input neurons 1502) in the network 1500. In this aspect, the output neuron 1504 coupled to the orchestrator neuron 1506 may assign a high priority (weight) to the orchestrator neuron output 1512. Such an approach allows the output neuron 1504 coupled to the orchestrator neuron 1506 to produce an output spike only when receiving an output 1512 from the orchestrator neuron 1506. The output 1516 may indicate that the data frame has been processed, or may indicate that the data frame just started.

The use of the orchestrator neuron 1506 may introduce the concept of data frames into asynchronous networks. In order to properly compute matrix multiplications within the network 1500, the orchestrator neuron 1506 forces the output neuron 1504 to spike only at certain times, such as the end of a data frame. This may occur by operating the output neuron 1504 in a sub-threshold (non-spiking) regime until the orchestrator neuron 1506 provides an output 1512 to the output neuron 1504. The orchestrator neuron output 1512 then moves the output neuron 1504 above the spiking threshold, and the output neuron 1504 provides an output 1516 to indicate the end of the frame processing (or other event within the network 1500). By assigning a proper weight, which may be a high weight, to the orchestrator neuron 1506 output, the output neuron 1504 may provide the output 1516 regardless of the outputs 1514 from any coupled input neurons 1502. The orchestrator neuron 1506 may also signify other events, such as a start of the frame, in which case the orchestrator neuron 1506 may be referred to as a “reset orchestrator neuron.”

In another aspect of the present disclosure, the neuron model may be modified to provide encoding of non-binary values within the network. This may be achieved in an aspect of the present disclosure by providing neurons with additional capabilities, such as performing vector multiplication, applying an arbitrary activation function to the neuron model, or incorporating the MSB/LSB expansive coding approaches into the neuron model within the neural network. Depending on the base neuron model, other operations may be enabled, such as applying a clipping function, a logarithmic temporal coding approach, rounding a value up or down, or other functions.

To realize a linear classifier using binary expansive coding, once a binary expansion of the input values has been implemented, and the binary sequences fed as spike sequences into the input neurons, the output neuron can use its LIF/ALIF dynamics to accumulate the synaptic current and have its membrane potential (v) equal to the linear combination w^Tx. The membrane potential v=w^Tx is then compared to a threshold and the linear classifier is obtained.

The neuron model may be modified so that it emits spikes encoding the non-binary value clip(w^Tx). This may be accomplished by modifying the neuron's update rule to:

v←v>>1

• • if v mod 2>=1 then spike.

This update rule encodes the membrane potential (v) according to a MSB-first binary expansive coding scheme. This update rule may be integrated into the ALIF neuron model that can accumulate the input synaptic current and compute the linear combination w^Tx. The overall neuron update rule model may then be modified as follows:

v(v−1)+i_s

• • if (v mod 2>=1) and (mode=1) then spike.

The additional state variable called ‘mode’ is a Boolean state variable that specifies if the neuron can spike or not. Such an approach is similar to the orchestrator neuron 1506 that ensures the output neuron 1504 can only spike after processing the entire input frame. The output neuron's mode is set to ‘spike mode’ after processing the entire frame. Before that, the neuron is in accumulation mode and computes the linear combination w^Tx without premature spiking.

During the training phase of a neural network, in accordance with an aspect of the present disclosure, a supervising neuron (i.e., the orchestrator neuron 1506) is added to the spiking neural network 1500. The supervising neuron represents the desired output. Similar to the input neurons 1502, the supervising neuron spikes if y=1 and does not spike if y=0. However, the supervising neuron spikes one tau (time period) earlier than the input neurons 1502. Further, the synaptic weight from the supervising neuron to the output neuron 1504 is set to a high enough value that the supervision spike will certainly cause a spike at the output neuron 1504. During the training phase, given a training sample (x, y), the label (y) may be supplied to the supervising neuron at time t=0, and the binary input (x) is fed into the input neurons at time t=1. The supervision spike arrives at the output neuron at time t=1 and causes an output spike if y=1. The input spikes arrive at time t=2 and cause an output spike if ŷ=1.

In another aspect of the present disclosure, a network may also employ a “maximum” function, where the output is based on a maximum value of a number of inputs. An output z may be determined by a maximum of the inputs y over the values y1, y2, . . . yn, and the output z is then assigned to the kth value of y. The index k may also be determined by the maximum function.

Long Short-Term Memory

FIG. 16 is a block diagram 1600 illustrating an exemplary long short-term memory in accordance with aspects of the present disclosure. Referring to FIG. 16, the LSTM includes input neurons (1602a, 1062b, 1602c, and 1602d), gate neurons 1604, a state cell 1606 and an output neuron 1608. Each of these elements of the LSTM may be coupled together via a synapse (shown as arrows in FIG. 16). In some aspects, the synapses in the LSTM may be configured with a fixed weight. In one example, each of the synapses may be configured with unit weight (w=1).

The input neurons (e.g., 1602a, 1602b, 1602c, and 1602d) may comprise, for example, bit-shift neurons (e.g., when base-expansive coding is employed). The bit-shift neurons may be configured to represent spike inputs as analog values. The spike inputs, which may represent positive or negative values, may be decoded and/or encoded by applying a scheme such as base expansive coding described above. Of course, this is merely exemplary, and other encoding/decoding schemes may also be used. For example, in some aspects, latency coding, rate coding or coding using synapse weight may be used to encode and/or decode the spikes to represent analog input values or vice versa.

In some aspects, the bit-shift neurons may also be configured with an activation function (logistic, tanh, and the like). The activation function may inject a degree of non-linearity into the system and improve performance.

The analog values corresponding to the input spikes may be encoded as spikes and supplied to gating neurons (e.g., 1604a and 1604b) and the output neuron 1608 along with an input gating signal via the input 1602b (at gating neuron 1604a) and feedback from the state neuron 1606 (at gating neuron 1604b.) The gating neurons (e.g., 1604a and 1604b) may be configured with a multiplier that multiplies the input values together. The input gating neuron (e.g., 1604a) may decode the spikes representation of the analog input values and analog input gating signal and perform the multiplication operation. The input gating neuron (e.g., 1604a) may then encode the product of the multiplication operation as spikes, which are supplied as a state input to the state cell 1606.

The state cell 1606 may similarly decode the spikes representation of the state input and accumulates theses analog values. The state cell 1606 may maintain a state value corresponding to the accumulated input from the input neurons (e.g., 1602a). For example, where v₁ is the input from input neuron 1 and v₂ is the input from input neuron 2, the state cell may maintain a state value of v₁+v₂. In some aspects, the input values (e.g., v₁, v₂) may also be stored.

A maintenance signal (e.g., Forget) may be applied via the input neuron 1602c to manage the state values in the state cell 1606. In some aspects, the maintenance signal may be supplied as spikes. The spikes representing the maintenance signal may be decoded via the input neurons (e.g., 1602c) to produce an analog value. The analog value corresponding to the maintenance signal may, in turn, be encoded as spikes and supplied to a gating neuron (1604). The gating neuron 1604b (forget gate) may decode the maintenance signal along with the state values, which may be supplied via a feedback loop 1610. The analog values of the state values and the maintenance signal are multiplied and used to determine whether the state values are to be maintained (e.g., maintenance value=1) or forgotten (e.g., maintenance value=0). Although, the exemplary maintenance values presented are binary, the disclosure is not so limited, and the maintenance value may comprise a non-binary value. As such, state values in the state cell 1606 may be maintained by a forget gate (e.g., 1604b) and input gate (e.g., 1604a). For example, if the spiking LSTM receives a spike train while the forget gate is ‘1’ and the input gate is ‘0’ then the spike train will be fully maintained.

In some aspects, the present state value may be combined with a subsequent or new input provided via an input neuron (e.g., 1602a). That is, where the state value is maintained and new input values are passed via the gating neurons (e.g., 1604a), the state cell 1606 may add the new input values to the maintained state value to produce a new state value, for example.

The state values may be encoded as spikes and supplied to the output neuron 1608. In some aspects, an output gating signal may be applied to control the outputting of the state values. As such, the output neuron 1608 multiplies the state value with the output gating signal, which may be supplied via an input neuron (e.g., 1602d). For example, the computed state value (e.g., v₁+v₂) may be multiplied by the output gating signal. In some aspects, the output gating signal may be, for instance, 0 to suppress the output or 1 to enable the state value to be output, for example. Although, the exemplary output gating signals presented are binary, the disclosure is not so limited, and the output gating signals may have a non-binary value (e.g., a value between 0 and 1).

FIG. 17 is block diagram 1700 illustrating an exemplary LSTM in accordance with aspects of the present disclosure. In the exemplary LSTM of FIG. 17, a bit shift neuron is used for the input gate 1702a while binary neurons are used for the input gates 1702b, 1702c, and 1702d. In FIG. 17, instead of bit-shift neurons with multipliers (see FIGS. 16, 1604a and 1604b), gated bit-shift neurons are used for the gate neurons 1704a and 1704b. A gated bit-shift neuron is a bit-shift neuron in that it may receive a spike input, convert the input to an analog value and output a spike train. However, for the gated bit-shift neuron, the spike train is gated according to a binary threshold. For example, if the binary signal is 1, then the gate is open and the value from the input neuron (e.g., 1702a) is passed through. On the other hand, if the binary value is 0, the gate is closed and the input is not passed through.

In one aspect, all gating signals are converted to binary signals by applying a threshold via input gates 1702b, 1702c and 1702d. For example, for a bit-width of 4 and a threshold of 0.5, a value of 0.2 may be converted to ‘0000’ and a value of 0.7 may be converted to ‘1111.’

The incorporation of binary neurons (e.g., 1702b, 1702c, and 1702d) may be beneficial for reducing computational costs of the LSTM. Because the output of the binary neuron (e.g., 1702b, 1702c, and 1702d) is either a 0 or a 1, the complexity decoding operation with respect to the gating signal (e.g., input gating signal) at the gating neuron (e.g., 1704a) is reduced. The multiplication operations at the succeeding layers are also simplified. This is because the input value is multiplied by either a 0 or a 1, at each time step in a frame. As such, the LSTM may be operated without complex multiplication operations. Furthermore, in some aspects, the LSTM may be operated without using additional state variables to store v₁ and v₂.

Each of the gate neurons (e.g., 1704a, and 1704b) may comprise a “gate” variable. The gate variable may be set by a synapse provided between binary threshold neurons (e.g., 1702b, 1702c, and 1702d) and gate neurons (e.g., 1704a and 1704b). The gate variable may be supplied to the gated bit shift neurons (e.g., 1704a, and 1704b) and multiplied with an input value, for example. In one example, gate neuron 1704a may receive an input signal=‘1010’ supplied via the input neuron 1702a and an input gate signal=0000 supplied via input neuron 1702b. The input spikes may be respectively decoded to produce an analog input signal=10 and an analog input gate signal=0. The analog value of the input signal may be multiplied by the analog value of the input gate signal to produce v=10*0=0. The product may be compared to a threshold value and encoded as spikes. Accordingly, in this example, the output of gate neuron (e.g., 1704a) may be given by gate output=‘0000’ and the state value of state cell 1706 may be maintained. In turn, the output neuron 1708 may output the state value under the control of the output gating signal received via input neuron 1702d.

In some aspects, the LSTM may be further configured with a peephole or a feedback connection (e.g., constant error carousel (CEC)) from the state cell (e.g., 1606, or 1706) to the gate cells. This may be beneficial for improving the learning capability of the LSTM, for example.

FIG. 18 illustrates a method 1800 for configuring a long short-term memory in a spiking neural network. In block 1802, the neuron model decodes input spikes into analog values within an LSTM. The input spikes may include an input signal and one or more gating signals. In some aspects, the gating signals may include an input gating signal, a maintenance (“forget”) signal, and/or an output gating signal. In some aspects, the gating signals (e.g., the input gating signal, the maintenance signal and the output gating signal) may be converted to a binary value by applying a threshold value.

In block 1804, the neuron model implements the LSTM based on an encoded representation of the analog values. The encoded representation of the analog values may be generated using base expansive coding, rate coding, latency coding or synaptic weight coding. In some aspects, the LSTM may be configured to represent analog values that are positive or negative. In one example, the sign of the analog value may be represented via a sign bit. Furthermore, an activation function may also be applied to provide a measure of non-linearity and improve performance.

In some aspects, the neuron model may further generate a state value based on a product of values corresponding to encoded representations of the input signal and the gating signal. The state value may be maintained based on a product of values corresponding to encoded representations of the maintenance signal and the state value.

In some aspects, the neuron model may be configured to output (and/or suppress) the state value based on a product of values corresponding to encoded representations of the output gating signal and the state value.

The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to, a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in the figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.

As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Additionally, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Furthermore, “determining” may include resolving, selecting, choosing, establishing and the like.

As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.

The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method or process described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable disk, a CD-ROM and so forth. A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. A storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

The functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a device. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement signal processing functions. For certain aspects, a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further.

The processor may be responsible for managing the bus and general processing, including the execution of software stored on the machine-readable media. The processor may be implemented with one or more general-purpose and/or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Machine-readable media may include, by way of example, random access memory (RAM), flash memory, read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable Read-only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer-program product. The computer-program product may comprise packaging materials.

In a hardware implementation, the machine-readable media may be part of the processing system separate from the processor. However, as those skilled in the art will readily appreciate, the machine-readable media, or any portion thereof, may be external to the processing system. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer product separate from the device, all which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or general register files. Although the various components discussed may be described as having a specific location, such as a local component, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.

The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture. Alternatively, the processing system may comprise one or more neuromorphic processors for implementing the neuron models and models of neural systems described herein. As another alternative, the processing system may be implemented with an application specific integrated circuit (ASIC) with the processor, the bus interface, the user interface, supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.

The machine-readable media may comprise a number of software modules. The software modules include instructions that, when executed by the processor, cause the processing system to perform various functions. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module.

If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects computer-readable media may comprise non-transitory computer-readable media (e.g., tangible media). In addition, for other aspects computer-readable media may comprise transitory computer-readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media.

Thus, certain aspects may comprise a computer program product for performing the operations presented herein. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. For certain aspects, the computer program product may include packaging material.

Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, various methods described herein can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described herein to a device can be utilized.

It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A method for configuring long short-term memory (LSTM) in a spiking neural network, comprising: decoding input spikes into analog values within the LSTM; andimplementing the LSTM based at least in part on an encoded representation of the analog values.

2. The method of claim 1, in which the implementing comprises encoding the analog values using base expansive coding, rate coding, latency coding or synaptic weight coding.

3. The method of claim 1, in which at least one analog value is negative.

4. The method of claim 1, in which the implementing comprises applying an activation function.

5. The method of claim 1, in which the input spikes include an input signal and a gating signal, and in which the implementing further includes generating a state value based at least in part on a product of values corresponding to encoded representations of the input signal and the gating signal.

6. The method of claim 5, in which the input spikes further include a maintenance signal and in which the state value is maintained based at least in part on a product of values corresponding to encoded representations of the maintenance signal and the state value.

7. The method of claim 5, in which the input spikes further include an output gating signal and in which the state value is output based at least in part on a product of values corresponding to encoded representations of the output gating signal and the state value.

8. The method of claim 5, in which the gating signal comprises a binary signal.

9. An apparatus for configuring long short-term memory (LSTM) in a spiking neural network, comprising: a memory; andat least one processor coupled to the memory, the at least one processor being configured:to decode input spikes into analog values within the LSTM; andto implement the LSTM based at least in part on an encoded representation of the analog values.

10. The apparatus of claim 9, in which the at least one processor is further configured to encode the analog values using base expansive coding, rate coding, latency coding or synaptic weight coding.

11. The apparatus of claim 9, in which at least one analog value is negative.

12. The apparatus of claim 9, in which the at least one processor is further configured to implement the LSTM by applying an activation function.

13. The apparatus of claim 9, in which the input spikes include an input signal and a gating signal, and in which the at least one processor is further configured to generate a state value based at least in part on a product of values corresponding to encoded representations of the input signal and the gating signal.

14. The apparatus of claim 13, in which the input spikes further include a maintenance signal and in which the at least one processor is further configured to maintain the state value based at least in part on a product of values corresponding to encoded representations of the maintenance signal and the state value.

15. The apparatus of claim 13, in which the input spikes further include an output gating signal and in which the at least one processor is further configured to output the state value based at least in part on a product of values corresponding to encoded representations of the output gating signal and the state value.

16. The apparatus of claim 13, in which the gating signal comprises a binary signal.

17. An apparatus for configuring long short-term memory (LSTM) in a spiking neural network, comprising: means for decoding input spikes into analog values within the LSTM; andmeans for implementing the LSTM based at least in part on an encoded representation of the analog values.

18. The apparatus of claim 17, further comprising means for encoding the analog values using base expansive coding, rate coding, latency coding or synaptic weight coding.

19. The apparatus of claim 17, in which at least one analog value is negative.

20. The apparatus of claim 17, further comprising means for applying an activation function.

21. The apparatus of claim 17, in which the input spikes include an input signal and a gating signal, and further comprising means for generating a state value based at least in part on a product of values corresponding to encoded representations of the input signal and the gating signal.

22. The apparatus of claim 21, in which the input spikes further include a maintenance signal and further comprising means for maintaining the state value based at least in part on a product of values corresponding to encoded representations of the maintenance signal and the state value.

23. The apparatus of claim 21, in which the input spikes further include an output gating signal and further comprising means for outputting the state value based at least in part on a product of values corresponding to encoded representations of the output gating signal and the state value.

24. A computer program product for configuring long short-term memory (LSTM) in a spiking neural network, comprising: a non-transitory computer readable medium having encoded thereon program code, the program code comprising:program code to decode input spikes into analog values within the LSTM; andprogram code to implement the LSTM based at least in part on an encoded representation of the analog values.

25. The computer program product of claim 24, further comprising program code to encode the analog values using base expansive coding, rate coding, latency coding or synaptic weight coding.

26. The computer program product of claim 24, in which at least one analog value is negative.

27. The computer program product of claim 24, further comprising program code to implement the LSTM by applying an activation function.

28. The computer program product of claim 24, in which the input spikes include an input signal and a gating signal, and further comprising program code to generate a state value based at least in part on a product of values corresponding to encoded representations of the input signal and the gating signal.

29. The computer program product of claim 28, in which the input spikes further include a maintenance signal and further comprising program code to maintain the state value based at least in part on a product of values corresponding to encoded representations of the maintenance signal and the state value.

30. The computer program product of claim 28, in which the input spikes further include an output gating signal and further comprising program code to output the state value based at least in part on a product of values corresponding to encoded representations of the output gating signal and the state value.