The present disclosure relates generally to power circuits, and more particularly but not exclusively to switching converters.
Power converters such as switch mode voltage regulators are widely used to provide power to electronic devices. COT (Constant On-Time) control has been widely used with DC/DC voltage converters for its fast transient response. However, the switching frequency of the COT controlled voltage converter is variable and not constant, which makes COT control hardly applied in cases where a constant switching frequency is essentially required, such as an automobile system. Contrarily, current mode control has a constant switching frequency, but it is slow in transient response, and the minimum on-time or off-time of a power switch during each switching cycle is required to implement current sensing function.
Consequently, a control circuit and scheme thereof with fast transient response and constant switching frequency is needed.
According to an embodiment of the present disclosure, a control circuit for a switching converter is provided. The switching converter having at least one power switch is configured to covert an input voltage into an output voltage in response to a pulse-width modulation (PWM) control signal. The control circuit includes a compensation circuit, a ramp generation circuit, a comparison circuit and a logic circuit. The compensation circuit is configured to generate a compensation signal in response to the output voltage and a reference signal. The ramp generation circuit is configured to generate a ramp signal in response to the PWM control signal. The comparison circuit is configured to provide a comparison signal in response to the compensation signal and the ramp signal. The logic circuit is configured to provide the PWM control signal in response to the comparison signal and a clock signal.
According to another embodiment of the present disclosure, a control circuit for a switching converter is provided. The switching converter having at least one power switch is configured to covert an input voltage into an output voltage in response to a PWM control signal. The control circuit includes a compensation circuit, a ramp generation circuit, a comparison circuit and a logic circuit. The compensation circuit is configured to generate a compensation signal in response to a feedback signal representing the output voltage and a reference signal. The ramp generation circuit configured to generate a ramp signal. The comparison circuit is configured to provide a comparison signal in response to the compensation signal and the ramp signal. The logic circuit is configured to provide the PWM control signal in response to the comparison signal and a clock signal. The PWM control signal is at a first voltage level when a value of the ramp signal reaches a value of the compensation signal. The PWM control signal is at a second voltage level in response to the clock signal.
The present disclosure can be further understood with reference to the following detailed description and appended drawings, where like elements are provided with like reference numerals. These drawings are only for illustration purpose, thus may only show part of the devices and are not necessarily drawn to scale.
Various embodiments of the present disclosure will now be described. In the following description, some specific details, such as example circuits and example values for these circuit components, are included to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the present disclosure can be practiced without one or more specific details, or with other methods, components, materials, etc. In other instances, well- known structures, materials, processes or operations are not shown or described in detail to avoid obscuring aspects of the present disclosure.
Throughout the specification and claims, the phrases “in one embodiment”, “in some embodiments”, “in one implementation”, and “in some implementations” as used includes both combinations and sub-combinations of various features described herein as well as variations and modifications thereof. These phrases used herein do not necessarily refer to the same embodiment, although it may. Those skilled in the art should understand that the meanings of the terms identified above do not necessarily limit the terms, but merely provide illustrative examples for the terms. It is noted that when an element is “connected to” or “coupled to” the other element, it means that the element is directly connected to or coupled to the other element, or indirectly connected to or coupled to the other element via another element. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.
The feedback circuit 30 is configured to receive the output voltage VOUT and provides a feedback signal VFB proportional to the output voltage VOUT. The control loop circuit 40 is configured to receive the feedback signal VFB and provide a PWM control signal SPWM to the gate driver 20. Accordingly, the gate driver 20 is configured to provide the driving signal (e.g., SD) to at least one switch of the switching converter 10 in response to the PWM control signal SPWM.
However, for high frequency switching converter, using the current sense signal as the ramp signal is not ideal as it has a long settling time. Specifically, for automotive radar system, a fixed high-frequency buck converter is required. Since the baseband frequency of the radar system is wide, for example, from a few KHz to a few MHZ, the switching frequency of the power converter should be higher than 12 MHz. In one example, the switching frequency of the power converter is 18 MHz, each cycle is about 56 ns. For such a short time, it is hard to sense the inductor current IL with the settling time. Therefore, instead of sensing the inductor current IL, a PWM signal is filtered as the ramp signal for the high frequency switching converter.
As shown in
Specifically, the control circuit 300 includes a compensation circuit 310, a ramp generation circuit 320, a comparison circuit 330, and a logic circuit 340. The compensation circuit 310 is configured to receive the output voltage VOUT and a reference signal VREF, and generate a compensation signal Comp in response to the output voltage VOUT and the reference signal VREF. In one embodiment, a feedback signal VFB representing the output voltage VOUT is generated by the feedback circuit 30. The ramp generation circuit 320 is configured to receive the PWM control signal SPWM, and generate a ramp signal Ramp in response to the PWM control signal SPWM. The comparison circuit 330 is configured to receive the compensation signal Comp and the ramp signal Ramp, and provide a comparison signal SCOM in response to the compensation signal Comp and the ramp signal Ramp. The logic circuit 340 is configured to receive the comparison signal SCOM and a clock signal Clk, and provide the control signal SPWM to the gate driver 20 in response to the comparison signal SCOM and the clock signal Clk.
In one embodiment, the PWM control signal SPWM is at a first voltage level (e.g., HSG at a high voltage level or high logic level) to turn on the high side power switch (e.g., M1) when a value of the ramp signal (e.g., Ramp) reaches a value of the compensation signal (e.g., Comp). In one embodiment, the PWM control signal SPWM is at a second voltage level (e.g., HSG at a low voltage level or low logic level) to turn off the high side power switch (e.g., M1) in response to the clock signal clk.
The slope compensation circuit 420 is configured to generate the ramp signal SRAMP in response to the first ramp signal Ramp1, the PWM control signal SPWM, and the clock signal SClk. The ramp signal SRAMP is a periodic signal having a constant frequency set by the clock signal SClk. In one embodiment, the slope compensation circuit 420 includes a frequency control circuit to generate the ramp signal SRAMP in response to an edge of a clock signal (e.g., a rising edge or a falling edge). Accordingly, the switching frequency of the high and low side power switches may be effectively locked to the constant frequency set by the clock signal SClk.
In one embodiment, the ramp generation circuit 400 further includes a high-pass filter circuit 430. The high-pass filter circuit 430 is configured to filter the first ramp signal Ramp 1 and generate a second ramp signal. For instance, a purely AC signal SAC is passed, while the DC signal of the first ramp signal Ramp1 is filtered. Since the DC signal of the first ramp signal Ramp 1 is related to the PWM control signal, determined by the input voltage VIN and the output voltage VOUT, the second ramp signal (e.g., SAC) is not affected by the output load transient, and thus the transient response is improved. In one embodiment, the ramp generation circuit 400 further includes a bias circuit 440. The bias circuit 440 is configured to receive the first ramp signal Ramp1 and adjust the DC bias (e.g., SDC) of the first ramp signal Ramp1 to provide the ramp signal SRAMP (e.g., SRAMP=SAC+SDC). In one embodiment, the DC bias (e.g., SDC) of the ramp signal SRAMP is proportional to the input voltage (e.g., SDC=k*VIN).
As shown in
In one embodiment, an AC tuning circuit 620 is configured to tune the AC amplitude of the PWM control signal. For instance, the AC tuning circuit 620 includes a voltage divider.
The first ramp signal Ramp1 is filtered by a high-pass filter circuit 640. For instance, the high-pass filter circuit 640 includes a capacitor CHPF and a resistor RHPF connected in series to pass the purely AC signal, while the DC signal of the first ramp signal Ramp1 that is related to the output voltage VOUT is filtered. Specifically, a first terminal of the capacitor CHPF is coupled to the first terminal of the capacitor CRAMP to receive the first ramp signal Ramp1, and a second terminal of the capacitor CHPF is coupled to a first terminal of the resistor RHPF to provide the second ramp signal SAC.
In one embodiment, the bias circuit 650 is configured to adjust the DC bias of the ramp signal aVRAMP. In some cases, when the input voltage VIN is at a lower value, while the output voltage VOUT is at a higher value, the output voltage of the error amplifier (e.g., 510) will be at a higher value in response to the output voltage VOUT. When the output voltage VOUT is higher, the ramp signal Ramp1 is also higher, the compensation signal aCOMP would also be higher to reach the ramp signal aRAMP as shown in
For instance, the bias circuit 650 includes an operational amplifier op. In one embodiment as shown in
In one implementation, the slope compensation circuit 660 includes a compensation capacitor CSLOPE, a current source ISLOPE, and a control switch S1.
The current source ISLOPE is configured to provide a charging current. The compensation capacitor CSLOPE is coupled in series with the current source ISLOPE. The first terminal of the compensation capacitor CSLOPE is configured to receive the ramp signal SAC via the transistor M2, and the second terminal of the compensation capacitor CSLOPE is configured to provide the ramp signal aVRAMP. The control switch S1 is coupled in parallel with the compensation capacitor CSLOPE.
In the embodiment as shown in
The control switch S1 is controlled in response to the clock signal SClk. The ramp signal aVRAMP is a periodic signal having a constant frequency set by the clock signal. For instance, the clock signal could be the clock signal Clk as shown in
After the compensation capacitor CSLOPE is reset, the signal dMIN_OFF is triggered at time t3. When the signal dMIN_OFF is triggered at time t3, the signal SPWM transitions to a low logic level, i.e., the high side power switch M1 is turned off and the low side power switch M2 is turned on.
Specifically, the control switch S1 is turned on when the PWM control signal dPWM transitions to the high voltage level at time t1. Meanwhile, the compensation capacitor CSLOPE is short-circuited and reset to provide the ramp signal aVRAMP, and the ramp signal aVRAMP increases as the ramp signal aVRAMP_TOP increases during high side power switch M1 is turned on (e.g., dPWM is at the high voltage level). At time t2, the falling edge of the clock signal dCLK is triggered, and the PWM control signal dPWM transitions to the low voltage level to turn off the high side power switch M1 of the switching converter 12. Accordingly, the high side power switch M1 is turned off and the low side power switch M2 is turned on. At the same time, the signal dRAMP_RST is triggered by the falling edge of the clock signal dCLK. In one embodiment, the control switch S1 is reset by the signal dRAMP_RST for fixed frequency operation. Specifically, during transient event, the PWM control signal dPWM and the switching frequency may change. For instance, during the pulse (high voltage level) of the signal dRAMP_RST, the control switch S1 is turned on and the compensation capacitor CSLOPE is reset. Meanwhile, the ramp signal aVRAMP continues to increase as the ramp signal aVRAMP_TOP increases. After the compensation capacitor CSLOPE is reset, at time t3, the control switch S1 is turned off, and the ramp signal aVRAMP decreases as the ramp signal aVRAMP_TOP decreases during high side power switch M1 is turned off (e.g., dPWM is at the low voltage level). Since the control switch S1 is turned off, the compensation capacitor CSLOPE is discharged by the current source ISLOPE to generate the ramp signal aVRAMP with a steeper slope to enhance the noise immunity.
For illustration purpose, the signals are switched synchronously (e.g., at time t1, t2, t3). However, the present disclosure is not limited thereto. In some embodiments, during switching between different states, a delay time may be set between the signals, or a delay may occur at the rising edge or the falling edge according to the practical application. Thus, the time points of the each signals could be adjusted, or with or without the delay time applied, to perform the function as the control circuit of the present disclosure.
It should be noted that, in the embodiment as shown in
It should be understood that, the control circuit and the related components, circuit structures, signals, and waveforms described or shown above in the present disclosure are only for illustration purpose. However, the present disclosure is not limited thereto. Persons having ordinary skill in the art may understood that the control circuit of the present disclosure could be realized, according to practical applications, by any other circuits with different circuit structures, and thus controlled by different types of the corresponding signals to achieve the corresponding functions. For example, the compensation circuit, the ramp generation circuit, the comparison circuit and the logic circuit could be realized by a digital circuit, an analog circuit, a software, an automatic generation circuit by hardware description language, or a combination of the above.
Based on the above, the present disclosure provides various control circuits for switching converter and control method thereof. The control circuit in the present disclosure provides a loop control methodology for fixed frequency switching converter. For high-frequency applications, the ramp signal settling time is reduced by filtering the PWM signal as the ramp signal. Furthermore, the ramp generation circuit includes a high-pass filter circuit to filter the DC bias of the ramp signal that is related to the output voltage and loading current, and thus the transient response is improved. Moreover, by tracking the input voltage as the DC bias of the ramp signal, the switching converter could operate in a wider operating range (e.g., VIN, VOUT, and IOUT). On top of that, a slope compensation circuit provides a slope current to increase the noise margin to avoid the false triggering oscillation.
It will be appreciated by persons skilled in the art that the present disclosure is not limited to what has been particularly shown and described herein above. Rather the scope of the present disclosure is defined by the claims and includes both combinations and sub-combinations of the various features described hereinabove as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not in the prior art.
The present application claims the benefit of and priority to a U.S. Provisional Patent Application Ser. 63/610,640 filed Dec. 15, 2023, which is hereby incorporated fully by reference into the present application.
Number | Date | Country | |
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63610640 | Dec 2023 | US |