Claims
- 1. A heteroj unction bipolar transistor comprising a substrate having formed thereon a heterojunction bipolar transistor layer structure including an emitter layer including a strained, n-doped compound of indium arsenic and phosphorus.
- 2. A heterojunction bipolar transistor as set forth in claim 1, wherein the indium arsenic phosphide compound is InAsxP1-x, where x is approximately between 0.7 and 1.0.
- 3. A heterojunction bipolar transistor as set forth in claim 2, wherein the n-doping in the emitter layer is approximately between 5×1016 and 2×1018.
- 4. A heterojunction bipolar transistor as set forth in claim 3, wherein the n-doping is substantially constant throughout the emitter layer.
- 5. A heterojunction bipolar transistor as set forth in claim 3, wherein the emitter layer is approximately 200-500 Å thick.
- 6. A heterojunction bipolar transistor as set forth in claim 5, wherein the heterojunction bipolar transistor layer structure further comprises a p-doped base layer between the emitter layer and the substrate.
- 7. A heterojunction bipolar transistor as set forth in claim 6, wherein the base layer is comprised of a material selected from a group consisting of InAs, InAsSb, and GaInAsSb.
- 8. A heterojunction bipolar transistor as set forth in claim 7, wherein the base layer is p-doped to approximately between 2×1018 and 4×1019.
- 9. A heterojunction bipolar transistor as set forth in claim 8, wherein the base layer is approximately 200-1000 Å thick.
- 10. A heterojunction bipolar transistor as set forth in claim 9, wherein the base layer is comprised of a material selected from a group consisting of InAs1-ySby where y is approximately 0.0 to 0.3 and Ga1-xInxAs1-ySby where x is approximately 0.5 to 1.0 and y is approximately 0.0 to 0.5.
- 11. A heterojunction bipolar transistor as set forth in claim 10, wherein the heterojunction bipolar transistor layer structure further comprises a collector layer formed between the base layer and the substrate.
- 12. A heterojunction bipolar transistor as set forth in claim 11, wherein the collector layer is comprised of n-doped InAs.
- 13. A heterojunction bipolar transistor as set forth in claim 12, wherein the collector layer is n-doped to approximately between 5×1015 and 5×1017.
- 14. A heterojunction bipolar transistor as set forth in claim 13, wherein the collector layer is approximately 1000 to 5000 Å thick.
- 15. A heterojunction bipolar transistor as set forth in claim 14, wherein the heterojunction bipolar transistor layer structure further comprises a subcollector layer formed between the collector layer and the substrate.
- 16. A heterojunction bipolar transistor as set forth in claim 15, wherein the subcollector layer is comprised of n-doped InAs.
- 17. A heterojunction bipolar transistor as set forth in claim 16, wherein the subcollector layer is n-doped to approximately between 2×1018 and 3×1019.
- 18. A heterojunction bipolar transistor as set forth in claim 17, wherein the subcollector layer is approximately 1000 Å to 5 μm thick.
- 19. A heterojunction bipolar transistor as set forth in claim 18, wherein a contact is formed on the emitter layer opposite the substrate.
- 20. A heterojunction bipolar transistor as set forth in claim 19, wherein the contact is formed of InAs.
- 21. A heterojunction bipolar transistor as set forth in claim 20, wherein the contact is n-doped to approximately between 2×1018 and 3×1019 cm−3.
- 22. A heterojunction bipolar transistor as set forth in claim 21, wherein the contact is approximately 200 to 2500 Å thick.
- 23. A heterojunction bipolar transistor as set forth in claim 22, wherein a spacer layer is formed between the base layer and the emitter layer.
- 24. A heterojunction bipolar transistor as set forth in claim 23, wherein the spacer layer is p-doped in a range from undoped to 5×1018.
- 25. A A heterojunction bipolar transistor as set forth in claim 24, wherein the spacer layer is formed of InAs.
- 26. A heterojunction bipolar transistor as set forth in claim 25, wherein the spacer layer is up to 100 Å thick.
- 27. A heterojunction bipolar transistor as set forth in claim 26, wherein the substrate is comprised of a material selected from sapphire and a compound including indium and arsenic.
- 28. A heterojunction bipolar transistor as set forth in claim 27, wherein the substrate is comprised of sulfur-doped InAs.
- 29. A heterojunction bipolar transistor as set forth in claim 3, wherein the n-doping is graded across at least a portion of the emitter layer.
- 30. A heterojunction bipolar transistor as set forth in claim 29, wherein the non-graded portion of the emitter is comprised of InAs0.7P0.3.
- 31. A heterojunction bipolar transistor as set forth in claim 1, wherein the heterojunction bipolar transistor layer structure further comprises a p-doped base layer between the emitter layer and the substrate.
- 32. A heterojunction bipolar transistor as set forth in claim 31, wherein the base layer is comprised of a material selected from a group consisting of InAs, InAsSb, and GaInAsSb.
- 33. A heterojunction bipolar transistor as set forth in claim 32, wherein the base layer is p-doped to approximately between 2×1018 and 4×1019.
- 34. A heterojunction bipolar transistor as set forth in claim 33, wherein the base layer is approximately 200-1000 Å thick.
- 35. A heterojunction bipolar transistor as set forth in claim 34, wherein the base layer is comprised of a material selected from a group consisting of InAs1-ySby where y is approximately 0.0 to 0.3 and Ga1-xInxAs1-ySby where x is approximately 0.5 to 1.0 and y is approximately 0.0 to 0.5.
- 36. A heterojunction bipolar transistor as set forth in claim 1, wherein the heterojunction bipolar transistor layer structure further comprises a collector layer formed between the base layer and the substrate.
- 37. A heterojunction bipolar transistor as set forth in claim 36, wherein the collector layer is comprised of n-doped InAs.
- 38. A heterojunction bipolar transistor as set forth in claim 37, wherein the collector layer is n-doped to approximately between 5×1015 and 5×1017.
- 39. A heterojunction bipolar transistor as set forth in claim 38, wherein the collector layer is approximately 1000 to 5000 Å thick.
- 40. A heterojunction bipolar transistor as set forth in claim 1, wherein the heterojunction bipolar transistor layer structure further comprises a subcollector layer formed between the collector layer and the substrate.
- 41. A heterojunction bipolar transistor as set forth in claim 40, wherein the subcollector layer is comprised of n-doped InAs.
- 42. A heterojunction bipolar transistor as set forth in claim 41, wherein the subcollector layer is n-doped to approximately between 2×1018 and 3×1019.
- 43. A heterojunction bipolar transistor as set forth in claim 42, wherein the subcollector layer is approximately 1000 Å to 5 μm thick.
- 44. A heterojunction bipolar transistor as set forth in claim 1, wherein a contact is formed on the emitter layer opposite the substrate.
- 45. A heterojunction bipolar transistor as set forth in claim 44, wherein the contact is formed of InAs.
- 46. A heterojunction bipolar transistor as set forth in claim 45, wherein the contact is n-doped to approximately between 2×1018 and 3×1019 cm−3.
- 47. A heterojunction bipolar transistor as set forth in claim 46, wherein the contact is approximately 200 to 2500 Å thick.
- 48. A heterojunction bipolar transistor as set forth in claim 1, wherein a spacer layer is formed between the base layer and the emitter layer.
- 49. A heterojunction bipolar transistor as set forth in claim 48, wherein the spacer layer is p-doped in a range from undoped to 5×1018.
- 50. A heterojunction bipolar transistor as set forth in claim 49, wherein the spacer layer is formed of InAs.
- 51. A heterojunction bipolar transistor as set forth in claim 50, wherein the spacer layer is approximately up to 100 Å thick
- 52. A heterojunction bipolar transistor as set forth in claim 1, wherein the substrate is comprised of a material selected from sapphire and a compound including indium and arsenic.
- 53. A heterojunction bipolar transistor as set forth in claim 52, wherein the substrate is comprised of sulfur-doped InAs.
- 54. A method for making a low base-emitter voltage heterojunction bipolar transistor comprising steps of providing a substrate and forming thereon thereon a heterojunction bipolar transistor layer structure lattice-matched to, and including an emitter layer including a strained, n-doped compound selected from a compound of indium arsenic and phosphorus and a compound of aluminum indium and arsenic.
- 55. A method as set forth in claim 54, wherein the indium arsenic phosphide compound is InAsxP1-x, where x is approximately between 0.7 and 1.0.
- 56. A method as set forth in claim 55, wherein the n-doping in the emitter layer is approximately between 5×1016 and 2×1018.
- 57. A method as set forth in claim 56, wherein the n-doping is substantially constant throughout the emitter layer.
- 58. A method as set forth in claim 57, wherein the emitter layer is approximately 200-500 Å thick.
PRIORITY CLAIM
[0001] This application claims the benefit of priority to U.S. Provisional Application No. 60/342,340, titled “Low VBE Heterojunction Bipolar Transistor,” filed Dec. 18, 2001.
Provisional Applications (1)
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Number |
Date |
Country |
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60342340 |
Dec 2001 |
US |