Embodiments of the invention relate to electronic systems, and more particularly to, electrical overstress protection for radio frequency signal interfaces.
Electronic systems can be exposed to electrical overstress events, or electrical signals of short duration having rapidly changing voltage and high power. Such electrical overstress events can occur during manufacturing, assembly, and/or end-user application environment. Electrical overstress events include, for example, electrical overstress (EOS), electromagnetic interference (EMI), and electrostatic discharge (ESD) arising from the abrupt release of charge from an object or person to an electronic system. The design constraints to safely handle these type of environmental overstress conditions are particularly complex in fin field-effect-transistor (FinFET) systems-on-a-chip (SoC) for high frequency applications.
Electrical overstress events can damage or destroy integrated circuits (ICs) by generating overvoltage conditions and high levels of power dissipation in relatively small areas of the ICs. High power dissipation can increase IC temperature, and can lead to numerous problems, such as gate oxide punch-through, junction damage, metal damage, and surface charge accumulation.
Low capacitance poly-bounded silicon controlled rectifiers (SCRs) are disclosed herein. In certain embodiments, an SCR includes an n-type well (NW) and a p-type well (PW) formed adjacent to one another in a substrate. The SCR further includes active regions including p-type active (P+) fin regions over the NW and connected to an anode terminal of the SCR, and n-type active (N+) fin regions over the PW and connected to a cathode terminal of the SCR. The SCR further includes polysilicon gate regions over the PW and NW that serve to separate the active regions while also improving the SCR's turn-on speed in response to fast overstress transients. Accordingly, the NW and PW of the SCR are bounded by polysilicon gate regions to achieve an enhancement in turn on speed. The polysilicon gate regions can be formed as gate fins as part of a FinFET process. In contrast, conventional SCRs do not include such polysilicon gate regions, but rather include shallow trench isolation (STI) regions to separate active regions formed in wells.
By including the polysilicon gate regions, performance parameters of the SCR are enhanced to provide an improvement in turn-on speed. For example, the P+ fin regions, the NW, and the PW form the emitter, base, and collector, respectively, of a PNP bipolar transistor of the SCR. Additionally, the polysilicon gate regions separate the active regions of the SCR and reduce a base width of the PNP bipolar transistor relative to a configuration in which STI is used for separating active regions. Providing a narrow base width directly impacts the base-transit time of the PNP bipolar transistor, resulting in faster protection. The SCR can be fabricated in a variety of advanced technologies, including CMOS FinFET process nodes of 16 nm or less.
In one aspect, an SCR protection structure for protecting an interface from an electrical overstress event is provided. The SCR protection structure includes an n-type well (NW) formed in a substrate, a p-type well (PW) formed in the substrate adjacent to the NW, a plurality of active regions including a first p-type active (P+) fin region over the NW and connected to an anode terminal and a first n-type active (N+) fin region over the PW and connected to a cathode terminal, and a plurality of polysilicon gate regions formed over the PW and NW. The plurality of polysilicon gate regions separate the plurality of active regions.
In another aspect, a semiconductor die is disclosed. The semiconductor die includes a plurality of pads including a signal pad and a ground pad, a circuit electrically connected to the signal pad, and an SCR including an anode terminal electrical connected to the signal pad and a cathode terminal electrically connected to the ground pad. The SCR includes an n-type well (NW) formed in a substrate, a p-type well (PW) formed in the substrate adjacent to the NW, a plurality of active regions including a first p-type active (P+) fin region over the NW and connected to the anode terminal and a first n-type active (N+) fin region over the PW and connected to the cathode terminal, and a plurality of polysilicon gate regions formed over the PW and NW. The plurality of polysilicon gate regions separate the plurality of active regions.
In another aspect, a method of forming an SCR protection structure is disclosed. The method includes forming an n-type well (NW) in a substrate, forming a p-type well (PW) formed in the substrate adjacent to the NW, and forming a plurality of active regions over the PW and the NW. The plurality of active regions include a first p-type active (P+) fin region over the NW and serving as an anode of the SCR, and a first n-type active (N+) fin region over the PW and serving as a cathode of the SCR. The method further includes separating the plurality of active regions by forming a plurality of polysilicon gate regions over the PW and NW.
The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to the drawings where like reference numerals may indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.
Certain electronic systems include overstress protection circuits to protect circuits and/or components from electrical overstress events. To help guarantee that an electronic system is reliable, manufacturers test such electronic systems under defined stress conditions, which can be described by standards set by various organizations, such as the Joint Electronic Device Engineering Council (JEDEC), the International Electrotechnical Commission (IEC), and the Automotive Engineering Council (AEC). The standards can cover a wide multitude of electrical overstress events, including electrical overstress (EOS) and/or electrostatic discharge (ESD).
A number of design challenges are present for protecting radio frequency (RF) circuits from electrical overstress events, particularly when such RF circuits are fabricated using FinFET processes. For example, the performance of RF circuits is degraded by capacitive loading and/or non-linearity arising from the presence of electrical overstress protection structures along RF signal paths. Furthermore, FinFET gate structures are easily damaged in response to electrical overstress conditions, thus rendering RF circuits fabricated with a FinFET process particularly susceptible to damage.
Conventional diode-based RF input-output (IO) protection poses significant limitations in achieving RF performance for advancing 5G communication requirements while preserving interface robustness.
For example, diode-based protection structures can suffer from slow reaction time and/or large voltage overshoot when subjected to fast ESD transients. Such large voltage overshoots can damage thin oxides being protected in advanced nm process nodes, such as complementary metal oxide semiconductor (CMOS) FinFET technologies of 16 nm or less.
Additionally, diode-based protection structures can have high trigger voltage that allows for large voltage build-up before activation. Moreover, diode-based protection structures can suffer from high capacitance and/or non-linearity that can degrade RF performance during normal operation when electrical overstress events are not present.
Low capacitance poly-bounded silicon controlled rectifiers (SCRs) are disclosed herein. In certain embodiments, an SCR includes an n-type well (NW) and a p-type well (PW) formed adjacent to one another in a substrate. The SCR further includes active regions including p-type active (P+) fin regions over the NW and connected to an anode terminal of the SCR, and n-type active (N+) fin regions over the PW and connected to a cathode terminal of the SCR. The SCR further includes polysilicon gate regions over the PW and NW that serve to separate the active regions while also improving the SCR's turn-on speed in response to fast overstress transients.
Accordingly, the NW and PW of the SCR are bounded by polysilicon gate regions to achieve an enhancement in turn on speed. The polysilicon gate regions can be formed as gate fins as part of a FinFET process. In contrast, conventional SCRs do not include such polysilicon gate regions, but rather include shallow trench isolation (STI) regions to separate active regions formed in wells.
By including the polysilicon gate regions, performance parameters of the SCR are enhanced to provide an improvement in turn-on speed. For example, the P+ fin regions, the NW, and the PW form the emitter, base, and collector, respectively, of a PNP bipolar transistor of the SCR. Additionally, the polysilicon gate regions separate the active regions of the SCR and reduce a base width of the PNP bipolar transistor relative to a configuration in which STI is used for separating active regions. Providing a narrow base width directly impacts the base-transit time of the PNP bipolar transistor, resulting in faster protection.
The SCR can be fabricated in a variety of advanced technologies, including CMOS FinFET process nodes of 16 nm or less.
The anode terminal and the cathode terminal of the SCR can be connected to provide protection to an RF circuit, which can be fabricated with the SCR on a common integrated circuit (IC). In certain implementations, the anode terminal connects to an RF signal pad of the IC while the cathode terminal connects to a ground signal pad of the IC. Thus, the SCR can be ground-referenced and used to protect an RF circuit formed on a common IC. In one example, the SCR protects an RF signal pad or port operating with asymmetrical signal swings in the range of +2.0V/−1.0V and having an operating frequency of up to about 20 GHz. However, the SCRs herein can be deployed in other configurations and operating scenarios.
In certain implementations, a voltage of the NW (corresponding to base voltage of the PNP) is left floating, which serves to reduce a trigger voltage of the SCR. In contrast, conventional diode and SCR protection structures suffer from a large trigger voltage that leads to a large voltage build-up and corresponding damage to circuitry being protected.
The NW and the PW of the SCR can be isolated from the substrate (for example, a p-type substrate) by deep n-type well (DNW). In certain implementations, rather than directly connected the DNW to a power supply voltage (for example, a highest available supply voltage with the aim of preventing parasitic diodes between the PW and DNW and/or between the substrate and DNW from becoming forward biased), a DNW bias circuit is included between the power supply voltage and DNW.
By including the DNW bias circuit, linearity performance is improved by blocking a potential path between the SCR's anode and the power supply voltage for RF signals. Furthermore, including the DNW bias circuit allows biasing of the DNW to a desired electrical potential to achieve low capacitance.
Accordingly, inclusion of the DNW bias circuit can achieve both improved linearity and reduced capacitance relatively to an implementation in which the DNW is directly connected to the highest available supply voltage.
The SCR includes a PNP bipolar transistor and an NPN bipolar transistor that are cross-coupled. For example, the P+ fin regions, the NW, and the PW form the emitter, base, and collector, respectively, of the PNP bipolar transistor, while the N+ fin regions, the PW, and the NW form the emitter, base, and collector, respectively, of the NPN bipolar transistor. Additionally, the collector of the NPN bipolar transistor is connected to the base of the PNP bipolar transistor, while the collector of the PNP bipolar transistor is connected to the base of the NPN bipolar transistor.
In certain implementations, a trigger circuit is included between the anode of the SCR and the base of the NPN bipolar transistor. Inclusion of the trigger circuit serves to further reduce the trigger voltage of the SCR by providing a displacement current to the base of the NPN bipolar transistor in response to an electrical overstress event. A tuning circuit (for example, a tuning resistor or other tuning element) can be included at the base of the NPN bipolar transistor to provide fine-tuned control over turn-on characteristics of the SCR. The trigger circuit can also serve to reduce DC leakage current of the SCR by biasing the base of the NPN bipolar transistor.
The SCRs disclosed herein serve to robustly protect RF circuits and/or other core devices with high speed, high voltage tolerance, high linearity, and/or low capacitance. The SCRs provide protection against electrical overstress events, which can include ESD events. Thus, the SCR provides robust protection from overstress conditions with little to no degradation to RF performance parameters such as second-order harmonic distortion (HD2), third-order harmonic distortion (HD3), third-order intermodulation distortion (IMD3), and/or third-order intercept point (IP3). Furthermore, the SCR behaves linearly with respect to capacitance and current characteristics such that presence of the protection device provides little to no interference with operation of the RF signal interface.
The teachings herein are applicable to SCRs that protect RF signal pads handling RF signals of a wide range of frequencies, including not only RF signals between 100 MHz and 7 GHZ, but also to higher frequencies, such as those in the X band (about 7 GHZ to 12 GHZ), the Ku band (about 12 GHZ to 18 GHZ), the K band (about 18 GHZ to 27 GHZ), the Ka band (about 27 GHz to 40 GHZ), the V band (about 40 GHz to 75 GHZ), and/or the W band (about 75 GHz to 110 GHz). Accordingly, the teachings herein are applicable to protecting a wide variety of RF circuits, including microwave circuits.
Furthermore, the RF circuits protected by the SCRs herein can be associated with a variety of communication standards, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Code Division Multiple Access (CDMA), wideband CDMA (W-CDMA), 3G, Long Term Evolution (LTE), 4G, and/or 5G, as well as other proprietary and non-proprietary communications standards.
In the illustrated embodiment, the SCR 2 is integrated with the RF circuit 1 on a common chip. The RF circuit 1 can include one or more of wide range of high frequency circuits for handling RF signals including, but not limited to, RF amplifiers, RF mixers, RF attenuators, RF filters, RF data converters, and/or other circuitry. Although shown as protecting an RF circuit, the SCRs herein can also be used to protect other types of circuits and/or components.
The RF circuit 1 is connected to the RF signal pad 3, which can correspond to an input signal pad, an output signal pad, or a bidirectional signal pad. The RF circuit 1 also receives a ground voltage from the ground pad 4 and a power supply voltage from the power supply voltage pad 5.
In the illustrated embodiment, the SCR 2 includes an anode connected to the RF signal pad 3 and a cathode connected to the ground pad 4. The SCR 2 is normally in a high impedance or off state, but transitions to a low impedance or on state in response to an electrical overstress event received between the RF signal path 3 and the ground pad 4. Thus, the SCR 2 serves as a ground referenced protection structure for providing protecting against ESD and/or other electrical overstress events received on the RF signal pad 3.
A traditional ground referenced diode-based ESD protection circuit causes high distortion due to stacking of multiple diodes to allow for large RF power handling. However, stacking multiple diodes leads to elevated distortion due to non-linearity and/or higher on-state resistance that degrades ESD performance.
In comparison, the SCR 2 of
Although
As shown in
The radio transmitter 40 illustrates another example application for the SCRs disclosed herein. Although
The FinFET 80 can provide a number of advantages relative to other transistor technologies. For example, the FinFET 80 facilitates higher level of integration and technology scaling. Moreover, the FinFET 80 can provide higher electrical control over a channel, more effective leakage suppression, enhanced driving current, and/or higher intrinsic gain for superior analog performance.
Thus, the FinFET 80 provides a number of advantages suitable for deployment in ICs for high-speed data conversion, wide bandwidth wireless communications, and/or other high-performance applications. For instance, a semiconductor chip implemented with FinFETs can be used to enable the high-speed applications discussed above with reference to
Accordingly, to aid in meeting bandwidth constraints for 5G or other high performance applications, it is desirable use FinFET technology to fabricate semiconductor dies (also referred to herein as integrated circuits or ICs) for high-performance transceivers and/or high-speed interfaces.
Although FinFET technology can provide a number of advantages, such FinFETs can operate with higher parasitic resistance, higher parasitic capacitance, and/or poorer thermal characteristics (for instance, higher thermal impedance and/or more self-heating) relative to transistors fabricated using a conventional complementary metal oxide semiconductor (CMOS) process. Such characteristics can render FinFETs susceptible to damage from electrical overstress.
The teachings herein can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, thereby helping to meet tight design windows for robustness. For example, in certain embodiments herein, high voltage tolerant FinFET SCRs are provided for handling high stress current and high RF power handling capability, while providing low capacitance to allow wide bandwidth operation.
With reference to
The SCR protection structures herein can include various wells (for instance, n-type well (NW) and/or p-type well (PW) regions), various active regions (for instance, n-type active (N+) and/or p-type active (P+) regions), gates, and/or other structures. As persons of ordinary skill in the art will appreciate, P+ regions have a higher doping concentration than the PWs. Additionally, N+ regions have a higher doping concentration than NWs. Persons having ordinary skill in the art will appreciate various concentrations of dopants in the regions.
It should be appreciated that because regions within a semiconductor device are defined by doping different parts of a semiconductor material with differing impurities or differing concentrations of impurities, discrete physical boundaries between different regions may not actually exist in the completed device but instead regions may transition from one to another. Some boundaries as shown in the figures of this type and are illustrated as abrupt structures merely for the assistance of the reader. As persons having ordinary skill in the art will appreciate, p-type regions can include a p-type semiconductor material, such as boron, as a dopant. Furthermore, n-type regions can include an n-type semiconductor material, such as phosphorous, as a dopant.
With continuing reference to
Various active fin regions have been formed over the NW 101 and/or PW 102. In particular, a first group of P+ fin regions 111a are formed over the NW 101, a second group of P+ fin regions 111b are formed over the PW 102, and a third group of P+ fin regions 111c are formed over the NW 101. Additionally, a first group of N+ fin regions 112a are formed over the NW 101 and the PW 102, and extend over a boundary between the NW 101 and the PW 102. Furthermore, a second group of N+ fin regions 112b are formed over the PW 102 and a third group of N+ fin regions 112c are formed over the PW 102.
In the illustrated embodiment, each group of fin regions includes four fins. However, each group of fin regions can include more or fewer fins. For example, the number of fins can be selected to control a current handling capability of the device.
With continuing reference to
The FinFET SCR 120 includes an NPN bipolar transistor having an emitter, a base, and a collector corresponding to the N+ fin regions 112b/112c, the PW 102, and the NW 101, respectively. Additionally, the FinFET SCR 120 includes a PNP bipolar transistor having an emitter, a base, and a collector corresponding to the P+ fin regions 111a/111c, the NW 101, and the PW 102, respectively.
With continuing reference to
As shown in
Inclusion of the polysilicon gate regions 115a-115g improve the SCR's turn-on speed in response to fast overstress transients. Thus, the NW 101 and the PW 102 of the FinFET SCR 120 are bounded by the polysilicon gate regions 115a-115g to achieve an enhancement in turn on speed. For example, the polysilicon gate regions 115a-115g separate the active fin regions of the SCR and reduce a base width of the SCR's PNP bipolar transistor relative to a configuration in which STI is used for separating active regions. Providing a narrow base width directly impacts the base-transit time of the PNP bipolar transistor, resulting in faster protection. The polysilicon gate regions 115a-115g also serve to introduce surface breakdown to lower intrinsic avalanching voltage further downward, thereby lowering trigger voltage.
The FinFET SCR 120 can be fabricated in a variety of advanced technologies, including CMOS FinFET process nodes of 16 nm or less.
In certain implementations, a voltage of the NW 101 (corresponding to base voltage of the PNP) is left floating, which serves to reduce a trigger voltage of the FinFET SCR 120. In contrast, conventional diode and SCR protection structures suffer from a large trigger voltage that leads to a large voltage build-up and corresponding damage to circuitry being protected.
In the illustrated embodiment, the FinFET SCR 120 includes a metal region 116 over a portion of N+ fin regions 112a as well as over a boundary between the NW 101 and the PW 102. Furthermore, the FinFET SCR 120 includes a metal region 117 formed over a portion of the second polysilicon gate region 115b. Inclusion of the metal region 116 and/or the metal region 117 aids in providing fine-tune control over the trigger voltage of the FinFET SCR 120.
The SCR 220 of
As shown in
With continuing reference to
Furthermore, in certain implementations, the poly bias circuit 207 can control the voltage levels of the polysilicon gate regions to different voltage levels. For instance, when the poly bias circuit 207 is used to bias the polysilicon gate regions 115a-115g of
In the illustrated embodiment, the trigger circuit 206 is connected between the IO terminal 211 and the base of the NPN bipolar transistor QN1. The trigger circuit 206 serves to reduce the trigger voltage of the SCR 220 by providing a displacement current to the base of the NPN bipolar transistor QN1 in response to an electrical overstress event received on the IO terminal 211. The trigger circuit 206 also serves to reduce DC leakage current of the SCR 220 by biasing the base of the NPN bipolar transistor QN1. The tuning circuit 208 (for example, a tuning resistor or other tuning element) is also included at the base of the NPN bipolar transistor QN1 to provide fine-tuned control over turn-on characteristics of the SCR 220. The tuning circuit 208 receives the displacement current from the trigger circuit 206, and thus operates in combination with the trigger circuit 206 to aid in activating the thyristor structure 201 in response to an electrical overstress event.
The DNW bias circuit 205 improves linearity performance by blocking a potential path between the IO terminal 211 and the power supply voltage terminal 214 for RF signals. Furthermore, including the DNW bias circuit 205 allows biasing of the DNW 213 to a desired electrical potential to achieve low capacitance.
The SCR 221 of
As shown in
ICs can include a power supply clamp between a power supply pad and a ground pad (for example, between the power supply pad 5 and the ground pad 4 of
In the illustrated embodiment, the trigger circuit 282 is included between the DNW 213 and the power supply terminal 214. In response to an overvoltage condition received between the IO terminal 211 and the ground terminal 212, a current flows through the forward-biased emitter-to-base junction of the PNP bipolar transistor QP1 and through the trigger circuit 282. This in turn leads to voltage build-up that triggers activation of the power clamp 281. Furthermore, once activated, the power supply clamp 281 provides an additional discharge path for discharging the overvoltage condition.
Accordingly, the SCR 229 of
In the illustrated embodiment, the trigger circuit 282 includes a first diode 283 and a second diode 284 connected in series between the DNW 213 and the power supply voltage terminal 214. By implementing the trigger circuit 282 in this manner, current conducts through the trigger circuit 282 in response to overvoltage conditions that raise the DNW 213 by about the sum of the forward voltage of the diodes 283/284. However, other implementations are possible. For instance, other numbers of series diodes can be included to tune the activation voltage of the trigger circuit 282.
The SCR 230 of
With continuing reference to
The thyristor structure 222 of
The SCR 240 of
The DNW bias circuit 205 improves linearity performance by blocking a potential path between the IO terminal 211 and the power supply voltage 213 for RF signals. Furthermore, including the DNW bias circuit 205 allows biasing of the DNW to a desired electrical potential to achieve low capacitance. Accordingly, inclusion of the DNW bias circuit 205 can achieve both improved linearity and reduced capacitance relatively to an implementation in which the DNW is directly connected to the highest available supply voltage.
The SCR 280 of
In the illustrated embodiment, the trigger circuit 271 includes a trigger NFET 272, a trigger capacitor 273, a trigger resistor 274, a first diode 275, and a second diode 276. The drain of the trigger NFET 272 is connected to the IO terminal 211. Additionally, the trigger capacitor 273 is connected between the drain of the trigger NFET 272 and the gate of the trigger NFET 272. Furthermore, the trigger resistor 274 is connected between the gate of the trigger NFET 272 and the source of the trigger NFET 272. The first diode 275 and the second diode 276 are connected in series (end to end from anode to cathode) between the source of the trigger NFET 272 and the base of the NPN bipolar transistor QN1.
In response to an electrical overstress event received on the IO terminal 211, the trigger circuit 271 generates a displacement current that flows through the tuning resistor RTUNE to increase the base-to-emitter voltage of the NPN bipolar transistor QN1 and turn on the thyristor structure 222.
In the illustrated embodiment, the trigger resistor 274 and the trigger capacitor 273 form a resistor-capacitor (RC) network (or RC-based trigger circuit) that helps reduce the quasi-static trigger voltage of the SCR. Furthermore, the RC-based trigger circuit significantly reduces the DC leakage, and exhibits high insensitivity to dV/dt triggering.
The inclusion of one or more diodes (for example, the diodes 275/276) help to lower the capacitive loading of the trigger circuitry on the IO terminal 211.
As shown in
For example, the forward protection SCR 301 activates to provide protection against positive polarity electrical overstress that causes the voltage of the signal terminal 212 to increase relative to the voltage of the ground terminal 212. The forward protection SCR 301 has a forward trigger voltage and a forward holding voltage that controls a forward protection characteristic of the bidirectional protection structure 310.
With continuing reference to
In certain implementations herein, the forward protection SCR 301 and the reverse protection structure 302 are implemented in a common layout with a DNW to enhance integration.
With reference to
As shown in
Various connections in metallization are shown, including connections between the second P+ region 315b and the first N+ region 316a and between the third P+ region 315c and the second N+ region 316b. Connections to the signal terminal 211, the ground terminal 212, and the DNW terminal 213 are also shown.
The circuit diagram of
With continuing reference to
The PNP bipolar transistor 325 and the NPN bipolar transistor 326 are cross-coupled to form a reverse protection SCR that operates in parallel with the series combination of diodes 321-323 to provide reverse protection. The PNP bipolar transistor 325 includes an emitter associated with the first P+ region 315a, a base associated with the DNW 311, and a collector associated with the third PW 312c. Additionally, the NPN bipolar transistor 326 includes an emitter associated with the third N+ region 316c, a base associated with the third PW 312c, and a collector associated with the DNW 311.
When activated in response to negative polarity electrical overstress, the combination of the series diodes 321-323 and reverse protection SCR 325/326 operate to provide electrical overstress protection. The presence of two parallel protection paths provides lower on-state resistance and more robust protection relative to a configuration with a single path.
Although one embodiment of reverse protection is depicted in
Devices employing the above described schemes can be implemented into various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, communication infrastructure applications, etc. Further, the electronic device can include unfinished products, including those for communication, industrial, medical and automotive applications.
The foregoing description may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and/or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.
Although the claims presented here are in single dependency format for filing at the USPTO, it is to be understood that any claim may depend on any preceding claim of the same type except when that is clearly not technically feasible.