Low cost DSSS communication system

Description

TECHNICAL FIELD

This invention relates to techniques and apparatus for wireless communication using Direct Sequence Spread Spectrum (DSSS) techniques.

BACKGROUND OF THE INVENTION

In the transmitter of a direct-sequence spread spectrum communication systems, a carrier waveform is modulated by a data sequence x(n) and by a spreading sequence or code sequence C(n). The code sequence may be a pseudo-noise (PN) sequence, such as a maximum length sequence (m-sequence). The PN sequence is used to reduce the sensitivity of the communication channel to noise, reduce the power spectral density of the signal and to allow multiple communication channels to operate simultaneously. In the latter case, each channel is assigned its own PN code sequence, so the technique is called code-division multiple access (CDMA).

In the receiver the data signal is recovered by removing the carrier wave and then correlating the received signal with the PN code sequence used for transmission. Decorrelation requires a large amount of computation to align the received signal with the PN code sequence, and so adds to the cost of the receiver.

In view of the preceding remarks, it is clear that there is an unmet need in the art for a receiver that avoids the high cost of performing a correlation between the received signal and a PN code sequence.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however, both as to organization and method of operation, together with objects and advantages thereof, may be best understood by reference to the following detailed description of the invention, which describes certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings in which:

FIG. 1

is a diagrammatic representation of the generation of spreading codes in accordance with an embodiment of the present invention.

FIGS. 2A and 2B

are diagrammatic representations of embodiments of a transmitter of the present invention.

FIG. 3

is a diagrammatic representation of a digital receiver of the present invention.

FIG. 4

is a diagrammatic representation of an analog receiver of the present invention.

FIG. 5

is a diagrammatic representation of a transmitter of a further embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

While this invention is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail specific embodiments, with the understanding that the present disclosure is to be considered as an example of the principles of the invention and not intended to limit the invention to the specific embodiments shown and described. In the description below, like reference numerals are used to describe the same, similar or corresponding parts in the several views of the drawings.

In direct sequence spread spectrum (DSSS) communication, a pseudo-noise (PN) code sequence is used to modulate a carrier waveform and thereby spread the spectrum of the transmitted signal. A PN code sequence of length N is denoted by C=(C

1

, C

2

, C

3

, . . . , C

N

), where C

i

has the value 1 or −1. The PN code sequence preferably has the property that the correlation of the sequence with a cyclically time-shifted version of itself has an absolute value of one or zero, whereas the correlation of the code sequence with itself has the value N.

In a first embodiment of the present invention, the two code sequences of length 2N are generated by interleaving groups of M elements from the sequences C and ±C. The two sequences are

C

a

(2

jM+i

)=

C

(

jM+i

)C

a

((2

j

+1)

M+i

)=

C

(

jM+i

)

and

C

b

(2

jM+i

)=

C

(

jM+i

)

C

b

((2

j

+1)

M+i

)=−

C

(

jM+i

)

where j=0, . . . , N/M −1 and i=1, . . . , M.

For example, when M=1, the two code sequences of length 2N are generated as C

a

=(C

1

, C

1

, C

2

, C

2

, C

3

, C

3

, . . . , C

N

, C

N

) and C

b

=(C

1

, −C

1

, C

2

, −C

2

, C

3

, −C

3

, . . . , C

N

, −C

N

). These sequences may be generated, as in

FIG. 1

for example, by interleaving the code sequence C with the code sequence C or −C. The transmitted signal is generated as shown in FIG.

2

A. The data signal x=(a

1

, a

2

, a

3

, . . . )

202

is passed to selector

204

. If the current signal a

i

is equal to 1 it is passed to multiplier

206

, where it is multiplied by the code sequence C

a

. If the current signal a

i

is equal to −1 it is passed to multiplier

208

, where it is multiplied by the code sequence C

b

. The outputs from the multipliers

206

and

208

are added at summer

210

, to produce a modulation signal

212

. The modulation signal

212

is passed to multiplier

214

, whereat multiplies (modulates) the carrier signal cos(ω

c

t)

216

. Here, ω

c

is the carrier frequency in radians per second, and t is the time in seconds. The resulting signal

218

is amplified and passed to antenna

220

for transmission. One element (chip) of the code sequence is generated every T

c

seconds, so the chip rate is R

c

=1/T

c

. The bit-rate is equal to R

c

/(2N), since 2N chips are used for each bit of information.

FIG. 2B

shows a further transmitter of the present invention. A PN code sequence C=(C

1

, C

2

, C

3

, . . . , C

N

) is supplied to interpolator or up-sampler

230

, that inserts zeros between the elements of the code sequence, yielding the sequence C

int

=(C

1

, 0, C

2

, 0, C

3

, 0, . . . , 0, C

N

, 0). The sequence is delayed by one chip period in delay element

232

to give the sequence (0, C

1

, 0, C

2

, 0, C

3

, 0, . . . , 0, C

N

). The delayed signal is multiplied by the data value a

i

at

234

and the result is added at

236

to the interpolated sequence to give the sequence (C

1

, a

i

C

1

, C

2

, a

i

C

2

, C

3

, a

i

C

3

, . . . , C

N

, a

i

C

N

). The gives the sequence C

a

when a

l

=1, and the sequence C

b

when a

l

=−1. The sequence is then modulated by the carrier signal and transmitted as usual.

The corresponding receiver is shown in FIG.

3

. Referring to

FIG. 3

, the incoming radio signal is received by antenna

302

. The received signal is multiplied by the signal cos((ω

c

t) in multiplier

304

to produce an in-phase signal component. The received signal is multiplied by the signal sin(ω

c

t) in multiplier

306

to produce a quadrature signal component. The in-phase and quadrature signal components are filtered in match filter

308

, which has an impulse response matched to the transmitted pulse shape, and the resulting filtered signals are sampled by analog-to-digital converter (ADC)

310

to produce in-phase and quadrature data sequences I and Q. The sampling rate of the ADC is preferably greater than the chip rate, and is denoted by K.R

c

, where K is bigger than or equal to 1. The n

th

samples of the sequences are denoted by the complex baseband signal S(n)=l(n)+iQ(n)=A(n)e

−θ

, where i=−1 and θ is an unknown phase offset. The complex baseband signal S(n) is passed to complex delay unit

312

, where the signal is delayed by an amount MT

c

, where T

c

is the chip period and M is the number of consecutive samples taken from each sequence during interleaving in the transmitter. The output from the complex delay unit is S(n−MK). In the sequel we consider the case M=1 without loss of generality. The complex conjugate of the signal is calculated at

314

, to give the signal

S

*(

n−k

)=

I

(

n−K

)−

iQ

(

n−K

)=

A

(

n−K

)·

e

iθ

.

At multiplier

316

, the signals S(n) and S*(n−K) are multiplied to give the complex product signal

U

(

n

)=

A

(

n

)

e

−iθ

·A

(

n−K

)e

iθ

=A

(

n

)·

A

(

n−K

).

At block

318

, the real part is taken to give V(n)=A(n)A(n−K). This removes any imaginary part introduced by a small mismatch between the carrier frequency in the transmitter and the receiver. The signal V(n) is then integrated at

320

and the result passed to decision logic

322

.

By way of explanation, we consider the case K=1. When a bit

1

is transmitted, the current data value is a

i

=1, the previous data value is a

i−1

. The received signal is I=C

a

=(C

1

, C

1

, C

2

, C

2

, C

3

, C

3

, . . . , C

N

, C

N

), the delayed version of I is I′=(a

i−1

C

N

, C

1

, C

1

, C

2

, C

2

, C

3

, C

3

, . . . , C

N−1

, C

N

), and the product of I with I′ is V=(a

i−1

C

N

C

1

, C

1

C

1

, C

1

C

2

, C

2

C

2

, C

2

C

3

, C

3

C

3

, C

3

C

4

, . . . , C

N−1

C

N−1

, C

N−1

C

N

, C

N

C

N

)=(a

i−1

C

N

C

1

, 1, C

1

C

2

, 1, C

2

C

3

, 1, C

3

C

4

, . . . , 1, C

N−1

C

N

, 1)

The integration over one cycle gives

N+a

i−1

C

N

C

1

+C

1

C

2

+C

2

C

3

, +C

3

C

4

+ . . . +C

N−1

C

N

=N

+(a

i−1

−1)C

N

C

1

+ε

where ε=C

1

C

2

+C

2

C

3

, +C

3

C

4

+ . . . +C

N−1

C

N

+C

N

C

1

=−1 is the cyclic correlation of the PN code sequence with shift one. By carefully picking the code, we can make the product C

N

C

1

=−1. Hence the value of the integration is N−a

i−1

, which equals to N−1 or N+1 depending on the previous bit value a

i−1

.

When the bit −1 is transmitted, the current data value is a

i

=−1, the previous data value is a

i−1

. The received signal is C

b

=(C

1

, −C

1

, C

2

, −C

2

, C

3

, −C

3

, . . . , −C

N

, C

N

), the delayed version of I is I′=(a

i−1

C

N

, C

1

, −C

1

, C

2

, −C

2

, C

3

, −C

3

, . . . , −C

N−1

, C

N

), The product of I with the delayed signal is

V=(a

i−1

C

N

C

1

, −C

1

C

1

, −C

1

C

2

, −C

2

C

2

, −C

2

C

3

, −C

3

C

3

, −C

3

C

4

, . . . , −C

N−1

C

N

, −C

N

C

N

)=(a

i−1

C

N

C

1

, −1, −C

1

C

2

, −1, −C

2

C

3

, −1, −C

3

C

4

, . . . , −C

N

C

N−1

,−1),

and the integration over one cycle gives

−N+a

i−1

C

N

C

1

−C

1

C

2

−C

2

C

3

, −C

3

C

4

− . . . −C

N−1

C

N

=−N+(a

i−1

+1) C

N

C

1

−ε,

where ε=C

1

C

2

+C

2

C

3

, +C

3

C

4

+ . . . +C

N−1

C

N

+C

N

C

1

=−1 is the cyclic correlation of the PN code sequence with shift one. As discussed above, the product C

N

C

1

=−1. Hence the value of the integration is −N−a

i−1

, which equals to −N−1or −N+1 depending on the previous bit value a

i−1

.

The value of N is large (typically

127

), SO the decision logic simply compares the integration value to zero. A positive value is interpreted as a +1 bit, while a negative value is interpreted as a −1 bit. Hence the signal has been decoded without the use of a correlation. Further, the differential decoding is performed chip-by-chip, so the receiver is very robust to drift in the carrier frequency. This further reduces cost by avoiding the need for a very accurate timer or clock source. For example, if the frequency difference between the transmitter and receiver is Δω, the receiver signal after demodulation is

S

(

t

)=

A

(

t

)exp(−iΔω

t

+6),

where θ is a phase offset. The product signal is

U

(

t

)=

S

(

t

)

{overscore (S)}

(

t−T

c

)=

A

(

t

)

A

(

t−T

c

)exp(−

iΔωT

c

),

and the real part is

V

(

t

)=

A

(

t

)

A

(

t−T

c

)cos(ΔωT

c

).

Thus, when the product ΔωT

c

is small, there is only a very small amplitude change. The computation can be performed using analog or digital hardware or using software running on a computer.

FIG. 4

shows an embodiment of a receiver of the invention using an analog system. In this embodiment the ADC is omitted. The discrete integration element

320

in

FIG. 3

is replaced by analog integrator

324

in FIG.

4

. The integrator is periodically reset to zero.

A further embodiment of a transmitter is shown in FIG.

5

. In this embodiment −1 bits are transmitted as before, but for +1 bits, the PN code sequence C is used rather than C

a

. Since C is of length N while C

a

is of length 2N, the data rate of this embodiment is higher. The receiver is as described above.

When a bit

1

is transmitted, the received signal is I=C=(C

1

, C

2

, C

3

, . . . , C

N

), and the real part of the product with the delayed signal is

V=(a

i−1

C

N

C

1

, C

1

C

2

, C

2

C

3

, C

3

C

4

, . . . , C

N−1

C

N

),

where a

i−1

is the previous bit data value.

The integration over one cycle gives

C

1

C

2

+C

2

C

3

, +C

3

C

4

+ . . . +C

N−1

C

N

+a

i−1

C

N

C

1

=ε+(a

i−1

−1)C

N

C

1

where, as before, ε=C

1

C

2

+C

2

C

3

, +C

3

C

4

+. . . +C

N

C

N−1

+C

N

C

1

=−1 is the cyclic correlation of the PN code sequence with shift one. By carefully picking the code, we can make the product C

N

C

1

=−1. Hence the value of the integration is a

i−1

, which equals to −1 or +1 depending on the previous bit value a

i−1

.

When the bit −1 is transmitted, the current data value is a

i

=−1, the previous data value is a

i−1

. The received signal is C

b

=(C

1

, −C

1

, C

2

, −C

2

, C

3

, −C

3

, . . . , C

N

, −C

N

), the delayed version of I is I′=(a

i−1

C

N

, C

1

, −C

1

, C

2

, −C

2

, C

3

, −C

3

, . . . , −C

N−1

, C

N

), The product of I with the delayed signal is

V=(a

i−1

C

N

C

1

, −C

1

C

1

, −C

1

C

2

, −C

2

C

2

, −C

2

C

3

, −C

3

C

3

, −C

3

C

4

, . . . , −C

N−1

C

N

, −C

N

C

N

)=(a

i−1

C

N

C

1

, −1, −C

1

C

2

, −1, −C

2

C

3

, −1, −C

3

C

4

, . . . , −C

N

C

N−1

,−1),

and the integration over one cycle gives

−N+a

i−1

C

N

C

1

−C

1

C

2

−C

2

C

3

, −C

3

C

4

− . . . −C

N−1

C

N

=−N+(a

i−1

+1) C

N

C

1

−ε,

where ε=C

1

C

2

+C

2

C

3

, +C

3

C

4

+ . . . +C

N−1

C

N

+C

N

C

1

=−1 is the cyclic correlation of the PN code sequence with shift one. As discussed above, the product C

N

C

1

=−1. Hence the value of the integration is −N−a

i−1

, which equals to −N−1 or −N+1 depending on the previous bit value a

i−1

.

The value of N is large (typically 127), so the decision logic simply compares the integration value to −N/2. A value greater than −N/2 is interpreted as a+1 bit, while a value less than −N/2 is interpreted as a −1 bit. Hence the signal has been decoded without the use of a correlation.

The first embodiment has better sensitivity than this embodiment, i.e. it is less sensitive to noise, but this embodiment has a higher data rate.

Those of ordinary skill in the art will recognize that the present invention has been described in terms of exemplary embodiments based upon use of an ideal rectangular pulse. However, the invention should not be so limited, since the present invention could be implemented using other pulse shapes. Similarly, the present invention may be implemented using general-purpose computers, microprocessor based computers, digital signal processors, microcontrollers, dedicated processors, custom circuits, ASICS and/or dedicated hard-wired logic.

Many other variations will also be evident to those of ordinary skill in the art. The embodiment disclosed can be embodied in a DSSS receiver for a location system, for instance, but it is understood that the method and apparatus of the present invention is equally applicable to all other systems using DSSS techniques.

While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications, permutations and variations will become apparent to those of ordinary skill in the art in light of the foregoing description. Accordingly, it is intended that the present invention embrace all such alternatives, modifications and variations as fall within the scope of the appended claims.

Claims

1. A method for recovering a data value from a received signal in a direct sequence spread spectrum receiver, said received signal having a chip period Tc, a bit period Tb and being modulated by first code sequence Ca or second code sequence Cb generated by interleaving groups of M chips from a pseudo-noise sequence C=(C1, C2, C3, . . . , CN) of length N with elements Ci=±1, said first code sequence Ca having elementsCa(2jM+i)=C(jM+i)Ca((2j+1)M+i)=C(jM+i) and said second code sequence Cb having elementsCb(2jM+i)=C(jM+i)Cb((2j+1)M+i)=−C(jM+i) where j=0, . . . , N/M −1 and i=1, . . . , M; said method comprising:transforming said received signal to complex baseband signal having in-phase and quadrature components; delaying said complex baseband signal by a time MTc equal to M chip periods to obtain a complex delayed signal; multiplying the complex baseband signal by the conjugate of the complex delayed signal to obtain a complex product signal; integrating the real part of said complex product signal over the bit period Tb to obtain an integrated value; and determining said data value from said integrated value.
2. A method as in claim 1, wherein M=1, Ca=(C1, C1, C2, C2, C3, C3, . . . , CN, CN) and Cb=(C1, −C1, C2, −C2, C3, −C3, . . . , CN, −CN).
3. A method as in claim 1, wherein said determining comprises comparing said integrated value to a predetermined threshold value.
4. A method as in claim 1, further comprising sampling said baseband complex signal using an analog-to-digital converter.
5. A direct sequence spread spectrum receiver for recovering a data value from a received signal in a direct sequence spread spectrum receiver, said received signal having a chip period Tc, a bit period Tb and being modulated by first code sequence Ca or second code sequence Cb generated by interleaving groups of M chips from a pseudo-noise sequence C=(C1, C2, C3, . . . , CN) of length N with elements Ci=±1, said second code sequence Cb having elementsCb(2jM+i)=C(jM+i)Cb((2j+1)M+i)=−C(jM+i) where j=0, . . . , N/M −1 and i=1, . . . , M; said receiver comprising:a converter operable to transform said received signal to a complex baseband signal having in-phase and quadrature components; a delay element operable to delay said complex baseband signal by a time MTc, equal to M chip periods, to obtain a complex delayed signal; a multiplier operable to multiply the complex baseband signal by the conjugate of the complex delayed signal to obtain a complex product signal; an integrator operable to integrate the real part of said complex product signal over the bit period Tb to obtain an integrated value; and a decision logic circuit operable to determine said data value from said integrated value.
6. A direct sequence spread spectrum receiver as in claim 5, wherein said first code sequence Ca has length 2N and elementsCa(2jM+i)=C(jM+i)Ca((2j+1)M+i)=C(jM+i)
7. A direct sequence spread spectrum receiver as in claim 5, wherein said first code sequence Ca is C and has length N.

US Referenced Citations (5)

Number	Name	Date	Kind
5222075	Richley	Jun 1993	A
5412620	Cafarella et al.	May 1995	A
5559828	Armstrong et al.	Sep 1996	A
5610940	Durrant et al.	Mar 1997	A
6111911	Sanderford, Jr. et al.	Aug 2000	A

Low cost DSSS communication system

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

Field of Search

US

International Classifications

Abstract

Description

Claims

US Referenced Citations (5)