This invention relates to techniques and apparatus for wireless communication using Direct Sequence Spread Spectrum (DSSS) techniques.
In the transmitter of a direct-sequence spread spectrum communication systems, a carrier waveform is modulated by a data sequence x(n) and by a spreading sequence or code sequence C(n). The code sequence may be a pseudo-noise (PN) sequence, such as a maximum length sequence (m-sequence). The PN sequence is used to reduce the sensitivity of the communication channel to noise, reduce the power spectral density of the signal and to allow multiple communication channels to operate simultaneously. In the latter case, each channel is assigned its own PN code sequence, so the technique is called code-division multiple access (CDMA).
In the receiver the data signal is recovered by removing the carrier wave and then correlating the received signal with the PN code sequence used for transmission. Decorrelation requires a large amount of computation to align the received signal with the PN code sequence, and so adds to the cost of the receiver.
In view of the preceding remarks, it is clear that there is an unmet need in the art for a receiver that avoids the high cost of performing a correlation between the received signal and a PN code sequence.
The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however, both as to organization and method of operation, together with objects and advantages thereof, may be best understood by reference to the following detailed description of the invention, which describes certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings in which:
While this invention is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail specific embodiments, with the understanding that the present disclosure is to be considered as an example of the principles of the invention and not intended to limit the invention to the specific embodiments shown and described. In the description below, like reference numerals are used to describe the same, similar or corresponding parts in the several views of the drawings.
In direct sequence spread spectrum (DSSS) communication, a pseudo-noise (PN) code sequence is used to modulate a carrier waveform and thereby spread the spectrum of the transmitted signal. A PN code sequence of length N is denoted by C=(C1, C2, C3, . . . ,CN), where Ci has the value 1 or −1. The PN code sequence preferably has the property that the correlation of the sequence with a cyclically time-shifted version of itself has an absolute value of one or zero, whereas the correlation of the code sequence with itself has the value N.
In a first embodiment of the present invention, the two code sequences of length 2N are generated by interleaving groups of M elements from the sequences C and ±C. The two sequences are
Ca(2jM+i)=C(jM+i) Ca((2j+1)M+i)=C(jM+i)
and
Cb(2jM+i)=C(jM+i) Cb((2j+1)M+i)=−C(jM+i)
where j=0, . . . , N/M−1 and i=1, . . . , M.
For example, when M=1, the two code sequences of length 2N are generated as Ca=(C1, C1, C2, C2, C3, C3, . . . , CN, CN) and Cb=(C1, −C1, C2, −C2, C3, −C3, . . . , CN, −CN). These sequences may be generated, as in
The corresponding receiver is shown in
S*(n−k)=I(n−K)−iQ(n−K)=A(n−K).eiθ.
At multiplier 316, the signals S(n) and S*(n−K) are multiplied to give the complex product signal
U(n)=A(n)e−iθ.A(n−K)eiθ=A(n).A(n−K).
At block 318, the real part is taken to give V(n)=A(n)A(n−K). This removes any imaginary part introduced by a small mismatch between the carrier frequency in the transmitter and the receiver. The signal V(n) is then integrated at 320 and the result passed to decision logic 322.
By way of explanation, we consider the case K=1. When a bit 1 is transmitted, the current data value is ai=1, the previous data value is ai−1. The received signal is I=Ca=(C1, C1, C2, C2, C3, C3, . . . , CN, CN), the delayed version of I is I′=(ai−1CN, C1, C1, C2, C2, C3, C3, . . . , CN−1, CN), and the product of I with I′ is
The integration over one cycle gives
N+ai−1CNC1+C1C2+C2C3, +C3C4+ . . . +CN−1CN=N+(ai−1−1)CNC1+ε
where ε=C1C2+C2C3, +C3C4+ . . . +CN−1CN+CNC1=−1 is the cyclic correlation of the PN code sequence with shift one. By carefully picking the code, we can make the product CNC1=−1. Hence the value of the integration is N−ai−1, which equals to N−1 or N+1 depending on the previous bit value ai−1.
When the bit −1 is transmitted, the current data value is ai=−1, the previous data value is ai−1. The received signal is Cb=(C1, −C1, C2, −C2, C3, −C3, . . . , CN, −CN), the delayed version of I is I′=(ai−1CN, C1, −C1, C2, −C2, C3, −C3, . . . , −CN−1, CN),
The product of I with the delayed signal is
and the integration over one cycle gives
−N+ai−1CNC1−C1C2−C2C3, −C3C4− . . . −CN−1CN=−N+(ai−1+1) CNC1−ε,
where ε=C1C2+C2C3, +C3C4+ . . . +CN−1CN+CNC1=−1 is the cyclic correlation of the PN code sequence with shift one. As discussed above, the product CNC1=−1. Hence the value of the integration is −N−ai−1, which equals to −N−1 or −N+1 depending on the previous bit value ai−1.
The value of N is large (typically 127), so the decision logic simply compares the integration value to zero. A positive value is interpreted as a +1 bit, while a negative value is interpreted as a −1 bit. Hence the signal has been decoded without the use of a correlation. Further, the differential decoding is performed chip-by-chip, so the receiver is very robust to drift in the carrier frequency. This further reduces cost by avoiding the need for a very accurate timer or clock source. For example, if the frequency difference between the transmitter and receiver is Δω, the receiver signal after demodulation is
S(t)=A(t)exp(−iΔωt+∂),
where θ is a phase offset. The product signal is
U(t)=S(t){overscore (S)}(t−Tc)=A(t)A(t−Tc)exp(−iΔωTc),
and the real part is
V(t)=A(t)A(t−Tc)cos(ΔωTc).
Thus, when the product ΔωTc is small, there is only a very small amplitude change. The computation can be performed using analog or digital hardware or using software running on a computer.
A further embodiment of a transmitter is shown in
When a bit 1 is transmitted, the received signal is I=C=(C1, C2, C3, . . . , CN), and the real part of the product with the delayed signal is
V=(ai−1CNC1, C1C2, C2C3, C3C4, . . . , CN−1CN),
where ai−1 is the previous bit data value.
The integration over one cycle gives
C1C2+C2C3, +C3C4+ . . . +CN−1CN+ai−1CNC1=ε+(ai−1−1)CNC1
where, as before, ε=C1C2+C2C3, +C3C4+ . . . +CNCN−1+CNC1=−1 is the cyclic correlation of the PN code sequence with shift one. By carefully picking the code, we can make the product CNC1=−1. Hence the value of the integration is −ai−1, which equals to −1 or +1 depending on the previous bit value ai−1.
When the bit −1 is transmitted, the current data value is ai=−1, the previous data value is ai−1. The received signal is Cb=(C1, −C1, C2, −C2, C3, −C3, . . . , CN, −CN), the delayed version of I is I′=(ai−1CN, C1, −C1, C2, −C2, C3, −C3, . . . , −CN−1, CN),
The product of I with the delayed signal is
and the integration over one cycle gives
−N+ai−1CNC1−C1C2−C2C3,−C3C4− . . . −CN−1CN=−N+(ai−1+1)CNC1−ε,
where ε=C1C2+C2C3, +C3C4+ . . . +CN−1CN+CNC1
=−1 is the cyclic correlation of the PN code sequence with shift one. As discussed above, the product CNC1=−1. Hence the value of the integration is −N−ai−1, which equals to −N−1 or −N+1 depending on the previous bit value ai−1.
The value of N is large (typically 127), so the decision logic simply compares the integration value to −N/2. A value greater than −N/2 is interpreted as a +1 bit, while a value less than −N/2 is interpreted as a −1 bit. Hence the signal has been decoded without the use of a correlation.
The first embodiment has better sensitivity than this embodiment, i.e. it is less sensitive to noise, but this embodiment has a higher data rate.
Those of ordinary skill in the art will recognize that the present invention has been described in terms of exemplary embodiments based upon use of an ideal rectangular pulse. However, the invention should not be so limited, since the present invention could be implemented using other pulse shapes. Similarly, the present invention may be implemented using general-purpose computers, microprocessor based computers, digital signal processors, microcontrollers, dedicated processors, custom circuits, ASICS and/or dedicated hard-wired logic.
Many other variations will also be evident to those of ordinary skill in the art. The embodiment disclosed can be embodied in a DSSS receiver for a location system, for instance, but it is understood that the method and apparatus of the present invention is equally applicable to all other systems using DSSS techniques.
While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications, permutations and variations will become apparent to those of ordinary skill in the art in light of the foregoing description. Accordingly, it is intended that the present invention embrace all such alternatives, modifications and variations as fall within the scope of the appended claims.
This application is a Div. of application Ser. No. 10/036,554 filed on Dec. 21, 2001, now U.S. Pat. No. 6,563,857.
Number | Name | Date | Kind |
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5559828 | Armstrong et al. | Sep 1996 | A |
5815526 | Rice | Sep 1998 | A |
6430212 | Alisobhani et al. | Aug 2002 | B1 |
6728295 | Nallanathan et al. | Apr 2004 | B1 |
Number | Date | Country | |
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20030152137 A1 | Aug 2003 | US |
Number | Date | Country | |
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Parent | 10036554 | Dec 2001 | US |
Child | 10378236 | US |