Claims
- 1. A method for a dynamic and automated generation of a custom processor for a Java program comprising steps of:
a) analyzing the Java program at a byte code level to determine an essential instruction set; b) converting the essential instruction set to a smaller, more regular Reduced Instruction Set Computing (RISC) instruction set; c) segmenting memory into code, constants and run time pools with a plurality of separate memory controllers for higher performance in a fetch/execute cycle; c) supporting subroutine calls and recursion through management of a plurality of frame stack pointers; d) coding of the essential instruction set based on a plurality of Algorithmic State Machine (ASM) charts; and e) testing and deploying a system that enables Java code to be directly converted to hardware.
- 2. The method according to claim 1 wherein the step of analyzing requires no access to source code during conversion and operates strictly on a code intended for a Java Virtual Machine, thereby distinct from Java Compilers or other approaches operating at a source code level requiring access to the source code and associated intellectual property.
- 3. The method according to claim 1 wherein the step of analyzing may be applied to programs written in other languages and subsequently converted to Java Byte Code either by automatically converting the code to Java or compiling it for a RISC like processor.
- 4. The method according to claim 1 wherein the step of analyzing results in the generation of a custom processor to run the algorithm, thereby removing the need for a generic purpose processor, resulting in decreased cost, power requirements and more compact devices.
- 5. The method according to claim 1 wherein the step of analyzing is extended to include all 227 byte code instructions of the Java Virtual Machine, resulting in a general purpose Java processor, which is more optimized than current Java processors.
- 6. The method according to claim 1 further comprising step of:
generating application specific and low footprint software for embedded system processors; wherein the low footprint, is generated as a result of a library of components of a plurality of operating system services with which a plurality of self standing executables is generated to include only components of an operating system essential for an operation of an application; and whereby a comprehensive hardware-software co-development environment is formed, operating in one framework with one common high level language and one common code base, thereby enabling a rapid migration from low footprint code generated for embedded system processors to a hardware implementation of the software, with a custom processor generated for the code.
- 7. The method according to claim 6 wherein the analyzing step requires no access to source code and thereby protects intellectual property associated with the source code.
- 8. The method according to claim 1 wherein the analyzing step further comprises generating code to run on a multitude of devices, including low cost, resource limited hardware.
- 9. The method according to claim 1 wherein the analyzing step further comprises generating code to run on devices such as Field Programmable Gate Arrays (FPGA) that can be upgraded in the field, remotely, via the Internet.
CROSS-REFERENCE
[0001] This application claims the benefit of priority from U.S. Provisional Application No. 60/421,930, filed Oct. 28, 2002, and is a continuation-in-part of application of U.S. application Ser. No. 10/434,948, filed May 8, 2003, which are herein incorporated by reference.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60421930 |
Oct 2002 |
US |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
10434948 |
May 2003 |
US |
Child |
10641917 |
Aug 2003 |
US |