Low-current digital-to-analog converter

Abstract

A current-multiplying digital-to-analog converter (DAC) produces a low-current output which has significantly reduced current spikes or "glitches" resulting from the inherent capacitances of the switching transistors. A transistor connected in what would normally be the output line of the DAC establishes a voltage which varies in proportion to the current in that line. This voltage is applied to the control terminal of a transistor in a second current line to regulate an output current which can be made very low without experiencing significant glitches. A DAC having differential outputs (actual and complementary values) is described.

Description

FIELD OF THE INVENTION

This invention relates to digital-to-analog converters (DACS) and, in particular, to current-multiplying DACS which convert a binary word to an analog value represented by an extremely small current.

BACKGROUND OF THE INVENTION

Current-multiplying digital-to-analog converters typically include a plurality of parallel conduction paths each of which is associated with one bit of the binary word which is to be converted to an analog value. The current magnitudes in the conduction paths are weighted by factors of two (often referred to as "binary weighting"). A switch included in each conduction path is controlled by the binary bit with which the path is associated. When a binary 1 is present at the input, the switch is closed and a current flows in the path. The currents in the paths are summed at a node, and the current emerging from the node is therefore representative of the binary word present at the input to the converter. In differential current DACS, double-poled switches are connected in each conduction path, and the DAC is provided with two outputs representative of the binary word and its complement.

While a variety of arrangements may be used to switch the currents in the conduction paths, these switches normally contain transistors. As is well known, transistors have inherent capacitances which yield current spikes or "glitches" as they are turned off and on. So long as the currents flowing through the DAC are fairly large these current glitches do not present a problem. However, since the glitch currents are of a fairly constant magnitude, they become proportionally more significant as the amount of current flowing through the converter is reduced. At current levels of 100 .mu.A or less, the current glitches can become a significant problem, that is, they may come to represent an appreciable fraction of the DAC's output current, thereby degrading its performance.

SUMMARY OF THE INVENTION

In accordance with this invention, a first transistor is connected in what would normally be the output conduction path of a DAC. As the current in that path varies, the voltage across the first transistor is applied to the control terminal of a second transistor which is connected in a second conduction path. The control potential of the second transistor in turn controls the current flowing through the second conduction path, which is used as the output current of the DAC. The current flowing through the first transistor can be maintained at a relatively high level, thereby reducing the significance of current glitches, while the current through the second conduction path can be reduced to a very low level.

In a preferred embodiment, to avoid the instability that would occur if the current flowing through the first transistor fell to zero, a current source provides a minimal current through the first transistor, even when the input to the DAC is all zeros. A compensating current source is also connected to the second transistor so as to provide a net zero output current at the all-zeros condition. A current amplifier is used to insure that the output current is equal to the input current when the maximum binary word (all ones) is present at the input of the DAC.

In the preferred embodiment, two differential outputs are provided showing the actual value and its complement, respectively, of the binary input.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic diagram of a prior art DAC.

FIG. 2 illustrates a schematic diagram of a double-ended DAC according to the invention.

FIGS. 3A and 3B illustrate simulated outputs of the prior art DAC of FIG. 1 and the DAC of FIG. 2, respectively.

FIGS. 4A-4D illustrate graphically the adjustments that are required by the need to maintain a current in transistors Q.sub.1 and Q.sub.2 at all times.

FIG. 5 illustrates a schematic diagram of a single-ended embodiment according to the invention.

FIG. 6 illustrates a modification of the DAC of FIG. 2 using a cascoded arrangement to further reduce current glitches.

FIG. 7 illustrates a block diagram of a generic DAC incorporating the principles of this invention

DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a schematic diagram of a conventional current-multiplying DAC having a digital input of n binary bits. The input current I.sub.in is generated by a constant current source 12 and flows through a transistor Q.sub.in. The collector and base of Q.sub.in are tied together, and Q.sub.in therefore acts as a diode which provides a steady reference voltage at its base terminal. The base terminal of transistor of Q.sub.in is tied to the respective bases of "current mirror" transistors Q.sub.1c through Q.sub.nc. Transistors Q.sub.1c through Q.sub.nc are connected in conduction paths 1 through n, respectively. The currents in conduction paths 1 through n are designated I.sub.1 through I.sub.n, respectively. Transistors Q.sub.1c through Q.sub.nc are fabricated such that currents I.sub.1 through I.sub.n differ from each other by a factor of two, i.e., I.sub.2 is double I.sub.1, I.sub.3 is double I.sub.2, etc. To accomplish this, the emitter area of each of transistors Q.sub.1c through Q.sub.nc is double that of the preceding transistor.

In reality, the emitter areas may be increased or precisely scaled by connecting several transistors in parallel, as is well known in the art. For example, transistor Q.sub.2c (not shown) may consist of two transistors connected in parallel, transistor Q.sub.3c (not shown) may consist of four transistors connected in parallel, and transistor Q.sub.nc may consist of 2.sup.n transistors connected in parallel, with each of the parallel-connected transistors being identical to transistor Q.sub.1c. This ensures that the currents in conduction paths 1 through n are related by a factor of two as nearly as possible.

Conduction paths 1 through n are connected together at a common node 15 and to a common node output line 13 which delivers the actual output current (I.sub.o +). Conduction paths 1 through n are also connected together at a common node 16 and to a common node output line 14 which delivers a complementary output current (I.sub.o -). These connections are made through paired transistors Q.sub.1a and Q.sub.1b for conduction path 1, and the corresponding paired transistors Q.sub.(n-1)a and Q.sub.(n-1)b for conduction path n-1, and Q.sub.na and Q.sub.nb for conduction path n. Each of transistors Q.sub.1a through Q.sub.nb is connected through a corresponding multiplexer M.sub.1a through M.sub.nb to lines 10 and 11. Line 10 is maintained at a voltage V.sub.low and line 11 is maintained at a voltage V.sub.hi. V.sub.low is a voltage that will turn off transistors Q.sub.1a through Q.sub.nb when applied to the bases thereof, and V.sub.hi is a voltage which will turn on transistors Q.sub.1a through Q.sub. nb when applied to the bases thereof.

The binary input to the DAC is applied to lines L.sub.1 through L.sub.n, with L.sub.1 holding the least significant bit and L.sub.n holding the most significant bit. Each of lines L.sub.1 through L.sub.n is connected to the control terminals of a corresponding pair of multiplexers M.sub.1a through M.sub.nb. For example, line L.sub.1 is connected to control terminals of multiplexers M.sub.1a and M.sub.1b, the input to multiplexer M.sub.1b being inverted. Thus, when a binary one appears at line L.sub.1, multiplexer M.sub.1a connects line 11 to the base of transistor Q.sub.1a, turning it on, and multiplexer M.sub.1b connects line 10 to the base of transistor Q.sub.1b, turning it off. Conversely, if a binary zero appears at line L.sub.1, transistor Q.sub.1a is turned off and transistor Q.sub.1b is turned on. As a result, when a binary 1 is at line L.sub.1 current flows in output line 13 into conduction path 1, and when a binary zero appears at line L.sub.1 current flows in output line 14 through conduction path 1. A capacitor C.sub.2 stabilizes V.sub.hi and V.sub.low and prevents differential glitches from appearing on lines 10 and 11 as multiplexers M.sub.1a -M.sub.nb are switched back and forth. This differential glitching would otherwise appear at all of the current switch inputs and would be coupled to the output of the DAC.

In a similar manner, the binary inputs at the remaining lines L.sub.2 through L.sub.n determine whether current flows from output line 13 or output line 14 into the corresponding conduction paths. The current flowing in output line 13 therefore represents the summation of the currents flowing in each of conduction paths 1 through n which has a binary 1 at its associated input. Because the current in each of conduction paths 1 through n represents a binary digit at the associated input, the summation in output line 13 represents the binary word which is present at input lines L.sub.1 through L.sub.n.

Conversely, the current in output line 14 is the summation of the currents flowing in conduction paths 1 through n which have a binary 0 at their associated inputs, and it therefore represents the complement of the binary word appearing at input lines L.sub.1 -L.sub.n.

Transistors Q.sub.1a through Q.sub.nb, which together are used to switch the currents between output lines 13 and 14, have inherent parasitic capacitances. Thus, as the binary input changes and these transistors are switched on and off, current spikes or "glitches" are coupled through these parasitic capacitances (base to collector and base to emitter) and appear in output lines 13 and 14. The size of the current glitches is relatively constant and does not vary much with the size of the currents flowing in conduction paths 1 through n. So long as the currents flowing in conduction paths 1 through n are fairly large (for example, 100 .mu.A or more) these glitch currents do not significantly affect the operation of the device. However, when the currents in the device fall below this level, the glitch currents begin to present a problem.

FIG. 3A illustrates the simulated output of a six-bit DAC as it cycles through 64 different states in sequence. The y-axis represents the DAC output current (I.sub.o +)-(I.sub.o -) in amperes; the x-axis represents time in seconds; the digital input word is incremented by one least significant bit (LSB) every 0.05.times.10.sup.-6 seconds. Each LSB increment represents a change of approximately 32.times.10.sup.-9 amperes (32 nanoamperes) at the DAC output. As is evident from FIG. 3A, the glitch currents, which show up as overshoots as the DAC proceeds from one state to the next, have a very significant effect on the output of the DAC.

FIG. 2 illustrates a low-current DAC in accordance with the invention. Elements which are the same as those shown in FIG. 1 are similarly numbered. A transistor Q.sub.1 is connected into line 13, with its collector coupled to a source of positive voltage. Similarly, a transistor Q.sub.2 is connected into line 14, with its collector coupled to a source of positive voltage. The bases of transistors Q.sub.1 and Q.sub.2 are tied in common to a reference voltage V.sub.ref. In this embodiment, V.sub.ref =3 V.sub.be, or about 2.25 V. A capacitor C.sub.2 stabilizes the reference voltage V.sub.ref.

The remainder of the circuitry in the lower part of FIG. 2 is identical to that shown in FIG. 1, except that I.sub.in has been redesignated as a reference current I.sub.ref to indicate that it is no longer the input current for the DAC. (Transistor Q.sub.in has also been redesignated as transistor Q.sub.ref.) Thus, as the binary bits at input lines L.sub.1 through L.sub.n vary, the currents in lines 13 and 14 vary as described above. As a result, the emitter voltages of transistors Q.sub.1 and Q.sub.2 vary in a logarithmic manner such that the voltage difference developed between the emitters of transistors Q.sub.1 and Q.sub.2 contains a logarithmic representation of the difference between the currents in lines 13 and 14.

The emitters of transistors Q.sub.1 and Q.sub.2 are connected to the bases of transistors Q.sub.3 and Q.sub.4, respectively. The collector of transistor Q.sub.4 is connected to a line 20 which carries the actual output current (I.sub.o +), and the collector of transistor Q.sub.3 is connected to a line 21 which carries the complementary output current (I.sub.o -). The emitters of transistors Q.sub.3 and Q.sub.4 are connected via a line 22 through a transistor Q.sub.5 to a source of negative voltage.

Assuming that transistors Q.sub.1 and Q.sub.2 are identical and transistors Q.sub.3 and Q.sub.4 are identical, it can be shown that the collector currents of these transistors are related as follows: ##EQU1##

This equation can be derived from the general equation for the base-emitter voltage (V.sub.be) of a bipolar transistor:

V.sub.be =V.sub.t ln[I.sub.c /I.sub.sat ] (2) where V.sub.t is the diode potential of the transistor, I.sub.c is the collector current, and I.sub.sat is the junction saturation current.

Let V.sub.e1 represent the emitter potential of Q.sub.1, V.sub.e2 represent the emitter potential of Q.sub.2, etc. Applying the above equation to transistors Q.sub.1 -Q.sub.4 yields the following.

V.sub.ref -V.sub.e1 =V.sub.t ln[I.sub.Q1 /I.sub.sat1 ] (3) V.sub.ref -V.sub.e2 =V.sub.t ln[I.sub.Q2 /I.sub.sat2 ] (4) V.sub.e1 -V.sub.e3 =V.sub.t ln[I.sub.Q3 /I.sub.sat3 ] (5) V.sub.e2 -V.sub.e4 =V.sub.t ln[I.sub.Q4 /I.sub.sat4 ] (6)

Subtracting equation (3) from equation (4) yields:

V.sub.e1 -V.sub.e2 =V.sub.t [ln(I.sub.Q2 /I.sub.sat2)-ln(I.sub.Q1 /I.sub.sat1)] (7)

Recognizing that V.sub.e3 =V.sub.e4, subtracting equation (6) from equation (5) gives:

V.sub.e1 -V.sub.e2 =V.sub.t [ln(I.sub.Q3 /I.sub.sat3)-ln(I.sub.Q4 /I.sub.sat4)] (8)

Combining equations (7) and (8) yields: ##EQU2##

Since Q.sub.1 and Q.sub.2 are identical, and Q.sub.3 and Q.sub.4 are identical, I.sub.sat1 =I.sub.sat2 and I.sub.sat3 =I.sub.sat4. Therefore, ##EQU3##

Since the ratio of the collector currents in transistors Q.sub.3 and Q.sub.4 is inversely proportional to the ratio of collector currents in transistors Q.sub.1 and Q.sub.2, the collector currents flowing through transistors Q.sub.3 and Q.sub.4 represent, in analog form, the actual and complementary value of the binary word present at input lines L.sub.1 -L.sub.n.

The absolute values of the currents flowing through transistors Q.sub.1 and Q.sub.2, on one hand, and the currents flowing through transistors Q.sub.3 and Q.sub.4, on the other hand, do not need to be related to each other in any particular way. That is, the currents flowing through transistors Q.sub.1 and Q.sub.2 may be made high, while the currents flowing through transistors Q.sub.3 and Q.sub.4 may be made low. Accordingly, in the DAC of FIG. 2 the output currents (through transistors Q.sub.3 and Q.sub.4) may be made extremely small while the currents through transistors Q.sub.1 and Q.sub.2 are kept at a level which is sufficiently large in relation to the glitch currents.

It is important to avoid the condition in which the current through either transistor Q.sub.1 or Q.sub.2 becomes zero, when the inputs at lines L.sub.1 -L.sub.n are either all ones or all zeros. If this happens, the emitters of these transistors may de-bias and experience excessive voltage drift. Moreover, maintaining a current through these transistors assures a relatively low impedance at the emitter nodes, which keeps the associated poles at high frequency, maintaining bandwidth and minimizing response time.

To avoid the no-current situation in transistors Q.sub.1 and Q.sub.2, current sources 23 and 24 are connected to the emitters of transistors Q.sub.1 and Q.sub.2, respectively, and supply currents designated I.sub.os.

It is desirable, however, to have the currents flowing through transistors Q.sub.3 and Q.sub.4 reach zero when the inputs are all ones or all zeros, and the presence of current sources 23 and 24 prevents this zero-current condition in transistors Q.sub.3 and Q.sub.4. To accomplish zero output current at an all-ones or all-zeroes input, compensating current sources 25 and 26 are connected to the collectors of transistors Q.sub.3 and Q.sub.4, respectively. Current sources 25 and 26 provide cancellation currents I.sub.oc in output lines 20 and 21 to compensate for the currents through transistors Q.sub.3 and Q.sub.4 which are attributable to current sources 23 and 24. That is, current source 25 provides a current through transistor Q.sub.3 which cancels out the current that would otherwise flow through line 21 when the inputs are all ones, and current source 26 provides a current through transistor Q.sub.4 which cancels out the current that would otherwise flow through line 20 when all of the inputs are zeros.

FIGS. 4A-4D contain graphs which help to explain this adjustment as well as several others that can be made in the device. FIG. 4A shows ideal DAC behavior, the horizontal axis representing the binary input and the vertical axis representing the analog current output I.sub.o + (the digital quantization steps are not shown). When the input is at the maximum binary input (all ones), the output current I.sub.o + is equal to the input current I.sub.in. The addition of current sources 23 and 24 yields the situation shown in FIG. 4B, where a small output current flows even when the binary input is all zeros. The output at the binary maximum is still equal to I.sub.in, i.e., the slope of the curve is reduced. Inclusion of current sources 23 and 24 prevents the emitter currents in transistors Q.sub.1 or Q.sub.2 from reaching zero value when the digital input is at all-zeros or all-ones, respectively. This achieves the desired minimum bias condition mentioned above, but also produces a non-zero minimum I.sub.o + and I.sub.o - current at the differential current outputs.

First, we determine the required output I.sub.oc of current sources 25 and 26. From the output current equation:

I.sub.Q1 /I.sub.Q2 =I.sub.Q4 /I.sub.Q3 (13)

At all-zeros digital input:

I.sub.os /[I.sub.os +(I.sub.l + - - - +I.sub.n)]=I.sub.Q4 /I.sub.Q3(14) where I.sub.os is current supplied by current sources 23 and 24. It can be seen from this that I.sub.Q4 is non-zero even with an all-zero input. Since I.sub.Q3 +I.sub.Q4 =I.sub.Q5 (15) where I.sub.Q5 is the current through transistor Q.sub.5, then I.sub.Q3 =I.sub.Q5 -I.sub.Q4 (16)

This can be substituted into equation (13) to yield:

I.sub.Q1 /I.sub.Q2 =I.sub.Q4 /(I.sub.Q5 -I.sub.Q4) (17)

Using equation (14):

I.sub.os /[I.sub.os +(I.sub.1 + - - - +I.sub.n)]=I.sub.Q4 /(I.sub.Q5 -I.sub.Q4) (18)

Inverting,

[I.sub.os +(I.sub.1 + - - - +I.sub.n)]/I.sub.os =(I.sub.Q5 -I.sub.Q4)/I.sub.Q4 (19) (I.sub.1 + - - - +I.sub.n)/I.sub.os +1=I.sub.Q5 /I.sub.Q4 -1(20) (I.sub.1 + - - - +I.sub.n)/I.sub.os +2=I.sub.Q5 /I.sub.Q4 (21) I.sub.Q4 =I.sub.Q5 /[(I.sub.1 +- - - +I.sub.n)/I.sub.os +2](22)

The residual current I.sub.Q4 is the current which must be canceled in order to allow the output currents I.sub.o + and I.sub.o - to reach zero value at all-ones and all-zeros digital input value, respectively. Therefore, I.sub.oc, the required current output of current source 26 is:

I.sub.oc =I.sub.Q5 /[(I.sub.1 + - - - +I.sub.n)/I.sub.os +2](23)

It can be seen from this last equation that if I.sub.os were zero, I.sub.oc would also be zero, i.e., there would be no output cancellation current needed because there would be no residual output current. If I.sub.os became very large (approached infinity) and swamped out (I.sub.1 + - - - +I.sub.n), then I.sub.Q3 and I.sub.Q4 would always be equal and thus the cancellation current would have to be I.sub.Q5 /2. The all-ones condition is the complement of the all-zeros condition, and the analysis is similar. Therefore, equation (23) also gives the required output current I.sub.oc for current source 25.

FIG. 4C illustrates the situation after compensation current sources 25 and 26 have been added. The analog output is now zero when the binary input is zero but, because the slope of the curve remains reduced, the output current at the maximum binary input (I.sub.o max) is somewhat less than I.sub.in.

To readjust the slope of the curve in FIG. 4C so that I.sub.o max=I.sub.in, it is necessary to add circuitry which multiplies the input current. This is done by means of transistors Q.sub.5 and Q.sub.6. Transistor Q.sub.6 is connected in a current path which carries I.sub.in, and its collector and base are shorted together. Thus, transistor Q.sub.6 performs like a diode with its emitter-base voltage varying with I.sub.in. The base of transistor Q.sub.6 is tied to the base of transistor Q.sub.5.

In order to re-achieve I.sub.o max equal to I.sub.in, the emitter area of transistor Q.sub.5 is made larger than the emitter area of transistor Q.sub.6. This provides current amplification. In an all-zeros condition, the output current I.sub.o - through line 21, which is I.sub.Q3 -I.sub.oc, should equal I.sub.in :

I.sub.o -=I.sub.in =I.sub.Q3 -I.sub.oc (24)

Recall that in an all-zeros condition,

I.sub.oc =I.sub.Q4 (25)

Thus,

I.sub.o -=I.sub.in =I.sub.Q3 -I.sub.Q4 (26)

Recall also that

I.sub.Q4 =I.sub.Q5 /[(I.sub.1 + - - - +I.sub.n)/I.sub.os +2](27) and I.sub.Q3 =I.sub.Q5 -I.sub.Q4 (28)

Thus

I.sub.in =I.sub.Q5 -2I.sub.Q4 (29) I.sub.in =I.sub.Q5 -2I.sub.Q5 /[(I.sub.1 + - - - +I.sub.n)/I.sub.os +2](30) I.sub.in =I.sub.Q5 ]1-2/[(I.sub.1 + - - - +I.sub.n)/I.sub.os +2](31) I.sub.in /I.sub.Q5 =[1-2/[(I.sub.1 + - - - +I.sub.n)/I.sub.os +2]](32) Inverting, I.sub.Q5 /I.sub.in =1/{[1-2/[(I.sub.1 + - - - + i I.sub.n)/I.sub.os +2]]}(33)

Rearranging,

I.sub.Q5 /I.sub.in =1+2I.sub.os /(I.sub.1 + - - - + I.sub.n)(34)

The ratio I.sub.Q5 I.sub.in is the emitter area ratio of Q.sub.5 to Q.sub.6 which will achieve restoration of I.sub.o max to equality with I.sub.in.

As a result of these adjustments, the DAC operates as shown in FIG. 4D, which is identical to FIG. 4A.

FIG. 3B illustrates by computer simulation the performance of a DAC in accordance with this invention, using the test and parameters described in FIG. 3A. By comparing FIG. 3B with FIG. 3A, one can see that the current glitches in a DAC according to this invention are substantially reduced.

The DAC illustrated in FIG. 2 is double-ended or differential in the sense that actual and complementary analog representations of the binary input appear on lines 20 and 21, respectively. FIG. 5 illustrates a single-ended version of the DAC which provides a push-pull output current which can be either source or sink, depending on whether the value of the input binary word is above or below its median value. In the DAC of FIG. 5, transistors Q.sub.7 and Q.sub.8 obviate the need for compensation current sources 25 and 26. It can be seen that if current sources 25 and 26 were to be added to the circuit of FIG. 5 at the collectors of transistors Q.sub.3 and Q.sub.4, as they are in FIG. 2, their currents would cancel each other by the effect of current mirror Q7/Q8. Thus, current sources 25 and 26 become unnecessary in the single-ended output embodiment.

An embodiment of a DAC which is even less susceptible to current glitches is shown in FIG. 6. This is similar to the embodiment shown in FIG. 2 except that it is a cascoded arrangement with transistors Q.sub.1d -Q.sub.nd connected in conduction paths 1-n and with a transistor Q.sub.9 connected to the collector of transistor Q.sub.5. The bases of transistors Q.sub.1d -Q.sub.nd are maintained at a reference voltage provided at the base of a transistor Q.sub.10, which is 2 V.sub.be, or about 1.5 V, above negative supply. The reference voltage for transistors Q.sub.1d -Q.sub.nd could be provided in other ways. Similarly, the base of transistor Q.sub.9 is maintained at a reference voltage equal to 2 V.sub.be.

Transistor pairs Q.sub.1a -Q.sub.1b through Q.sub.na -Q.sub.nb are differential current switches. As any pair is switched, a minor voltage disturbance will occur at the common emitter node. This will produce a glitch in the corresponding current (I.sub.1 -I.sub.n), which will be proportional to the parasitic capacitance seen at the collector of the corresponding transistor Q.sub.1c -Q.sub.nc. Since transistors Q.sub.1c -Q.sub.nc are generally large for reasons of current scaling or device matching, they may have large parasitic capacitances, and significant glitches may occur as currents are switched in conduction paths 1-n. This problem can be lessened by including cascode transistors Q.sub.1d -Q.sub.nd in conduction paths 1-n. Cascode transistors Q.sub.1d -Q.sub.nd may be made significantly smaller than transistors Q.sub.1c -Q.sub.nc so that they proportionally reduce the current glitches that are passed to transistors Q.sub.1a -Q.sub.nb and to the output of the DAC. Similarly, cascode transistor Q.sub.9 reduces the current glitches that are produced as the voltage at the common emitters of transistors Q.sub.3 and Q.sub.4 is varied.

While specific embodiments of this invention have been disclosed, it will be clear to those skilled in the art that many additional or alternative embodiments may be constructed in accordance with the broad principles of the invention. For example, there are many alternative ways of switching the currents in the circuit in addition to the multiplexer arrangement illustrated in FIG. 2. Among the possible alternatives is the circuitry for the DAC0800 series of 8-bit digital-to-analog converters described at pages 8-118 to 8-120 of the National Semiconductor Linear Products Databook (1982). Moreover, while in the embodiments described transistors Q.sub.1 -Q.sub.4 are shown as bipolar transistors, other devices such as MOSFETS may be used.

This invention is furthermore not limited to DACs which use binary weighted currents in parallel conduction paths to produce an analog current output. It is also applicable to other types of DACs, such as those which use a decoder to provide an output representative of the value of the binary input. For example, the decoder in a 6-bit DAC would have 64 output lines; if the input were 100100, 36 of the output lines would be active. Each active line results in the generation of a current having a magnitude equal to the other currents, and all of the currents are summed to provide an analog output. This type of DAC is sometimes referred to as a "thermometer type" DAC.

FIG. 7 illustrates a block diagram which includes a generic current-multiplying DAC 70 which has digital input lines A.sub.1 -A.sub.n and differential output lines 71 and 72. The current in line 71 represents the digital input on lines A.sub.1 -A.sub.n and the current in line 72 represents the complement thereof. The remaining elements in FIG. 7 are identical to those shown in FIG. 2 and operate to provide a relatively glitch-free output despite parasitic capacitances of the components of DAC 70.

Claims

1. A digital-to-analog converter for providing an output current in response to a digital input, said converter comprising:

a plurality of parallel conduction paths, each of said conduction paths being associated with a digit of a binary input to said digital-to-analog converter;

a common node conduction path connected to each of said parallel conduction paths;

a first transistor connected in said common node conduction path, said first transistor defining a reference voltage point in said common node conduction path; and

an output line having a second transistor connected therein, a control terminal of said second transistor being connected to said reference voltage point, the voltage at said reference voltage point operative to determine the magnitude of an output current in said output line.

2. The digital-to-analog converter of claim 1 comprising a first current source connected to said common node conduction path.

3. The digital-to-analog converter of claim 2 wherein said first current source is operative to maintain a current flowing in said common node conduction path while said digital-to-analog converter is in operation.

4. The digital-to-analog converter of claim 2 comprising a second current source connected to said output current line.

5. The digital-to-analog converter of claim 4 wherein said second current source is operative to cancel a current flowing in said output line as a result of the current produced by said first current source, when the output of said digital-to-analog converter is at a minimum value.

6. The digital-to-analog converter of claim 4 comprising a current amplification means connected to said output current line, said current amplification means operative to provide a current in said output line of a magnitude which is at a predetermined ratio to the magnitude of an input current supplied to said current amplification means.

7. The digital-to-analog converter of claim 6 wherein said current amplification means comprises a pair of transistors, one of said pair of transistors being connected in said output line.

8. The digital-to-analog converter of claim 6 wherein said current amplification means is operative to ensure that the current in said output line is substantially equal to said input current when the output of said digital-to-analog converter is at a maximum value.

9. The digital-to-analog converter of claim 1 comprising a second output line for providing a second output current representative of the complement of said binary input.

10. The digital-to-analog converter of claim 1 comprising:

a second common node conduction path;

respective switching units connected to each of said parallel conduction paths, each of said switching units operative to switch a current in one of said parallel conduction paths to said common node conduction path or said second common node conduction path;

a third transistor connected to said second common node conduction path, said third transistor defining a second reference voltage point in said second common node conduction path; and

a second output line having a fourth transistor connected therein, a control terminal of said fourth transistor being connected to said second reference voltage point, the voltage at said second reference voltage point operative to determine the size of a second output current in said second output line.

11. The digital-to-analog converter of claim 10 comprising a first current source connected to said common node conductor path and a second current source connected to said second common node conduction path.

12. The digital-to-analog converter of claim 11 comprising a third current source connected to said output line and a fourth current source connected to said second output line.

13. The digital-to-analog converter of claim 12 comprising a current amplification means connected to said second and fourth transistors.

14. The digital-to-analog converter of claim 10 comprising a current mirror means connected between said output line and said second output line, said current mirror means being for introducing a current to said output line which is substantially equal in magnitude to a current in said second output line.

15. The digital-to-analog converter of claim 14 wherein said current mirror means comprises a pair of transistors having their control terminals connected together.

16. The digital-to-analog converter of claim 14 wherein an output current in said output line is a bi-directional current, flowing in one direction when said binary input is at a maximum and the other direction when said binary input is at a minimum.

17. The digital-to-analog converter of claim 1 wherein each of said parallel conduction paths contains a cascoded transistor.

18. The digital-to-analog converter of claim 1 wherein a cascoded transistor is connected in series with said second transistor.

19. The digital-to-analog converter of claim 1 wherein each of said first and second transistors comprises a bipolar transistor.

20. A digital-to-analog converter having a common node current line, the magnitude of a current in said common node current line representing in analog form a binary input to said converter; and

a reference voltage point in said common node current line, the voltage at said reference voltage point being for determining the magnitude of an output current in an output line of said digital-to-analog converter.

21. The digital-to-analog converter of claim 20 wherein the voltage at said reference voltage point varies substantially as the natural logarithm of the magnitude of a current in said common node current line.

22. The digital-to-analog converter of claim 21, said output line comprising a current regulating means, a control terminal of said current regulating means being connected to said reference voltage point.

23. The digital-to-analog converter of claim 22 wherein said current regulating means comprises a bipolar transistor.

24. A method of providing an output current for a digital-to-analog converter, said digital-to-analog converter comprising a line which carries a first current representative of a digital input to said converter, said method comprising:

creating a voltage representative of the magnitude of said first current; and

providing said voltage to a current controlling means in an output line, said current controlling means regulating the size of a second current in said output line.

25. The method of claim 24 wherein said voltage varies substantially in proportion to the natural logarithm of said first current.

26. The method of claim 25 wherein the current controlling means comprises a bipolar transistor.

27. A digital-to-analog converter comprising:

a first current path which carries a current representative of a digital input to said converter, said first current path containing a first transistor;

a second current path which carries a current representative of the complement of said digital input, said second current path containing a second transistor,

a third current path containing a third transistor;

a fourth current path containing a fourth transistor;

a point in said first current path being connected to a control terminal of said third transistor and a point in said second current path being connected to a control terminal of said fourth transistor;

wherein the currents in said transistors have substantially the following relationship when said converter is in operation ##EQU4## where I.sub.Q1 is the current through said first transistor, I.sub.Q2 is the current through said second transistor, I.sub.Q3 is the current through said third transistor, and I.sub.Q4 is the current through said fourth transistor.

28. A digital-to-analog converter comprising:

a digital-to-analog conversion means comprising:

a plurality of digital input lines; and

an intermediate output line;

the current in said intermediate output line being of a magnitude representative of a binary input on said input lines when said digital-to-analog conversion means is operative;

a first transistor connected to said intermediate output line, said first transistor defining a reference voltage point; and

a second transistor in an output line, a control terminal of said second transistor being connected to said reference voltage point, the voltage at said reference voltage point operative to determine the size of an output current in said output line.

29. The digital-to-analog converter of claim 28 comprising a first current source connected to said intermediate output line.

30. The digital-to-analog converter of claim 29 comprising a second current source connected to said output line.

31. The digital-to-analog converter of claim 30 comprising a current amplification means connected to said output line, said current amplification means operative to provide a current in said output line of a magnitude which is at a predetermined ratio to the magnitude of an input current supplied to said current amplification means.

32. The digital-to-analog converter of claim 31 wherein said current amplification means comprises a pair of transistors, one of said pair of transistors being connected in said output line.

33. The digital-to-analog converter of claim 28 wherein said digital-to-analog conversion means comprises a second intermediate output line, the current in said second intermediate output line representing a complement of a binary input on said input lines when said digital-to-analog conversion means is operative;

a third transistor connected in said second intermediate output line, said third transistor defining a second reference voltage point in said second intermediate output line; and

a second output line having a fourth transistor connected therein, a control terminal of said fourth transistor being connected to said second reference voltage point, the voltage at said second reference voltage point operative to determine the size of a second output current in said second output line.

34. The digital-to-analog converter of claim 33 comprising a first current source connected to said intermediate output line and a second current source connected to said second intermediate output line.

35. The digital-to-analog converter of claim 34 comprising a third current source connected to said output line and a fourth current source connected to said second output line.

36. The digital-to-analog converter of claim 35 comprising a current amplification means connected to said second and fourth transistors.

37. The digital-to-analog converter of claim 33 comprising a current mirror means connected between said output line and said second output line, said current mirror means introducing a current to said output line which is substantially equal in magnitude to a current in said second output line.

38. The digital-to-analog converter of claim 28 wherein said digital-to-analog conversion means comprises a plurality of conduction paths for carrying respective weighted binary currents.

39. The digital-to-analog converter of claim 28 wherein said digital-to-analog conversion means comprises a thermometer type digital-to-analog converter.