This invention relates to an amplifier, and more particularly to a low distortion class-D amplifier with high efficiency.
Conventional class-D amplifiers receive an analog input signal and generate a digital output signal. One advantage of a class D amplifier over a linear amplifier (e.g., a class-AB amplifier) is its high efficiency. Because the output pulses of the class-D amplifier have a fixed amplitude, the switching elements are switched either on or off, rather than operated in linear mode. One common application for a class-D amplifier is a driver for a loudspeaker.
However, most class-D amplifiers that employ standard implementations suffer from propagation delays and low power supply rejection ratio due to the switching waveforms.
The present invention provides a low distortion class-D amplifier. In accordance with one embodiment of the present invention, an amplifier comprises a power supply terminal for receiving a power supply, an amplification stage, and an output stage. The amplification stage receives an input signal and generates a ramp signal. Furthermore, the amplification stage generates a pulse width modulation signal based on the ramp signal and a hysteretic signal. The output stage coupled to the power supply terminal receives the pulse width modulation signal and generates an output. Advantageously, the ramp signal and the hysteretic signal are positioned at a voltage level that is half the voltage level of the power supply and that varies proportionally with the power supply.
Features and advantages of embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals depict like parts, and in which:
Reference will now be made in detail to the embodiments of the present invention. While the invention will be described in conjunction with the embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims.
Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
The amplification stage 180 receives an input signal 170 and generates a ramp signal 130. The amplification stage 180 generates a pulse width modulation signal 140 based on the ramp signal 130 and a hysteretic signal 132 that is used to drive the output stage 160. Advantageously, the ramp signal 130 and the hysteretic signal 132 are positioned at a voltage level that is half the voltage level of the power supply VDC and varies proportionally with the power supply VDC.
The output stage 160 coupled to the power supply terminal 110 receives the pulse width modulation signal 140 from the amplification stage 180 and generates an amplified output signal 190. In one embodiment, the output stage 160 comprises a full bridge circuit.
As shown in
The amplification stage 180 further comprises a second circuit shown as the integrating stage 102 that receives the translated signal 120 from the first circuit (translation stage) 101 and an integrating signal 122 from the full bridge circuit 160, and generates the ramp signal 130 therefrom. Therefore, an oscillator and a ramp generator are not needed in the present invention.
A comparison stage 103 receives the ramp signal 130 and the hysteretic signal 132, and generates the pulse width modulation signal 140 to drive the full bridge circuit 160.
To summarize, the amplifier 100 in
Advantageously, the ramp signal 130 and the hysteretic signal 132 are positioned at a voltage level that is half the voltage level of the power supply and that varies proportionally with the power supply.
The amplifier 100 in
The first resistor divider comprises a first resistor 260 and a second resistor 262. In one embodiment, the first resistor 260 comprises a first resistance R1 less a second resistance ΔR1. In one embodiment, the second resistor 262 comprises the first resistance R1 added to the second resistance ΔR1. Therefore, R260=R1−ΔR1 and R262=R1+ΔR1.
The amplifier 100 further comprises a second resistor divider, shown as resistors 250 and 252, coupled between the first switching node LX1 and the second switching node LX2 of the full bridge circuit 160 for providing the integrating signal 122 to the second circuit (integrating stage) 102.
The second resistor divider comprises a first resistor 250 and a second resistor 252. In one embodiment, the first resistor 250 comprises a first resistance R2 added to a second resistance ΔR2. In one embodiment, the second resistor 252 comprises the first resistance R2 subtracted from the second resistance ΔR2. Therefore, R250=R2+ΔR2 and R252=R2−ΔR2.
The first circuit shown as the translation stage 101 comprises an operational transconductance amplifier 202 which is coupled to the second circuit (integrating stage) 102 for converting the input signal 170 to an input current Iin. The translation stage 101 further comprises a resistor divider, shown as resistors 240 and 242, coupled between LX1 and LX2 for receiving the input current Iin and producing a translated signal 120 that is positioned at half of the voltage level of the power supply VDC. The resistor 240 and resistor 242 have the same resistance R.
The second circuit shown as the integrating stage 102 comprises an operational amplifier 204 and a capacitor 234. The integrating stage 102 receives the translated signal 120 and the integrating signal 122, and generates a ramp signal 130 to the comparison stage 103.
The comparison stage shown as the comparator 103 compares the hysteretic signal 132 with the ramp signal 130, and generates a pulse width modulation signal 140 to drive the full bridge circuit 160. The output capacitor 232 that is coupled between the first switching node LX1 and the second switching node LX2 provides the amplified output signal to the speaker 230. As such, the speaker 230 receives the amplified audio signal and generates audible sound therefrom.
In one embodiment, the input signal 170 comprises an input voltage Vin. In operation, the operational transconductance amplifier 202 converts the input voltage Vin to an input current Iin and uses the resistor divider (shown as resistor 240 and resistor 242) to create a translated signal 120 that is positioned at half of the voltage level of the supply voltage VDC from terminal 110. If we assume that the gain of the operational transconductance amplifier 202 is g, then the voltage of the translated signal 120 is given by:
V120=g*(R/2)*Vin+VDC/2 (1)
It should be noted that the first switching node LX1 and the second switching node LX2 of the full bridge circuit 160 are always out of phase. Therefore, the integrating current I122 will have two different levels depending on the state of the switching nodes LX1 and LX2. In one embodiment, when the pulse width modulation signal 140 is high, the voltage at LX1 is VDC and voltage at LX2 is zero. In contrast, when the pulse width modulation signal 140 is low, the voltage at LX1 is zero and the voltage at LX2 is VDC.
Since the voltage Vint at the inverting input of the operational amplifier 204 is equal to the voltage V120 at the non-inverting input of the operational amplifier 204, the integrating current I122 when the pulse width modulation signal 140 is high and the integrating current I122′ when the pulse width modulation signal 140 is low can be calculated as:
I122=(VCD−V120)/(R2+ΔR2)−V120/(R2−ΔR2), when the pulse width modulation signal 140 is high; (2)
I122′=(VCD−V120)/(R2−ΔR2)−V120/(R2+ΔR2), when the pulse width modulation signal 140 is low. (3)
Based on equation (1), equations (2) and (3) can be rewritten as:
I122=(−VCD*ΔR2−g*R*Vin*R2)/(R22−ΔR22), when the pulse width modulation signal 140 is high; (4)
I122′=(VCD*ΔR2−g*R*Vin*R2)/(R22−ΔR22), when the pulse width modulation signal 140 is low. (5)
The voltage of the hysteretic signal 132 is
V132=VDC*(R1+ΔR1)/2R1=VDC/2+VDC*ΔR1/2R1, when the pulse width modulation signal 140 is high; (6)
V132′=VDC*(R1−ΔR1)/2R1=VDC/2−VDC*ΔR1/2R1, when the pulse width modulation signal 140 is low. (7)
Therefore, the amplitude of the ramp signal 130 is the difference between V132 and V132′, that is:
A130=VDC*ΔR1/R1. (8)
As such, a parameter limit of the ramp signal 130 is defined by the first resistance R1 and the second resistance ΔR1 of the first resistor divider (shown as resistors 260 and 262). In one embodiment, the aforementioned parameter limit of the ramp signal 130 comprises the amplitude A130 of the ramp signal 130.
As shown in
Advantageously, both hysteretic signal 132 and ramp signal 130 are positioned at a voltage level that is half of the power supply voltage VDC.
Turning back to
ΔQ=C230*A130=−I122*T1=I122′*T2. (9)
Therefore, when equations (3) and (4) are substituted into equation (9), the following equation will be obtained:
VDC*(T2−T1)/(T2+T1)=g*R*R2/ΔR2*Vin. (10)
The equivalent theoretical output voltage 190 across the output capacitor 232 is equal to:
Therefore, the gain of the amplifier 100 is:
A=V190/Vin=−g*R*R2/ΔR2. (12)
It will be appreciated that the gain A of the amplifier 100 remains constant when the input signal 170 varies. Therefore, the gain of the amplifier 100 does not depend on the input voltage Vin, which assures high power supply rejection ratio.
According to equation (9), the switching frequency of the full bridge circuit 160 is:
fsw=1/(T1+T2)=1/((−C230*A130/I122)+(C230*A130/I122′)) (13)
When equation (2) and (3) are substituted into equation (13), the switching frequency becomes:
fsw=(VDC2*ΔR22−g2*R2*Vin2*R22)/(C230*A130(R22−ΔR22)*2*VDC*ΔR2) (14)
When equation (8) is substituted into equation (14), the switching frequency becomes:
fsw=R1*ΔR2/(2*C230*ΔR1*(R22−ΔR22))−g2*R2*Vin2*R22*R1/(2*C230*ΔR1*VDC2*ΔR22*(R22−ΔR22)) (15)
If we assume K1=R1*ΔR2/(2*C230*ΔR1*(R22−ΔR22)) and K2=g2*R2*R22*R1/(2*C230*ΔR1*ΔR22*(R22−ΔR22) then equation (15) becomes:
fsw=K1−K2*(Vin/VDC)2 (16)
It should be appreciated that K1 and K2 are constant. The switching frequency fsw only relates to the input voltage Vin and the supply voltage VDC. As such, the switching frequency fsw remains constant when the input signal is zero.
Accordingly, the present invention provides a low distortion class-D amplifier with high power supply rejection ratio. The gain of the class-D amplifier does not depend on the input signal. In addition, no oscillator and ramp generator is required in the present invention. In addition, the present invention also provides an audio system comprising a low distortion class-D amplifier for receiving an audio signal, and a speaker coupled to the low distortion class-D amplifier for converting the audio signal to audible sound.
While the foregoing description and drawings represent the preferred embodiments of the present invention, it will be understood that various additions, modifications and substitutions may be made therein without departing from the spirit and scope of the principles of the present invention as defined in the accompanying claims. One skilled in the art will appreciate that the invention may be used with many modifications of form, structure, arrangement, proportions, materials, elements, and components and otherwise, used in the practice of the invention, which are particularly adapted to specific environments and operative requirements without departing from the principles of the present invention. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims and their legal equivalents, and not limited to the foregoing description.
This application claims the benefit of U.S. Provisional Application No. 60/785,105, filed on Mar. 22, 2006, the specification of which is hereby incorporated in its entirety by reference.
Number | Name | Date | Kind |
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6614297 | Score et al. | Sep 2003 | B2 |
7221216 | Nguyen | May 2007 | B2 |
Number | Date | Country | |
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20070222507 A1 | Sep 2007 | US |
Number | Date | Country | |
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60785105 | Mar 2006 | US |