This invention relates to a DC voltage regulator and particularly to a low drop-out (LDO) voltage regulator.
A DC voltage regulator provides to a load a well-specified and stable DC (‘direct current’) output voltage whose fluctuations from a nominal value are low compared to fluctuations of the power supply that is regulated. The operation of the regulator is based on feeding back an error signal whose value is a function of the difference between the actual output voltage and the nominal value, which is amplified and used to control current flow through a pass device (such as a power transistor) from the power supply to the load. The drop-out voltage is the value of the difference between the power supply voltage and the desired regulated voltage below which regulation is lost. A low drop-out voltage regulator continues to regulate the output voltage effectively until the power supply voltage reduces to a value close to the desired regulated value. A low drop-out voltage regulator is therefore particularly useful in applications where it is powered by the same power supply used to supply the load, since it continues to function almost until the power supply becomes too low to supply the load at the desired voltage in any case.
The low drop-out nature of the regulator makes it appropriate (over other types of regulators such as dc-dc converters and switching regulators) for use in many applications such as automotive, portable, and industrial applications with an internal power supply, especially a battery. In the automotive industry, the low drop-out voltage is necessary during cold-crank conditions where an automobile's battery voltage of nominally 12V can drop below 6V, for example. Demand for LDO voltage regulators is also apparent in hand held battery operated products (such as cellular phones, pagers, camera recorders and laptop computers).
A known LDO voltage regulator comprises a comparator, which is a differential voltage amplifier that produces the feedback error signal by comparing a voltage related to the output voltage to a reference voltage, an intermediate buffer stage responsive to the differential amplifier output, the pass device, and a bypass capacitor coupled to the load. These elements constitute a regulation loop which provides voltage regulation.
In many known LDO voltage regulators, the bypass capacitor has to have a large capacitance to ensure stability of the operation of the regulator, which is costly, especially since this usually requires the use of an external capacitor. Not only is the cost of the capacitor component itself higher if the component is larger but also the component occupies more space on the circuit board of the regulator. These factors are aggravated if a given device needs several voltage regulators. Moreover, design of the regulator is often complex, and the design complexity increases with the number of different poles in the regulator and with the effects of parasitic impedances and manufacturing tolerances.
There is a need for an LDO voltage regulator that alleviates some or all of the above disadvantages.
The present invention provides a low drop-out voltage regulator as described in the accompanying claims.
The differential amplifier 1 receives a BandGap reference voltage Vbg, on one differential input and on the other differential input receives a voltage proportional to the output voltage of the regulator from a voltage divider comprising two resistors R1 and R2 connected in series across the regulator output. The output voltage of the differential amplifier 1 at the connection between the PMOS transistor T2 and the NMOS transistor T4 is applied to the gate of the NMOS transistor T5 and the transistors T5, T6 then apply-this voltage to the gate of the pass device T7. These elements constitute a regulation loop which provides low drop-out DC voltage regulation of the output voltage applied to. the external bypass/load capacitor CL. The regulator is supplied with a supply voltage VSupply, for example from a battery, through a current source IS. The battery also supplies power to the load through the pass device T7 of the regulator.
The gain bandwidth GBW of the regulator is given by:
where A1 is the gain of the differential amplifier 1, A2 is the gain of the intermediate buffer 2, and gmp is the transconductance of the pass device T7.
It is found that, to ensure stability, the loop gain must be below 0 dB when the pole Fpint becomes influential and that the ESR ‘zero’ Zesr must be situated close to the pole Fpdiff. Both of these requirements necessitate a large value for the capacitance CL and, in a practical example of this regulator, the value of the capacitance CL is at least 10 μF per 100 mA of output current.
Some reduction in the bypass capacitance CL is obtained by the known regulator shown in
In addition, the regulator of
It is found that the AC feedback loop with the bypass capacitance Cf creates a very low frequency dominant pole in the DC feedback loop, so that the regulator is stable with smaller values of the bypass capacitor CL than in the regulator of
In operation, the first NMOS transistor 9 conducts the feedback current flowing in the parallel feedback paths of resistor 5 and capacitor 6 and maintains the voltage of the common point 7 substantially equal to the reference voltage Vref, due to the amplification of any voltage difference by the amplifier 8 applied to the gate of the first NMOS transistor 9. The same output voltage of the amplifier 8 applied to the gate of the second NMOS transistor 10 causes the second NMOS transistor 10 to conduct the same current. Any difference between the current (Vout−Vref)/R2 flowing in the second NMOS transistor 10, mirrored from the first NMOS transistor 9, and the current Vref/R1 from the current source 11 constitutes an error signal applied to the buffer 2. The connection 12 presents a high impedance, so that the error signal appears as an-error voltage.
The buffer 2 responds to the error signal at the connection 12 corresponding to any difference between the current (Vout−Vref)/R2 flowing in the second NMOS transistor 10, mirrored from the first NMOS transistor 9, and the current Vref/R1 from the current source 11. The feedback loop acts to modify the regulator output voltage Vout until the error signal is zero, when
The presence of the capacitive feedback path including the capacitor 6 forms a very low frequency, dominant pole in the feedback loop. The capacitive path is embedded in the current feedback structure so it has a larger bandwidth and one less pole than a capacitive loop in a voltage feedback structure. This improves the stability of the capacitive path and removes the peaking in the response of the feedback loop that is encountered with the regulator of
A small capacitor 13 in series with the conductive path of an NMOS transistor 14 are connected in parallel with the conductive path of the second transistor 10 between the connection point 12 and ground. The gate of the transistor 14 is connected to the connection point 12, so that the transistor 14 acts to present a low resistance that varies as a function of the voltage applied to the gates of the transistors Rz1 and T5, which varies as a function of the output current drawn by the load. The capacitor 13 and transistor 14 reduce the feedback loop gain at high frequencies, where poles due to parasitic capacitances are likely to appear.
ro1=equivalent resistance at the connection point 12, forming a high impedance node
Gmp=transconductance of the T7Pass Device
RL=resistance of the load 3
R2=resistance of the resistor 5
C2=capacitance of the capacitor 6
A2=gain of the inverting buffer 2
Tvtime constant of the pole formed by the current mirror pair 9 and 10 driven by the amplifier 8
T1=ro1.C1time constant of the pole formed by the capacitor 13 with the equivalent resistance ro1 at the connection point 12
Tz1=Rz1.C1time constant of the ‘zero’ formed by the capacitor 13 with the resistance Rz1 of the transistor 14 at the connection point 12
T2time constant of the pole formed by the inverting buffer 2
TL=RL.CLtime constant of the output pole including the load and the bypass capacitor CL
HT(s)=overall transfer function of the regulator observed by exciting the open-circuit resistive feedback path with the capacitive feedback path through the capacitor 6 active.
HR(S)=transfer function of the regulator observed by exciting the open-circuit resistive feedback path with the capacitive feedback path through the capacitor 6 open circuit
HC(s)=transfer function of the regulator observed by exciting the open-circuit capacitive feedback path with the resistive feedback path through the resistor 6 open circuit.
The overall transfer function is given by
s being the Laplace constant (jω=j.2πf).
At steady state, where s is substantially zero:
At low frequencies, that is to say slow changes in the signals, the values of T1.s, T2.s, TL.S, TV.s, and TZ1.s are all much smaller than 1 and Equation 3 reduces to:
The dominant pole is formed by the time constant A2.gmp.RL.ro1.C2 . As soon as the factor A2.gmp.RL.ro1.C2.s is much greater than 1, HT(S) tends towards
For frequencies below GBWC, where the transfer function of the capacitive feedback path falls to 0 dB, there is approximate cancellation between the poles of HR(S) and the poles of HC(s), producing a linear decline of HT(S) in a 1st order approximation. The frequency ranges where the 2nd and higher order influence of the poles Tv, T1, Tz1, T2, TL and Tz1 appears are indicated in
It is found that the capacitance of the bypass capacitor CL can be reduced very significantly compared to the regulators. of
Since the feedback current flows in the resistive feedback path and in the capacitive feedback path in parallel, and the capacitive feedback path forms a very low frequency dominant internal pole, all the sub-dominant poles of the regulator tend to be cancelled. It will be appreciated that this reduces the effect of complex poles, or even eliminates them in practice, increasing design robustness concerning regulation stability.
These factors simplify analysis and design of the regulator as overall constraints can be partitioned at sub-block level, reducing design cycle time.
Number | Date | Country | Kind |
---|---|---|---|
04290820.2 | Mar 2004 | EP | regional |
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/EP05/02819 | 3/15/2005 | WO | 9/15/2006 |