Patent Application
20120299564
1. Field of the Invention
This invention relates generally to voltage regulator circuits. More particularly, this invention relates to low dropout voltage regulator circuits. Even more particularly this invention relates to low dropout voltage regulator circuits having dynamic voltage control.
2. Description of Related Art
Battery powered applications such as smart-phones and tablet computers demand long battery life and therefore highly power efficient circuits. Often, the power supply voltage of digital circuits for the battery power applications must be adjusted during operation to minimize power consumption, since the power dissipated is proportional to the square of the power supply voltage. To achieve the required speed of operation, a certain minimum supply voltage is required. As demand fluctuates, so the supply voltage is adjusted as required.
The power supply for these types of circuits is often regulated down from the main battery by a voltage regulator, e.g. buck converter or linear regulator.
Buck regulators are generally power efficient but can consume a significant area and need bulky external components (inductors). These circuits are often used for higher load currents where the area of the control circuit is not significant compared with the size of the power switches.
However, for applications which require only a modest load current, the area penalty of a buck converter may be unacceptable. In such cases, the use of a low dropout voltage regulator (LDO) can be more area efficient although with some loss of energy efficiency.
A low dropout regulator is a class of linear regulator that is designed to minimize the saturation of the output pass transistor and its drive requirements. A low-dropout linear regulator will operate with input voltages only slightly higher than the desired output voltage.
An object of this invention is to provide a low dropout voltage regulator circuit that minimizes the power consumption of the load circuit by dynamically adjusting its output voltage.
To accomplish at least this object, a voltage regulation circuit has a voltage adjustment circuit that is in communication with a dynamic voltage controlling circuit for modifying an output voltage of the voltage regulation circuit. In various embodiments, the voltage adjustment circuit is a voltage digital-to-analog converter. A first amplification circuit is connected to receive an adjusted reference voltage from an output of the voltage adjustment circuit. The first amplification circuit is connected to receive an output feedback signal that is proportional to the output voltage of the voltage regulation circuit and from the differential of the adjusted reference voltage and the output feedback generates a voltage drive signal.
An output of the first amplification circuit is in communication with a signal input terminal of a follower output transistor to transfer the voltage drive signal to the follower output transistor. The follower output transistor has an input voltage terminal connected to receive a pre-regulated input supply voltage and an output terminal to provide the output voltage of the regulation circuit that is determined by the voltage to drive signal. The follower output transistor in some embodiments is a metal oxide semiconductor (MOS) field effect transistor (FET) and in other embodiments the follower output transistor is a bipolar transistor. In various embodiments the MOS FET is an N-type MOS FET. In various embodiments the bipolar transistor is an N-type bipolar transistor.
In various embodiments, a dynamic biasing circuit senses a load current through the follower output transistor and generates a dynamic biasing signal that is communicated to the first amplification circuit to modify the bandwidth of the first amplification circuit.
The output terminal of the follower output transistor is in communication with an adjustable internal load circuit. The adjustable internal load circuit is in communication with the dynamic voltage controlling circuits to apply a load current to the output terminal of the follower output transistor to increase the bandwidth of the voltage regulation circuit. The output voltage at the output terminal of the follower output transistor is modified by changing an output voltage level of the voltage adjustment circuit. In some embodiments, when the output voltage has been modified, the adjustable internal load circuit is disabled. In other embodiments, the load current of the adjustable internal load circuit is maintained at a level pending another modification of the output voltage level or a transient change in an external load. In still other embodiments, the load current of the adjustable internal load circuit is maintained at a lower level to conserve energy.
In various embodiments, the load current of the adjustable internal load circuit is a function of an output load capacitance connected to the output terminal of the follower output transistor. In other embodiments the load current of the adjustable internal load circuit is a function of a rate of modification of the output voltage level.
In some embodiments, the output of the first amplification circuit is connected to an input of a second amplification circuit. The input of the second amplification circuit is connected to a first terminal of a coupling capacitor. A second terminal of the coupling capacitor is connected to the output terminal of the follower output transistor to provide a feedback signal to the input of the second amplification circuit.
In various embodiments, an output of the second amplification circuit is connected to a buffer circuit to condition the output voltage level of the voltage adjustment circuit for driving the input terminal of the follower output transistor.
In various embodiments, the voltage regulation circuit is maintained at a quiescent state to conserve energy. When a request to modify the output voltage of the voltage regulation circuit is received, the load current of the adjustable internal load circuit is increased to increase the bandwidth of the voltage regulation circuit. The dynamic voltage controlling circuit commands that the voltage adjustment circuit modify the output voltage of the voltage regulation circuit. The voltage adjustment circuit adjusts the reference voltage to the first input of the first amplification circuit. The output of the first amplification circuit is changed to cause the output terminal of the follower output transistor to change the output voltage of the voltage regulation circuit. The dynamic voltage controlling circuit commands the adjustable internal load circuit to be disabled or to cause the load current of the internal load circuit to be decreased.
In other embodiments, a battery driven power supply includes a dynamic voltage control circuit in communication with external control circuitry to receive power level commands instructing the dynamic voltage control circuit to modify an output voltage level of the battery driven power supply to minimize energy usage from the battery. The dynamic voltage control circuit is in communication with a low drop out voltage regulation circuit to receive voltage level signals developed by the dynamic voltage control circuit from the power level commands. The low dropout voltage regulation circuit dynamically adjusts the output voltage level based on the voltage level signals. The low dropout voltage regulation circuit is connected to the battery. The low dropout voltage regulation circuit is further connected to a switching voltage regulator to provide a pre-regulated input voltage to generate the output voltage level. The switching voltage regulator is connected to the battery to generate the pre-regulated input voltage.
U.S. Pat. No. 6,856,124 (Dearn, et al.) describes a low dropout voltage regulator with wide output load range and fast internal loop. The circuit is internally compensated and uses a capacitor to ensure that the internal pole is more dominant than the output pole as in standard Miller compensation. The quiescent current is set to be proportional to the output load current. No explicit low power drive stage is required. The whole output range is covered by one output drive stage. This means the total consumption of quiescent or wasted current is reduced. An excellent power supply rejection ratio (PSRR) is achieved due to load dependent bias current. Dearn, et al. covers the basic low dropout voltage regulator architecture. However, the low dropout voltage regulator of Dearn, et al. is unable to dynamically change its output voltage.
What is needed is a low dropout voltage regulator circuit in which the output voltage can be dynamically increased or decreased in response to a system request. This increase or decrease must be achieved rapidly. The circuit requires no knowledge of the load current. High efficiency is achieved by using an input voltage which has already been pre-regulated from the battery voltage. For example, the pre-regulated input voltage may be developed by a switching converter which may already be present for other system tasks. This means that the total voltage drop across the linear regulator's output device can be kept small maintaining high power efficiency.
To minimize battery power consumption, the output voltage level of the low-dropout voltage regulation circuit is dynamically adjusted depending on system requirements. To respond to a system request to increase or decrease the output voltage rapidly, which is normally required, the low dropout voltage regulator needs to have a high bandwidth. This requires a high power dissipation. In the prior art, a dynamic bias scheme ensures that the quiescent current of the circuit is kept low and only increases as the load current increases, which ensures the internal circuit bandwidth (poles) track the output bandwidth (pole). It is apparent that a high circuit bandwidth is achieved only with a high output load current.
In most embodiments of this invention, the low dropout regulator does not require the output load current to be a particular value, but the circuit is forced into a high bandwidth state by applying an internal load current which increases the output pole. In various embodiments, the dominant pole of the low dropout regulator is increased via dynamic current sensing. Once this high bandwidth state is reached, the output voltage level is ramped up by changing the reference voltage output from a voltage adjustment circuit such as a voltage digital-to-analog converter. At the end of the adjusting of the output voltage level, the internal load current may be switched off to save power. In some embodiments, the internal load current may be maintained if another adjustment command is expected or a load transient is expected. In other embodiments, the internal load current may be maintained after the end of an adjustment of the output voltage level, but at a lower level. The internal load current for a modification of the output voltage level may be a function of the ramp rate required, the initial ramp voltage, or the end of ramp voltage. In other embodiments, the internal load current may be a function of the load capacitance. In some embodiments, the internal load current could be made a function of the system load current. The system load current is known from dynamic bias sense circuitry.
In various embodiments, the low dropout voltage regulator has a controlled ramp-rate from zero volts to the initial output target voltage during a power initialization by dynamically controlling the voltage adjustment circuit and the internal load current.
In the prior art, the output transistor is a common source or common emitter configured amplifier. The pre-regulating of the input voltage from the battery voltage reduces the gate-to-source (base-to-emitter) drive available to the output transistor. In the embodiments, a follower output transistor (source follower or emitter follower) is configured with a current mirror drive stage. The higher battery supply voltage is used to provide a high drive to the input terminal (gate or base) of the output transistor such that the output transistor maintains its area small.
In some embodiments the output transistor is a source follower configured metal oxide semiconductor (MOS) field effect transistor (FET) or an emitter follower configured bipolar transistor. In various embodiments, the MOS FET is an N-type MOS FET. In other embodiments, the bipolar transistor is an NPN bipolar transistor.
The buffer 215 acts as the current mirror for the NMOS follower output transistor 220.
Return now to
The internal current output of the adjustable internal load current source 225 is maintained at a level pending another modification of the output voltage level or a transient change in the external load current 130. In still other embodiments, the load current of the adjustable internal load current source 225 is maintained at a lower level to conserve energy. The load current of the adjustable internal load current source 225 may be a function of the output load capacitance 140. In other embodiments the load current of the adjustable internal load current source 225 is a function of a ramp rate of the modification of the output voltage level.
To minimize the energy consumption from the battery 100, the output voltage level Vout of the low dropout voltage regulator 105 is dynamically adjusted depending on system requirements. To respond to the system request to increase or decrease the output voltage at a fast rate the low dropout voltage regulator 105 needs to have a high bandwidth. To minimize the power dissipation a dynamic bias sensing circuit 230 ensures that the quiescent current of the circuit is kept low and only increases as the load current increases. This ensures the internal circuit poles track the output pole. To accomplish this, the dynamic bias sensing circuit 230 senses the current flowing through the NMOS output transistor 220 and modifies the current applied from the battery 100 to the first amplifier gain stage 200.
The drain of the PMOS transistor MP1 is connected to the diode connected load NMOS transistor MN1. The drain of the PMOS transistor MP2 is connected to the load NMOS transistor MN2. The gates of the NMOS transistor MN1 and the NMOS transistor MN2 are connected together and to the drain of the PMOS transistor MP1. The sources of the NMOS transistor MN1 and NMOS transistor MN2 are connected to the ground reference voltage. The drains of the PMOS transistor MP2 and the NMOS transistor MN2 are connected to the input of the second amplifier gain stage 210 of
The embodiments of the low dropout voltage regulator 105 as shown are adjusted by activating the adjustable internal load current source 225. The dynamic biasing sensing circuit 230 senses the change in the current flowing through the NMOS output transistor 220 and adjusts the dynamic bias current source IDB of the first amplifier gain stage 200 to increase the bandwidth of the first amplifier gain stage 200. The dynamic voltage control 110 adjusts the voltage digital-to-analog converter 205. The output of the first amplifier gain stage 200 adjusts the drive signal for the NMOS output transistor 220 to adjust the output voltage Vout at the output terminal 135 of the low dropout voltage regulator 105.
While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 11392004.5 | May 2011 | EP | regional |
U.S. patent application Ser. No. 10/191,491, filed on Jul. 9, 2002, issued as U.S. Pat. No. 6,856,124 (Dearn, et al.), Feb. 15, 2005, assigned to the same assignee as the present invention, and incorporated herein by reference in its entirety.
