TECHNICAL FIELD
This disclosure relates to voltage regulators, and, more particularly, to a low drop out voltage regulator with an improved response to load variations and reduced power consumption, and a related method of generating a regulated voltage.
BACKGROUND
Low drop out (LDO) regulators are devices that provide a nominal and stable DC voltage by adjusting their internal resistance to any occurring variation of a supplied load. Because of their functioning characteristics, LDO regulators may be embedded in power management ICs for collecting energy to adapt power interfaces between an energy storage device, such as a battery or a supercapacitor, and loads functioning with a low duty cycle. Microprocessors, analog sensors and RF transceivers are example loads functioning with a low duty cycle.
To meet these requirements, power management ICs maximize power transfer from an energy collecting source to a battery and to a supplied load, and reduce power consumption. Power consumption is reduced particularly during stand-by periods due to the low duty cycle of the supplied loads.
Furthermore, load currents may vary from values below 1 μA, in stand-by conditions, to several tens of mA during data processing and transmission. For this reason, another requirement for LDO regulators in energy collecting applications is a fast response to load variations with reduced undershoots and overshoots to avoid an unwanted reset of the supplied load (e.g., a microprocessor).
A well-known basic linear voltage regulator is depicted in the block scheme of FIG. 1a and in the corresponding circuit of FIG. 1b. The linear voltage regulator comprises an error amplifier ErrAmp configured to receive as an input a reference voltage Vref, typically generated by a band-gap circuit, and a feedback voltage Vfb. The feedback voltage Vfb represents the output voltage Vout_pch, and is configured to control a pass transistor Tpass, typically a PMOS enhancement FET. The pass transistor Tpass is biased in a conduction state to regulate the output voltage Vout_pch so as to make the feedback voltage Vfb match the reference voltage Vref. The amplifier may be a differential amplifier with an active load, as shown in FIG. 1b. The response to load variations of this basic regulator is relatively slow, and this may make it practically unsuitable for energy collecting applications.
Another known regulator is illustrated in the block scheme of FIG. 2a and in the corresponding circuit of FIG. 2b. In this regulator, the powering voltage Vboost of the error amplifier ErrAmp is a boosted replica of the supply voltage VDD. This causes the pass NMOS transistor Tpass to function in the linear functioning region of its current-voltage characteristic when the output regulated voltage Vout_nch is close to the supply voltage VDD. The boosted powering voltage Vboost is typically generated by a charge pump generator CHARGE PUMP controlled by an oscillator operating at a fixed frequency. The amplifier may be a differential amplifier with an active load, as shown in FIG. 2b, in which the voltages Vref and Vfb are applied to the input terminals of the amplifier to properly drive the NMOS pass transistor Tpass.
This regulator is characterized by a fast response to load variations due to the reduced size of the load supplying NMOS transistor. This is done at the cost of greater power consumption in inactive conditions due to the presence of a charge pump generator, which may make it unsuitable for energy collecting applications.
A low drop out (LDO) regulator capable of combining the contrasting requirements of a short transient response to load variations with a very small power consumption may be advantageous for realizing energy collecting devices with reduced power consumption, and thus with improved yield.
SUMMARY
An operational transconductance amplifier (OTA) powered with the supply voltage of the regulator may be used for generating an intermediate current representing a difference between a reference voltage and a feedback voltage. A current-to-voltage amplification stage powered with a boosted voltage available on a high voltage line may be used to generate the driving voltage of the pass transistor that provides the regulated output voltage.
The operational transconductance amplifier may be a differential amplifier with an active load.
The boosted voltage may be generated by a feedback charge pump generator having a voltage controlled oscillator (VCO) controlled by the boosted voltage to reduce the oscillation frequency of the VCO as the boosted voltage approaches its nominal value.
The LDO regulator may be realized with MOS transistors and/or with BJT transistors.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1
a and 1b depict a voltage regulator and a circuit implementation thereof, respectively, according to the prior art.
FIGS. 2
a and 2b depict another voltage regulator and a circuit implementation thereof, respectively, according to the prior art.
FIGS. 3
a and 3b depict an embodiment of the LDO regulator and an exemplary circuit implementation thereof, respectively, according to the present disclosure.
FIG. 4 compares output voltage responses of the regulators of FIGS. 1 to 3 after an abrupt increase of the output current according to the present disclosure.
DETAILED DESCRIPTION
An embodiment of the LDO regulator of the present disclosure is depicted in FIG. 3a, and an exemplary circuit scheme thereof realized with MOS technology is illustrated in FIG. 3b. Corresponding circuit blocks in the figures have the same references. The same circuit may be realized with BJT technology, as readily appreciated by those skilled in the art.
The regulator comprises a charge pump generator CHARGE PUMP that provides a boosted voltage Vboost, though what will be stated below also holds if the boosted voltage Vboost is made available to the LDO regulator on a high voltage line but is generated by a device not belonging to the LDO regulator.
Differently from the known voltage regulator of FIG. 2a, the regulator disclosed herein includes an operational transconductance amplifier supplied with the supply voltage VDD that generates an intermediate current corresponding to the voltage unbalance between the reference voltage Vref and the feedback voltage Vfb. A current-to-voltage amplification stage, powered with a boosted voltage available on a high voltage line, generates a driving voltage of the pass transistor Tpass that is increased or decreased by an amount corresponding to the value and the sign of the intermediate current delivered by the operational transconductance amplifier OTA.
The current-to-voltage amplification stage draws a nonnull current from the high voltage line at the boosted voltage for charging/discharging the gate of the output pass transistor Tpass only during output load transients. When the load is stable and all transients have ceased, the charging/discharging current of the gate of the pass transistor Tpass nullifies and thus no current is drawn from the high voltage line.
Therefore, the charge pump generator in the embodiment of FIG. 3b generates the boosted voltage but does not deliver any current during an inactive condition. This is different from the voltage regulator of FIG. 2b, and as a result, power consumption is reduced. Therefore, the current consumption in inactive functioning conditions is practically the same as in the regulator of FIG. 1a, but the transient responses after an abrupt increase of the current absorbed by a supplied load are relevantly faster because the pass transistor is an N-type transistor.
According to an example embodiment, the pass transistor Tpass is an NMOS transistor. The transient response after an abrupt increase of the output current may even be shorter than that of the prior regulator of FIG. 2a.
FIG. 4 depicts exemplary time graphs of simulations of the circuits of FIGS. 1b, 2b and 3b. The regulator of FIG. 1b is the slowest because its pass transistor Tpass is an enhancement PMOS transistor, thus it is larger than an NMOS transistor with the same on resistance. Therefore, the NMOS pass transistor Tpass of the present LDO regulator requires a smaller charging/discharging current for obtaining the same transient performance than a PMOS transistor. Furthermore, the source follower NMOS pass transistor topology has intrinsically better performance in voltage buffer applications than the PMOS pass transistor common source topology.
The regulator of FIG. 3b is even faster than that of FIG. 2b. This is due to the fact that the overall gain of the disclosed LDO regulator is greater than the loop gain of the regulator of FIG. 2b using components having the same size. This is because the former is the product of the gain of the operational transconductance amplifier OTA by the gain of the current-to-voltage amplification stage. Therefore, using a current-to-voltage amplification stage with a gain >1, the current for charging/discharging the gate of the pass transistor is amplified with respect to the maximum current provided by the OTA. This improves the transient response without increasing an inactive condition power consumption of the LDO regulator.
The current-to-voltage amplification stage of FIG. 3a controls the pass transistor Tpass and may be realized as shown in FIG. 3b, but other architectures may be used provided that they are adapted to generate a voltage that is increased or decreased by an amount that corresponds to the sign and to the intensity of the intermediate current.
The current-to-voltage amplification stage as shown in FIG. 3b includes low-side and high-side current mirrors. The low-side current mirror includes an output transistor. Similarly, the high-side current mirror includes an output transistor. A pair of complementary transistors is coupled together in series. The pair of complementary transistors is coupled to the operational transconductance amplifier (OTA) such that the intermediate current flows through a respective transistor of the pair of complementary transistors based on a sign of the intermediate current from the operational transconductance amplifier. The pair of complementary transistors is also coupled to a voltage reference through the low-side current mirror and is coupled to the high voltage line through the high-side current mirror. The low-side and high-side current mirrors are configured to mirror a current flowing through a respective transistor of the pair of complementary transistors. The output transistors of the low-side and high-side current mirrors are coupled together in series, and with the driving voltage being made available on a common current terminal shared by the output transistors of the low-side and high-side current mirrors.
According to a further innovative characteristic of the embodiment shown in FIG. 3a, the boosted voltage is generated by a feedback charge pump generator CHARGE PUMP driven by a voltage controlled oscillator (VCO). The frequency of the VCO is adjusted as a function of the value of the boosted voltage Vboost effectively made available on the high voltage line. The frequency of the VCO is increased the more the boosted voltage drops below its nominal value. This feature may be particularly useful for reducing further power losses because it allows a reduction of the switching frequency of the charge pump generator, as determined by the oscillation frequency of the VCO, when there is no load transient.
Patent Grant
9223329
