Low drop-out voltage regulator

Abstract

A low drop-out voltage regulator having a pass device (Mp), an error amplifier (M1-M51) and a double regulation loop including DC feedback loop (R1, R2) and an AC feedback loop (Rf, Cf) including a high pass filter (Cf). Combining these two loops creates an ultra low frequency internal pole which makes the regulator stable substantially independent of the output bypass capacitor's value. This provides the following advantages: allows the use of very low bypass capacitors; allows to extend the PSRR frequency behavior; allows an increase in the regulator's efficiency (reduced power consumption on heavy loads).

Description

FIELD OF THE INVENTION

This invention relates to voltage regulators, and particularly to low drop-out (LDO) voltage regulators.

BACKGROUND OF THE INVENTION

A low drop-out voltage regulator is a regulator circuit that provides a well-specified and stable DC voltage (whose input-to-output voltage difference is typically low). The operation of the circuit is based on feeding back an amplified error signal which is used to control output current flow of a pass device (such as a power transistor) driving a load. The drop-out voltage is the value of the input/output differential voltage where regulation is lost.

The low drop-out nature of the regulator makes it appropriate (over other types of regulators such as dc-dc converters and switching regulators) for use in many applications such as automotive, portable, and industrial applications. In the automotive industry, the low drop-out voltage is necessary during cold-crank conditions where an automobile's battery voltage can be below 6V. Increasing demand for LDO voltage regulators is also apparent in mobile battery operated products (such as cellular phones, pagers, camera recorders and laptop computers), where the LDO voltage regulator typically needs to regulate under low voltage conditions with a reduced voltage drop.

A typical, known LDO voltage regulator uses a differential transistor pair, an intermediate-stage transistor, and a pass device coupled to a large (external) bypass capacitor. These elements constitute a DC regulation loop which provides voltage regulation.

Depending on the application, a critical component of the regulator is often its bypass capacitor. Indeed, to ensure stability under all operating conditions, large values of capacitor are used. This translates into large area on the PCB on which the regulator circuit is built, and higher costs.

However, this known LDO voltage regulator has the disadvantages that it is difficult (i) to significantly reduce the bypass-capacitor below approximately 1 μF per 10 mA output current capability, and (ii) to significantly increase the PSRR frequency behavior without high increase of power consumption.

A need therefore exists for a low drop-out voltage regulator wherein the abovementioned disadvantage(s) may be alleviated.

STATEMENT OF INVENTION

In accordance with the present invention there is provided low drop-out voltage regulator as claimed in claim 1.

At least in a preferred form, the present invention allows the use of capacitors lower than 1 μF overall, allowing costs to be significantly reduced, and ensures good stability (even if no external output capacitor is used—providing the most cost-efficient solution for applications where the transient response of the regulator is not a critical requirement). Also, since low capacitors have low serial resistance, the design of the LDO is made easier. In a preferred form the invention achieves such performance without increasing the overall power consumption of the LDO voltage regulator.

BRIEF DESCRIPTION OF THE DRAWINGS

One low drop-out regulator incorporating the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 shows a block-schematic circuit diagram of a typical, classical low drop-out voltage regulator;

FIG. 2 shows a block-schematic circuit diagram of a simplified practical implementation of the LDO voltage regulator of FIG. 1;

FIG. 3 shows a block-schematic circuit diagram illustrating the open-loop AC-model of the LDO voltage regulator of FIG. 2;

FIG. 4 shows a graphical illustration of the stability of the LDO voltage regulator of FIG. 2 under conditions of varying load;

FIG. 5 shows a block-schematic circuit diagram of an LDO voltage regulator incorporating the present invention;

FIG. 6 shows a block-schematic circuit diagram illustrating the open-loop AC model of the LDO voltage regulator of FIG. 5; and

FIG. 7 shows a graphical illustration, similar to FIG. 4, of the open-loop performance of the LDO voltage regulator of FIG. 5.

DESCRIPTION OF PREFERRED EMBODIMENT(S)

A classic, known low drop-out regulator is depicted in FIG. 1. It is partitioned into 3 main parts: Pass-device (MOS transistor M_p—having transconductance G_M(P) and resistance R_dsp), error amplifier (A(p)) and resistor feedback (R₁, R₂). The pass-device M_p is used as a current-source, which is driven by the error amplifier (A(p)) to pass a current I_I from an input voltage V_I. The output voltage V_O is divided by the resistor ladder R₁, R₂ and compared with reference voltage V_REF. The current in the pass-device M_p is controlled according to this difference. Bypass capacitor C_L (having electrical series resistance E_SR) is connected to the the output, and output resistance of the load is represented by R_L⁻. The output voltage is given by:

$\begin{array}{cc}{V}_O=V_{\mathrm{REF}}\left(1+\frac{R_1}{R_2}\right)& \left(1\right)\end{array}$

To obtain a low drop-out voltage, a PMOS pass device is the most convenient transistor for power management applications.

Most low-dropout regulators designs use the regulation architecture combined with pole-tracking. Even if topologies are changing to improve a given specification requirement, pole tracking is a common and an efficient design technique. Indeed, to prevent instability due to changes of the output current, a local feedback is used to perform a tracking between the output pole and the pole of the intermediate stage. FIG. 2 shows a simplified schematic of a practical implementation of the LDO voltage regulator of FIG. 1, typically used for wireless applications. In the circuit of FIG. 2, the differential pairs of MOS transistors M₁-M₄ constitute the first stage of the amplifier and drive an intermediate stage M₅, M₆, M₅₁. The amplifier has an input stage constituted by MOS transistors M₁₁ and M₁₂ producing a current I_T, and is biased by a current source producing a bias current I_BIAS.

Pole-tracking is implemented using the current mirror between M_P and M₆. By feeding a part of the current of the pass-device in the intermediate stage, the impedance and the pole of this stage tracks the output impedance/pole. However, although it is easier to stabilize the regulator of FIG. 2 under variations in load current I_LOAD using the pole tracking scheme, the inventors of the present invention have recognized that the problem of stability regarding variations of E_SR is still unsolved since there is no means to sense the value of this serial resistance.

The absolute stability of a regulator is an implicit specification, which is the root cause of many trade-offs in designing the regulator. Before considering the stability of the regulator in more detail, its open-loop frequency response must be calculated.

FIG. 3 shows the AC model of the low drop-out regulator of FIG. 2. In the model of FIG. 3, the low drop-out regulator of FIG. 2 is modeled as follows:

• • the differential stage (transistors M₁-M₄) is modeled by an amplifier of gain −g_m1, a resistor R_o1 and a capacitor C_o1;
  • the intermediate stage (transistors M₅, M₆, M₅₁) is modeled by an amplifier of gain −g_m2, a resistor R_o2 and a capacitor C_gs;
  • the pass device M_p is modeled by the capacitor C_gs, a voltage controlled current source driven by a voltage V_gs and a resistor R_dsp;
  • the load section is modeled by the resistor E_SR and capacitor C_L and the resistor R_L; and
  • the feedback loop is modeled by the resistors R₁ and R₂.

The open-loop gain of this model is:

$\begin{array}{cc}\mathrm{OpenLoopGain}\left(s\right)=\frac{N_{\mathrm{OLG}}\left(s\right)}{D_{\mathrm{OLG}}\left(s\right)}& \left(2\right)\end{array}$ whereN_OLG(s)=−R₂g_m1r_o1g_m2r_o2g_mpR_S(1+E_SRC_Ls)D_OLG(s)=(R₁+R₂)(1+R_o1C_o1s)(1+R_o2C_gss)(1+(E_SR+R_s)C_Ls) andR_S=(R₁+R₂)//R_L//R_dsp, ‘//’ indicating ‘in parallel’.

The open-loop DC gain of the model is:

$\begin{array}{cc}{A}_{\mathrm{OL}}\left(\mathrm{DC}\right)=\frac{R_2}{R_1+R_2}{g}_{\mathrm{m1}}{r}_{\mathrm{o1}}{g}_{\mathrm{m2}}{r}_{\mathrm{o2}}{g}_{\mathrm{mp}}{R}_s& \left(3\right)\end{array}$

The system has 3 poles and 1 zero. The main pole is the pole of the output stage:

$F_{\mathrm{OUT}}=\frac{1}{2\pi \left(E_{\mathrm{SR}}+R_S\right)C_L}$

E_SR is low compared to R_S and can be neglected. It can be seen that this pole is a function of the load, which means that it changes with the load current. The relation is direct proportional and the pole-frequency increases directly with the output current. It should be noted that the low-frequency gain of the output stage is given by the equation:A_outputstage(DC)=g_mpR_S∝g_mpR_S

It is also a function of the output current, but the relation is different to that of the pole. G_m changes with the square root of the load current. R_L, which represents the load current, varies directly with the current. This means that the gain decreases with the square root of the load current. Finally, when the output current increases, the output pole increases faster than the open-loop gain decreases. Depending on the design and the operating conditions, the pole of the differential stage is placed before or after that of the intermediate stage:

$F_{\mathrm{pdiff}}=\frac{1}{2\pi R_{\mathrm{o1}}{C}_{\mathrm{o1}}}$ $F_{\mathrm{pint}}=\frac{1}{2\pi R_{\mathrm{o2}}{C}_{\mathrm{gs}}}$

The zero is created by the E_SR of the output capacitor:

$Z_{\mathrm{ESR}}=\frac{1}{2\pi E_{\mathrm{SR}}{C}_L}$

It is obvious that such a system can be unstable under certain conditions. To simplify the study of the stability, the problem is split into 2 cases:

• • E_SR is constant and the output current varies, and
  • the output current is constant and E_SR varies.

F_pout is the main pole and varies with the output current. If I_LOAD is minimum F_pout is placed at low-frequencies. At the opposite extreme, when I_LOAD is maximum, F_pout is a high-frequency pole. FIG. 4 depicts the problem of stability, when the output current goes from its minimum to its maximum value (minimum value of the current in the pass-device is set by the feedback resistor). These curves show that if the system is stable under low-load conditions, it is not stable when the regulator operates under heavy-load conditions. Indeed, when changing from low to heavy load, the open-loop DC gain A_OL decreases proportionally with the square-root of the current in the pass-device, but the output pole is pushed toward high-frequencies proportionally to this current. This is why the frequency response crosses the 0 dB-axis with a slope of −40 dB/decade leading to the instability of the system. This analysis explains the use of the pole-tracking scheme implemented in most of regulators.

The effect of the pole tracking is depicted in FIG. 4. By pushing F_pint toward high-frequencies proportionally to the output current, the 0 dB-axis is now crossed with a slope of −20 dB/decade.

It may be noted that since the zero due to E_SR and the poles of the differential pair and the intermediate stage are constant, the gain between the frequencies Z_ESR and F_pdiff is higher under heavy-load conditions than for low-load conditions, explaining why the stability is more critical under heavy-load operations.

Referring now to FIG. 5, a new, improved LDO voltage regulator adds an extra feedback loop to the classical architecture (e.g., FIG. 2). Compared with the prior art LDO of FIG. 2, the LDO of FIG. 5 includes additional MOS transistors M_2B, M₂₁ and M₂₂, together with capacitor C_F (and resistor R_F through which reference voltage V_REF is applied). The LDO regulator circuit as shown in FIG. 5 is typically fabricated substantially entirely (the portion within the dashed line) in integrated circuit form, only the bypass capacitor and load (represented by the components E_SR, C_L and R_L) being external to the integrated circuit.

The LDO of FIG. 5 thus includes a feedback loop (as in the prior art LDO of FIG. 2) formed by R₁, R₂ and the differential pair M₁₁, M₁₂. Additionally, the LDO of FIG. 5 includes an extra feedback loop containing R_F, C_F and the second differential pair M₂₁, M₂₂. Due to the high-pass filter formed by R_F and C_F this additional feedback does not act at DC but in middle-frequencies; it helps to regulate the output voltage and to stabilize the system. A large value for R_F is implemented by using an integrated resistor or a depletion transistor with a large length.

As will be discussed in more detail below, Combining these two feedback loops creates an ultra low frequency internal pole which makes the regulator stable, substantially independent of the value (or, with particular applicability to applications where the transient response of the regulator is not a critical requirement, even the absence) of the output bypass capacitor. Also, since low capacitors have low serial resistance, the design of the LDO is made easier. Further, it will be understood that, thanks to the high pass filter provided by C_F, the extra feedback loop increases the PSRR for high frequencies.

The system of FIG. 5 has two loops which have to be opened and analyzed separately. Using a simplified AC-model such as depicted in FIG. 6, the poles and zeroes of the main loop can be found.

As shown in FIG. 6, the LDO of FIG. 5 is modeled as follows:

• • the differential stages of transistors M₁-M₄, M₂₁ & M₂₂ and M₁₁ & M₁₂ are modeled by amplifiers of gain −g_m21 & −g_m11, a resistor R_o1 and a capacitor C_o1;
  • the intermediate stage (transistors M₅, M₆, M₅₁) is modeled by an amplifier of gain −g_m2, a resistor R_o2 and a capacitor C_gs;
  • the pass device M_p is modeled by the capacitor C_gs, a voltage controlled current source driven by a voltage V_gs and a resistor R_dsp;
  • the load section is modeled by the resistor E_SR and capacitor C_L and the resistor R_L;
  • the main feedback loop is modeled by the resistors R₁ and R₂; and
  • the AC feedback loop is modeled by R_F and C_F.

The open-loop gain at DC for the main loop is:

$\begin{array}{cc}{A}_{{\mathrm{OL}}_{\mathrm{MAIN}\text{-}\mathrm{LOOP}}}\left(\mathrm{DC}\right)=\frac{R_2}{R_1+R_2}{g}_{\mathrm{m11}}{r}_{\mathrm{o1}}{g}_{\mathrm{m2}}{r}_{\mathrm{o2}}{g}_{\mathrm{mp}}{R}_s& \left(4\right)\end{array}$

Equation (4) clearly shows that the DC performance-of the LDO of FIG. 5 is not impacted by the extra feedback loop.

The main loop has now 2 zeroes instead of 1 in the classical configuration of FIG. 2, and 4 poles instead of 3. With this new structure, the first pole is now:

$P_1=\frac{1}{2\pi A_2{R}_F{C}_F}\mathrm{with}{A}_2=g_{\mathrm{m21}}{r}_{\mathrm{o1}}{g}_{\mathrm{m2}}{r}_{\mathrm{o2}}{g}_{\mathrm{mp}}{R}_s$

The low-frequency zero is created by the high-pass filter:

$Z_2=\frac{1}{2\pi R_F{C}_F}$

It is followed by two (real or complex) poles P₂, P₃ related to the second order term:

$1-Z_{4}s+\frac{Z_4^2{T}_2}{T_2-Z_4}{s}^2$

The previous location of poles and zeroes clearly shows that the extra feedback loop creates a very low frequency pole which is internal while reducing the effect of the output stage on the regulator's stability. If A₂ is large enough, the pole-tracking scheme is no longer required. Finally, the power consumption at full load is improved.

This very low-frequency pole related to the new LDO of FIG. 5 implies a very good phase margin of the system with high output currents and very low output capacitors. The locations of the new poles and zeroes are depicted FIG. 7, which shows the open-loop gain of the DC-feedback loop without (lower line) and with (upper line) a frequency-peak.

The stability of the extra feedback loop may be analysed from the following expression for the open-loop gain of the extra feedback loop:

$A_{{\mathrm{OL}}_{2\mathrm{nd}-\mathrm{LOOP}}}\left(s\right)=\frac{A_{{\mathrm{OL}}_{\mathrm{MAIN}-\mathrm{LOOP}}}\left(\mathrm{DC}\right)·\left(R_F{C}_{F}s\right)·\left(1+E_{\mathrm{SR}}{C}_{L}s\right)}{\begin{array}{c}\left(1+R_F{C}_{F}s\right)·\left(1+\left(E_{\mathrm{SR}}+\frac{R_F}{A_1}{C}_{L}s\right)R_F{C}_{F}s\right)·\\ \left(1+\left(\frac{R_S·R_{02}}{A_1{E}_{\mathrm{SR}}+R_S}\right)C_{\mathrm{gs}}s\right)·\left(1+R_{01}{C}_{01}\right)\end{array}}$ $\mathrm{where}{A}_{{\mathrm{OL}}_{2\mathrm{nd}-\mathrm{LOOP}}}\left(\mathrm{DC}\right)=g_{\mathrm{m21}}{r}_{01}{g}_{\mathrm{m2}}{r}_{02}{g}_{mp}{R}_s$ $\mathrm{and}{A}_1=\frac{R_2}{R_1+R_2}{g}_{\mathrm{m11}}{r}_{01}{g}_{\mathrm{m2}}{r}_{02}{g}_{mp}{R}_s$

The locations of the poles and zeroes and the stability analysis can be deduced from the above equation for A_OL2nd-LOOP(s).

It will be appreciated that, due to the capacitor C_F, the extra feedback loop provides only AC feedback. As previously explained, this loop acts at middle frequencies. Since the feedback voltage is directly taken at the output of the regulator, this new arrangement provides an increase in the bandwidth of the PSRR.

It will be understood that the improved low drop-out regulator described above provides the following advantages:

• • Allows the use of very low bypass capacitors (which, with particular applicability to applications where the transient response of the regulator is not a critical requirement, may even be absent). Also, since low capacitors have low serial resistance, the design of the LDO is made easier.
  • Allows extended bandwidth of PSRR frequency behavior.
  • Allows increased regulator efficiency (reduced power consumption with heavy loads).

Claims

1. A low drop-out voltage regulator comprising: pass means for controlledly passing a current from an input voltage applied thereto to produce a controlled output voltage;feedback means, including a DC first feedback loop coupled to the regulator output, for providing a feedback signal representative of the output voltage there at; anderror amplifier means for comparing the feedback signal with a predetermined voltage and for producing a signal in dependence on the comparison for controlling the pass means;the feedback means also includes an AC second feedback loop coupled to the regulator output, and arranged in parallel with the DC first feedback loop, for operating in combination with the DC first feedback loop.

2. The low drop-out voltage regulator of claim 1 wherein the AC feedback loop includes a high pass filter.

3. The low drop-out voltage regulator of claim 1 wherein the feedback voltage of the AC feedback loop is taken directly at the regulator's output.

4. The low drop-out voltage regulator of claim 1 wherein the AC feedback loop includes a large value resistor formed by an integrated resistor.

5. The low drop-out voltage regulator of claim 1 wherein the AC feedback loop includes a large value resistor formed by a depletion transistor with a large length.

6. An integrated circuit comprising a low drop-out voltage regulator of claim 1.

7. A low drop-out voltage regulator comprising: pass circuit for controlledly passing a current from an input applied thereto to produce a controlled output voltage;feedback circuit, including a DC first feedback loop coupled to the regulator output, for providing a feedback signal representative of the output voltage thereat; anderror amplifier circuit for comparing the feedback signal with a predetermined voltage and for producing a signal in dependence on the comparison for controlling the pass circuit;wherein the feedback circuit also includes an AC second feedback loop coupled to the regulator output, and arranged in parallel with the DC first feedback loop, for operating in combination with the DC first feedback loop.

8. The low drop-out voltage regulator of claim 7 wherein the AC feedback loop includes a high pass filter.

9. The low drop-out voltage regulator of claim 7 wherein the AC feedback voltage of the AC feedback loop is taken directly at the regulator's output.

10. The low drop-out voltage regulator of claim 7 wherein the AC feedback loop includes a large value resistor formed by an integrated resistor.

11. The low drop-out voltage regulator of claim 7 wherein the AC feedback loop includes a large value resistor formed by a depleting transistor with a large length.

12. An integrated circuit comprising a low drop-out voltage regulator of claim 7.