LOW DROPOUT CURRENT SOURCE

Abstract

Disclosed is a low dropout current source that includes a first field effect transistor (FET), a second FET having a drain that is an output for an output voltage and an output current, and a third FET, wherein a gate of the first FET is coupled to both a gate of the second FET and a drain of the third FET, and wherein a drain of the first FET is coupled to a source of the third FET. A differential amplifier has an inverting input coupled to the drain of the first FET, a non-inverting input coupled to the drain of the second FET and an amplifier output coupled to the gate of the third FET. A current reference is coupled between the drain of the third FET and a fixed voltage node. The current reference provides a reference current that is multiplied and output from the third FET.

Description

FIELD OF THE DISCLOSURE

Embodiments of the present disclosure relate to current sources that are usable to provide bias currents to circuits such as power amplifiers.

BACKGROUND

A complementary metal oxide semiconductor (CMOS) design for a power amplifier (PA) often includes an array of output current sources that supply a bias current for biasing a PA such that the PA operates within a desired operating region. FIG. 1 depicts a related art current source 10 having a first field effect transistor (FET) M1 that is coupled between a battery input VBATT and a typical current reference 12 that provides a reference current IREF. The typical current reference 12 is usually a bandgap type reference. The current reference is coupled between a drain of the first FET M1 and a fixed voltage node such as ground GND. The current source 10 also includes a second FET M2 that is coupled between the battery input VBATT and a PA bias network 14 that is modeled with a resistor R_L coupled in series with a first diode D1, which is coupled in series with a second diode D2. The PA bias network 14 is coupled between a drain of the second FET M2 and ground GND. A gate of the first FET M1 is coupled to a gate of the second FET M2. The second FET M2 is typically N times a physical size of the FET M1, wherein N is a natural number. Moreover, the gate and drain of the first FET M1 are coupled together, so that the first FET M1 and the second FET M2 are configured as a current mirror. In this way, the reference current IREF is mirrored as an output current IOUT that flows through the second FET M2. The output current IOUT is N times larger than the reference current IREF. For example, the reference current IREF is typically within a range of microamperes (μA), whereas the output current IOUT is typically within a range of milliamperes (mA). The output current IOUT flows from the second FET M2 and through the PA bias network 14. An output voltage VOUT can be measured across the PA bias network 14 with respect to ground GND.

In order to maintain an accurate output current IOUT, the second FET M2 should remain biased in a saturation region for all expected operating conditions such as supply voltage variations and temperature extremes. Typically, minimum voltage headroom available for the current source 10 is around 250 mV. For example, this minimum voltage headroom can occur when a voltage at the VBATT terminal is 3.0V and the output voltage VOUT is 2.75V. As a result, the second FET M2 must be made sufficiently large so that the second FET M2 remains in saturation for all expected operating conditions such as supply voltage variations and temperature extremes. For example, with an output current IOUT requirement of 3 mA, the die area required is on the order of 9600 micrometers (μm) by 2 μm, which occupies 0.19 mm². This amount of die area taken up by the second FET M2 is undesirable.

In addition, a reduced voltage specification for the voltage applied to the VBATT terminal, a change in a PA biasing network to increase a maximum VOUT, or an increase in the output current specification typically necessitates a complete re-design of a schematic and physical layout of a conventional current source such as the current source 10. Any of these changes would result in reduced voltage headroom available across the second FET M2, thereby preventing operation of the second FET M2 in the saturation region over all conditions. Operation outside the saturation region of the second FET M2 and inside the triode region of the second FET M2 causes the output current IOUT to be detrimentally sensitive to variations in voltage headroom. A fluctuating output current IOUT does not allow generation of stable and accurate bias currents needed for properly biasing PAs. Thus, there is a need for a low dropout current source that enables accurate operation of the low dropout current source down to approximately 75 mV of voltage headroom.

SUMMARY

The present disclosure provides a low dropout current source. The present disclosure also provides a method of supplying a constant current to a circuit such as a power amplifier of a mobile terminal.

In general, the low dropout current source includes a first field effect transistor (FET), a second FET having a drain that is an output for an output voltage and an output current, and a third FET, wherein a gate of the first FET is coupled to both a gate of the second FET and a drain of the third FET, and wherein a drain of the first FET is coupled to a source of the third FET. A differential amplifier has an inverting input coupled to the drain of the first FET, a non-inverting input coupled to the drain of the second FET and an amplifier output coupled to the gate of the third FET. A current reference is coupled between the drain of the third FET and a fixed voltage node. The current reference includes a temperature independent current source that is derived from a band-gap reference. Alternately, the current reference includes a temperature dependent current source that is derived from proportional to absolute temperature (PTAT) current sources. The current reference provides a constant current that flows through the first FET and the third FET.

In operation of the low dropout current source, the differential amplifier drives the gate of the third FET such that the voltage on the inverting terminal and an output voltage on the non-inverting terminal are equal. The output voltage can be measured across the PA bias network with respect to a fixed voltage node, which can be ground GND. As a result, the drain-to-source voltage (V_DS) for each of the first FET and the second FET are equal. Also, the first FET and the second FET are matched so that the gate-to-source voltage (V_GS) of each of the first FET and the second FET are equal during operation of the low dropout current source. Consequently, an output current flowing through the second FET is proportional to the reference current. Moreover, the output current that flows through the second FET remains at a constant current level as the second FET transitions from a saturation region operating point to a triode region operation point. Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1 is a schematic of a typical related art current source.

FIG. 2 is a schematic of a low dropout current source in accordance with the present disclosure.

FIG. 3 is a graph that compares the required voltage headroom between the typical related art current source and the low dropout current source of the present disclosure.

FIG. 4 is a graph that compares the required voltage headroom between the typical related art current source and the low dropout current source of the present disclosure after the physical size of an output FET is scaled down by a factor of twelve.

FIG. 5 is a block diagram depicting a mobile terminal that incorporates the low dropout current source of the present disclosure.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

FIG. 2 is a schematic of a low dropout current source 16 that is in accordance with the present disclosure. The low dropout current source 16 includes the first FET M1, the second FET M2 and the PA bias network 14. The source (S) of the first FET M1 and the source (S) of the second FET M2 are both coupled to a power source input, which can be the battery terminal VBATT. The PA bias network 14 is coupled between the drain of the second FET M2 and a fixed voltage node such as ground GND. However, the low dropout current source 16 differs from the related art current source 10 (FIG. 1) in that the low dropout current source 16 adds a differential amplifier 18, a third FET M3, and replaces the typical current reference 12 (FIG. 1) with a current reference 20. The differential amplifier 18 is powered via a power terminal VCC and ground GND. The differential amplifier 18 has an inverting input 22 coupled to the drain (D) of the first FET M1. The differential amplifier 18 also includes a non-inverting input 24 that is coupled to the drain (D) of the second FET M2. An output 26 of the differential amplifier 18 drives a gate of the third FET M3, which has a source (S) that is coupled to the drain (D) of the first FET M1. The current reference 20 is coupled between a drain (D) of the third FET M3 and the fixed voltage node that is depicted as ground GND in FIG. 2. The drain (D) of the third FET M3 is also coupled to the gate (G) of the first FET M1, which in-turn is coupled to the gate (G) of the second FET M2.

The current reference 20 includes a temperature independent current source that is derived from a band-gap reference (not shown). Alternately, the current reference 20 includes a temperature dependent current source that is derived from proportional to absolute temperature (PTAT) current sources (not shown). The current reference 20 provides a constant current IREF_PTAT that flows through the first FET M1 and the third FET M3.

In operation of the low dropout current source 16, the differential amplifier 18 drives the gate (G) of the third FET M3 such that the voltage on the inverting terminal 22 and the voltage VOUT on the non-inverting terminal 24 are equal. The output voltage VOUT can be measured across the PA bias network 14 with respect to the fixed voltage node, which as depicted in FIG. 2 can be ground GND. As a result, the drain-to-source voltage (V_DS) for each of the first FET M1 and the second FET M2 are equal. Also, the first FET M1 and the second FET M2 are matched so that the gate-to-source voltage (V_GS) each of the first FET M1 and the second FET M2 are equal during operation of the low dropout current source 16. Consequently, the current IOUT is a constant current that flows through the second FET M2, and is a multiple of a current level of the reference current IREF_PTAT flowing through the first FET M1. This current multiplication holds true even when the voltage V_DS across the second FET M2 is relatively small causing the second FET M2 to operate in the triode region.

FIG. 3 shows computer simulation results for the operation of the low dropout current source 16. In particular, FIG. 3 is a graph that compares the required voltage headroom between the typical related art current source 10 (FIG. 1) and the low dropout current source 16 (FIG. 2). Indirectly, the graph shows that a die area of the second FET M2 may be sized relative to the area of the first FET M1 to maintain a proportional relationship between the reference current IREF_PTAT provided by the current reference 20 and an output current flowing through the second FET M2 operating under a voltage headroom of around 75 mV.

FIG. 4 shows a computer simulation in a case in which a specified voltage headroom will not fall below a range of about 200 mV to about 250 mV. In this case, the particular configuration of the low dropout current source 16 (FIG. 2) allows a die area of the second FET M2 to be at least twelve times smaller than the die area needed for the second FET M2 as used in the typical related art current source 10 (FIG. 1).

FIG. 5 depicts the basic architecture of user equipment (UE) in the form of a mobile terminal 28 that incorporates an embodiment of the low dropout current source 16 of FIG. 2. In particular, the low dropout current source 16 is usable to bias a power amplifier 30 in the mobile terminal 28. The mobile terminal 28 may include a receiver front end 32, a radio frequency (RF) transmitter section 34, an antenna 36, a multi-band duplexer/switch 38, a baseband processor 40, a control system 42, a frequency synthesizer 44, and an interface 46. The receiver front end 32 receives information bearing radio frequency signals from one or more remote transmitters provided by a base station (not shown). A low noise amplifier (LNA) 48 amplifies the signal. A filter circuit 50 minimizes broadband interference in the received signal, while down conversion and digitization circuitry 52 down converts the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams. The receiver front end 32 typically uses one or more mixing frequencies generated by the frequency synthesizer 44. The baseband processor 40 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. As such, the baseband processor 40 is generally implemented in one or more digital signal processors (DSPs).

On the transmit side, the baseband processor 40 receives digitized data, which may represent voice, data, or control information, from the control system 42, which it encodes for transmission. The encoded data is output to the RF transmitter section 34, where it is used by a modulator 54 to modulate a carrier signal that is at a desired transmit frequency. The power amplifier 30 amplifies the modulated carrier signal to a level appropriate for transmission, and delivers the amplified and modulated carrier signal to the antenna 36 through the a power amplifier 30. The control system 42 controls an ENABLE signal that activates and deactivates the low dropout current source 16 as needed. For example, the control system 42 may activate the low dropout current source 16 in anticipation of a transmission event. Alternately, the control system 42 may deactivate the low dropout current source 16 to conserve energy.

A user may interact with the mobile terminal 28 via the interface 46, which may include interface circuitry 56 associated with a microphone 58, a speaker 60, a keypad 62, and a display 64. The interface circuitry 56 typically includes analog-to-digital converters, digital-to-analog converters, amplifiers, and the like. Additionally, it may include a voice encoder/decoder, in which case it may communicate directly with the baseband processor 40. The microphone 58 will typically convert audio input, such as the user's voice, into an electrical signal, which is then digitized and passed directly or indirectly to the baseband processor 40. Audio information encoded in the received signal is recovered by the baseband processor 40, and converted by the interface circuitry 56 into an analog signal suitable for driving the speaker 60. The keypad 62 and the display 64 enable the user to interact with the mobile terminal 28, input numbers to be dialed, address book information, or the like, as well as monitor call progress information.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A low dropout current source comprising: a first field effect transistor (FET) having a drain, a gate and a source, a second FET having a drain, a gate and a source, wherein the drain of the second FET is an output for an output voltage and an output current, and a third FET having a drain, a gate and a source, wherein the gate of the first FET is coupled to both the gate of the second FET and the drain of the third FET, and wherein the drain of the first FET is coupled to the source of the third FET;a differential amplifier having an inverting input coupled to the drain of the first FET, a non-inverting input coupled to the drain of the second FET and an amplifier output coupled to the gate of the third FET; anda current reference coupled between the drain of the third FET and a fixed voltage node.

2. The low dropout current source of claim 1, wherein the fixed voltage node is ground.

3. The low dropout current source of claim 1, wherein the source of the first FET and the source of the second FET are both coupled to a power source input.

4. The low dropout current source of claim 1, wherein the current reference includes a temperature independent current source that is derived from a band-gap reference.

5. The low dropout current source of claim 1, wherein the current reference includes a temperature dependent current source that is derived from proportional to absolute temperature (PTAT) current sources.

6. The low dropout current source of claim 1, wherein an area of the second FET is sized relative to an area of the first FET to maintain a proportional relationship between a reference current provided by the current reference and an output current flowing through the second FET operating under a voltage headroom of around 75 mV.

7. The low dropout current source of claim 1, wherein the output current that flows through the second FET remains at a constant current level as the second FET transitions from a saturation region operating point to a triode region operating point.

8. A mobile terminal comprising: a power amplifier (PA) for amplifying signals to be transmitted from the mobile terminal;a low dropout current source adapted to provide bias current to the PA, the low dropout current source comprising: a first FET having a drain, a gate and a source, a second FET having a drain, a gate and a source, wherein the drain of the second FET is an output for an output voltage and an output current, and a third FET having a drain, a gate and a source, wherein the gate of the first FET is coupled to both the gate of the second FET and the drain of the third FET, and wherein the drain of the first FET is coupled to the source of the third FET;a differential amplifier having an inverting input coupled to the drain of the first FET, a non-inverting input coupled to the drain of the second FET and an amplifier output coupled to the gate of the third FET; anda current reference coupled between the drain of the third FET and a fixed voltage node; anda control system for enabling and disabling the low dropout current source.

9. The mobile terminal of claim 8, wherein the fixed voltage node is ground.

10. The mobile terminal of claim 8, wherein the source of the first FET and the source of the second FET are both coupled to a power source input.

11. The mobile terminal of claim 8, wherein the current reference includes a temperature independent current source that is derived from a band-gap reference.

12. The mobile terminal of claim 8, wherein the current reference includes a temperature dependent current source that is derived from PTAT current sources.

13. The mobile terminal of claim 8, wherein the second FET is sized relative to the first FET to maintain a proportional relationship between a reference current provided by the current reference and an output current flowing through the second FET operating under a voltage headroom of around 75 mV.

14. The mobile terminal of claim 8, wherein an output current that flows through the second FET remains at a constant current level as the second FET transitions from a saturation region operating point to a triode region operating point.

15. A method of supplying a constant current to a circuit, comprising: providing a low dropout current source having a first FET, a second FET, a third FET, a current reference and a differential amplifier;generating a reference current with the current reference such that the reference current flows through both the first FET and the third FET;driving the third FET with the differential amplifier such that a drain-to-source voltage of the first FET is substantially equal to a drain-to-source voltage of the second FET; andmirroring the reference current that flows through the first FET to the second FET to provide the constant current that flows through the second FET and into the circuit.

16. The method of claim 15, wherein the current reference includes temperature compensation that is derived from a band-gap reference.

17. The method of claim 16, wherein the temperature compensation is further derived from PTAT current sources.

18. The method of claim 15, wherein the second FET is sized relative to the first FET to maintain a proportional relationship between a reference current provided by the current reference and the constant current that flows through the second FET operating under a voltage headroom of around 75 mV.

19. The method of claim 15, wherein operation of the second FET transitions from operation in a saturation region to operation in a triode region while maintaining a constant current level to the circuit.

20. The method of claim 15, wherein the constant current that flows through the second FET is a multiple of a current level of the reference current flowing through the first FET.