This application claims priority to Indian Provisional Application No. 201941015764, filed on Apr. 20, 2019, which is hereby incorporated by reference.
A low-dropout (LDO) voltage system regulates its voltage output to provide a consistent power drive to a load coupled to the LDO voltage system. Where voltage input varies, the LDO voltage system can provide a consistent voltage output that is minimally lower than the lowest of the varying voltage input. For instance, where the input voltage ranges from 2.2 V to 2.5 V, the LDO voltage system outputs a consistent voltage of 1.8 V.
A digital isolator provides isolation between circuits communicating with each other. Many electronic circuits include integrated circuits that operate using power supplies having a group voltage that is different from the ground voltage of other integrated circuits. The direct current (DC) isolation between communicating circuits is desirable to protect the components of each circuits, shift signal levels, adhere to safety regulations, etc.
The communication between the two isolated sides coupled through a digital isolator is accomplished using high-frequency modulated signals. When a digital isolator is coupled to the LDO voltage system as a load, the LDO voltage system drives a transceiver that generates the high-frequency modulated signals. To reduce the power consumption during the operation of the digital isolator, there is a need for a LDO voltage system that outputs varying size of load current to the transceiver that syncs with the generation of the high-frequency modulated signals.
According to an aspect of the present invention, a LDO voltage system with at least two operational mode is provided, wherein the at least two operational mode comprises a low mode that provides a low current to its load and a high mode that provides a high current to its load. In one example, the LDO voltage system operates in the high mode where a transceiver of a digital isolator generates a high-frequency modulated signal.
According to another aspect of the present invention, a LDO voltage system enters into a boost mode to transition from a low mode to a high mode to prepare for the generation of the high-frequency modulated signal by the transceiver.
According to another aspect of the present invention, a LDO voltage system enters into a boost mode or a high mode by adjusting a bias current of a MOSFET circuitry, where the MOSFET circuitry outputs a current forwarded to a load of the LDO voltage system as a load current. In one example, the bias current of the MOSFET circuitry is increased so that the LDO voltage system enters a boost mode or a high mode. The bias current of the MOSFET circuitry may be increased by opening and closing a switch connecting the transistors of the MOSFET circuitry.
For a detailed description of various examples, reference will now be made to the accompanying drawings in which:
In this description, the term “couple” or “couples” means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.
Input buffer 10 temporarily stores input data 31 provided to the isolator, and encoder 11, coupled to input buffer 10, generates encoded data 32 representing input data 31. As illustrated, encoded data 32 represents a rising edge of input data 31 by a single pulse of 10 ns and a falling edge of input data 31 by two consecutive pulses. Encoder 11 is driven by LDO voltage system 21.
Transceiver 12, coupled to encoder 11 and driven by LDO voltage system 21, generates a high-frequency modulated signal based on pulse signal 32. In the example of
Isolation barrier 13 comprises a capacitor. Receiver 14, coupled to isolation barrier 13 and driven by LDO voltage system 22, generates demodulated data 34 based on the operation of isolation barrier 13 driven by modulated signal 33. Demodulated data 34 is fed into one pulse detector 15 and two pulse detector 16. Decoder 17, coupled to one pulse detector 15 and two pulse detector 16, decodes demodulated data 34, which is temporarily stored in output buffer 18 before output as output data 35. One pulse detector 15 and two pulse detector 16 are each driven by LDO voltage system 22.
Transceiver 12 generates modulated signal 33 that represents encoded data 32. LDO voltage system 21 provides a regular load current to transceiver 12 during the period where encoded data 32 value is low. Flat portions 41 of modulated signal 33 correspond to and represent the period during which encoded data 32 value is low. LDO voltage system 21 provides a higher load current to transceiver 12 during the period where encoded data 32 value is high. Non-flat portions 42 of modulated signal 33 correspond to and represent the period during which encoded data 32 value is high.
In one example, LDO voltage system 21 is configured to regulate the load current output to transceiver 12 based on encoded data 32 output of encoder 11.
In an example according to an aspect of the present invention, LDO voltage system 21 provides the 6 mA of transient current without increasing, or increasing only minimally, bias current or bias voltage of LDO voltage system 21 to suppress and regulate power consumption during the output of transient current. In other words, LDO voltage system 21 is configured to generate a higher current output to transceiver 12, when encoded data 32 value is high, by reconfiguring the interconnects of its circuit components while maintaining its power consumption at a minimum.
In an example according to an aspect of the present invention, LDO voltage system 21 is configured to operate in a low mode where encoded data 32 value is low. The value of transient current output from LDO voltage system 21 to transceiver 21 when LDO system voltage system 21 is in a low mode is about 0 mA. LDO voltage system 21 is further configured to operate in a high mode where encoded data 32 value is high. The value of transient current output from LDO voltage current system 21 to transceiver 12 when LDO voltage system 21 is in a high mode is about 6 mA.
In an example according to an aspect of the present invention, LDO voltage system 21 enters a boost mode before or when the value of encoded data 32 transitions from low to high. Boost mode conditions LDO voltage system 21 to enter a high mode when encoded data 32 value is about to transition from low to high. LDO voltage system 21 may enter the boost mode within a preset time before encoded data 32 value transitions from low to high. In one example, the present time may be a range of time from 5 to 10 ns.
In an example according to an aspect of the present invention, LDO voltage system 21 enters a fast release mode when a preset time lapses after encoded data 32 value has transitions from low to high. In one example, LDO voltage system 21 enters the fast release mode about 10 ns after the transition from low to high occurred. In another example, LDO voltage system 21 enters the fast release mode when encoded data 32 value transitions from high to low. Fast release mode conditions LDO voltage system 21 to return to a low mode quickly.
In one example, same or largely consistent bias current or bias voltage is applied to LDO voltage system 21 during the different modes. In other words, despite the transitions between a low mode, a high mode, a boost mode, and a fast release mode, the external power drive may be configured to supply the same or only slightly varying bias current or bias voltage to LDO voltage system 21. LDO voltage system 21 is configured to reconfigure the interconnects of its circuit components to output 0 or 6 mA of current to transceiver 12 so that transceiver 12 generates modulated signal 33 corresponding to encoded data 32.
Details related to the examples of the present invention is provided further in relation to
Depending on the value of output signal of encoder 11 of
For efficient transitions, LDO voltage system 310 enters a boost mode when it transitions from the low mode to the high mode. In the boost mode, LDO voltage system 310 is conditioned to quickly increase load current Iload. Similarly, LDO voltage system 310 enters a fast switch mode when it transitions from the high mode to the low mode. In the fast switch mode, LDO voltage system 310 is conditioned to quickly decrease load current Iload.
In one example, external load EX of
Transceiver 12 assumes more current when it generates non-flat portions 42 of modulated signal 33. As illustrated in
Before LDO voltage system 310 enters into the high mode, however, it goes through the boost mode, which conditions LDO voltage system 310 to boost its load current Iload. In one example, LDO voltage system 310 determines when transceiver 12 will be generating non-flat portions 42 based on encoded data 32 of encoder 11. LDO voltage system 310 may make the determination based on the current profile of encoder 11: when encoder 11 generates high value encoded data, it assumes more power from LDO voltage system 310. Based on encoded data 32, LDO voltage system 31 enters a boost mode about 5 to 10 ns before transceiver 12 starts generating non-flat portions 42 of modulated signal 33. Similarly, when encoded data 32 transitions from high to low, LDO voltage system 310 enters fast switch mode to swiftly return to the low mode.
Below table 1 compares the values of source current Iq, load current Iload of LDO voltage system 310, and bandwidth BW when LDO voltage is in a low mode and a high mode.
As seen in Table 1, load current Iload of LDO voltage system 310 can be increased to 6 mA without significantly increasing source current Iq. Because the
LDO voltage system 310 of
By adjusting supply current Tout from current supply, mode changing switch 340 changes the mode of LDO voltage system 310 from a low mode to a boost mode to a high mode. Acceleration switch 330 accelerates the transition of LDO voltage system 310 when it transitions from a high mode to a low mode.
In
Current supply 320 of LDO voltage system 310 comprises a MOSFET current mirror circuitry with transistors MN1·MN5 and MP1·MP5. Bias voltage Vref, Vbiasp, Vbiasn is applied to the respective transistors, and current supply 320 outputs supply current Tout to external load EX. When encoded data 32 value is low, there is little to no transient current in supply current Tout: at most, the transient current in supply current Tout is about 10 μA.
In
When the voltage at gate of PMOS transistor MP3 is pulled down, higher bias current is applied through PMOS transistor MP3, which leads to a boost in supply current Tout. In one example, the increased boost in supply current Tout is a transient current increasing to reach 6 mA. As LDO voltage system 310 enters a high mode, a transient current of 6 mA of supply current Tout is forwarded to external load TX as load current Iload. When external load is transceiver 12, the transient current continues for about 10 ns.
After the transient current is applied to load current Iload for 10 ns, LDO voltage system 310 returns to a low mode. In another example, LDO voltage system 310 returns to a low mode when encoded data 32 value transitions from high to low.
LDO voltage system 310 enters a fast switch mode, illustrated in
According to the examples of the present invention, a LDO voltage system with embedded decoupling capacitor (e.g., decoupling capacitor 350) can swiftly enter a high mode and return to a low mode to drive a transceiver according to the high and low values of encoded data. Further, the LDO voltage system's consumption of energy is limited when it enters a high mode because the LDO voltage system provides a transient current by simply adjusting the configuration of its transistors. In other words, the LDO voltage system according to the present invention does not rely solely on the external power source to generate a transient current to forward as a load current.
According to the examples of the present invention, a LDO voltage system can meet the ultra-low power consumption quiescent current consumption requirements. Also, it enables an on load demand bandwidth increase of a LDO voltage system with a preset mode change, and on load demand transient response from the LDO voltage system.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
Number | Date | Country | Kind |
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201941015764 | Apr 2019 | IN | national |