1. Field of Invention
The present invention relates to a voltage stabilizing circuit and system, and more particularly to a low-dropout linear voltage stabilizing circuit able to leave out an external decoupling capacitor and a system thereof.
2. Description of Related Arts
LDO (low dropout regulator), as a low-dropout linear voltage regulator, has low noise and is fit for integrity and thus is widely applied in electronic systems.
Referring to
However, in a conventional electronic system, in order to produce a compact circuit board and reduce cost, the external decoupling capacitor CO is desired to be left out, accordingly the LDO circuit is usually designed to have a very big loop bandwidth and a very low loop gain to improve speed of response. However two problems exist in this design. The big loop bandwidth results in big power consumption; the low loop gain reduces outputting precision.
Thus, it is necessary to provide a low-dropout linear voltage stabilizing circuit able to reduce power consumption, maintain outputting precision and leave out an external decoupling capacitor and a system thereof.
A low-dropout linear voltage stabilizing circuit comprises a power source terminal, a reference voltage terminal, an outputting terminal, a load and a grounding terminal connected to the load. The low-dropout linear voltage stabilizing circuit further comprises a fast channel circuit connected between the power source terminal and the load for adjusting voltage values outputted by the outputting terminal and a slow channel circuit connected between the power source terminal and the load for stabilizing the voltage values outputted by the outputting terminal. The fast channel circuit and the slow channel circuit are both connected to the outputting terminal. The slow channel circuit is connected to the reference voltage terminal The fast channel circuit comprises a first FET and a controlling subcircuit connected to the first FET. The slow channel circuit comprises an operational amplifier connected to the reference voltage terminal, a first resistance connected to the operational amplifier, a second resistance connected to the first resistance and the first FET. In other preferred embodiments of the low-dropout linear voltage stabilizing circuit of the present invention, the fast channel circuit can comprise other element or circuit for realizing a function of the fast channel circuit; the slow channel circuit can comprise other element or circuit for realizing a function of the slow channel circuit.
A low-dropout linear voltage stabilizing system comprises a power source terminal, a reference voltage terminal, an outputting terminal, a load and a grounding terminal connected to the load. The low-dropout linear voltage stabilizing system further comprises a fast channel circuit connected between the power source terminal and the load for adjusting voltage values outputted by the outputting terminal and a slow channel circuit connected between the power source terminal and the load for stabilizing the voltage values outputted by the outputting terminal. The fast channel circuit and the slow channel circuit are both connected to the outputting terminal. The slow channel circuit is connected to the reference voltage terminal.
Compared to conventional arts, the low-dropout linear voltage stabilizing circuit and its system of the present invention are able to quickly respond to the rapid changes of the power source terminal or the load through the fast channel circuit, so as to quickly turn a voltage value outputted by the outputting terminal back to normal. The low-dropout linear voltage stabilizing circuit and system of the present invention also have a simple structure, reduce the power consumption and maintain the outputting precision of the outputting terminal
These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims.
Referring to
According to the preferred embodiment of the present invention, the low-dropout linear voltage stabilizing system has following connections. The power source terminal VDD and a source electrode of the first FET M1 are connected. A gate electrode of the first FET M1 is connected to an outputting terminal of the operational amplifier OP and a first end of the controlling subcircuit a1. A drain electrode of the first FET M1 is connected to a second terminal of the controlling subcircuit a1, a first terminal of the first resistance R1, a first terminal of the load LOAD and the outputting terminal VOUT. A non-inverting inputting terminal of the operational amplifier OP is connected to a second terminal of the first resistance R1 and a first terminal of the second resistance R2. An inverting inputting terminal of the operational amplifier OP is connected to the reference voltage terminal VREF. A second terminal of the second resistance R2 and a second terminal of the load LOAD are both connected to the grounding terminal GND.
Referring to
According to the preferred embodiment of the present invention, the low-dropout linear voltage stabilizing circuit has following connections. A gate electrode of the first FET M1 is connected to a drain electrode of the second FET M2, a drain electrode of the sixth FET M6, a drain electrode of the fourth FET M4 and a first terminal of the second capacitor C2. A drain electrode of the first FET M1 is connected to a source electrode of the third FET M3, a first terminal of the first capacitor C1 and a first terminal of the load LOAD. A gate electrode of the second FET M2 is connected to a first voltage terminal VBP1. A gate electrode of the third FET M3 is connected to a gate electrode and a drain electrode of the ninth FET M9, a drain electrode of the tenth FET M10 and a voltage controlling terminal VSET. A drain electrode of the third FET M3 is connected to a source electrode of the fourth FET M4, a second terminal of the second capacitor C2 and a drain electrode of the fifth FET M5. A gate electrode of the fourth FET M4 and a gate electrode of the sixth FET M6 are both connected to a second voltage terminal VBN1. A gate electrode of the fifth FET M5, a gate electrode of the seventh FET M7 and a gate electrode of the tenth FET M10 are all connected to a third voltage terminal VBN2. A source electrode of the sixth FET M6 is connected to a drain electrode of the seventh FET M7 and a second terminal of the first capacitor C1. A gate electrode of the eighth FET M8 is connected to an outputting terminal of the operational amplifier OP. A drain electrode of the eighth FET M8 is connected to a first terminal of the first resistance R1, a source electrode of the ninth FET M9 and an outputting controlling terminal VOUT1. A non-inverting inputting terminal of the operational amplifier OP is connected to a second terminal of the first resistance R1 and a first terminal of the second resistance R2. An inverting inputting terminal of the operational amplifier OP is connected to the reference voltage terminal VREF. A source electrode of the first FET M1, a source electrode of the second FET M2 and a source electrode of the eighth FET M8 are all connected to the power source terminal VDD. A second terminal of the second resistance R2, a source electrode of the tenth FET M10, a source electrode of the seventh FET M7, a source electrode of the fifth FET M5 and a second terminal of the load LOAD are all connected to a grounding terminal GND.
The low-dropout linear voltage stabilizing circuit and its system of the present invention have following working principles.
When the power source terminal VDD and the load LOAD are both relatively stable, the slow channel circuit determines a voltage value outputted by the outputting terminal VOUT. According to
When the power source terminal VDD and the load LOAD are changing rapidly, a current of the outputting terminal VOUT suddenly increases or decreases. An example of the rapidly changing load LOAD is following.
When the load LOAD is changing rapidly and the current of the outputting terminal VOUT suddenly increases, the voltage of the outputting terminal VOUT tends to decrease and then the third FET M3 and the first capacitor C1 are able to simultaneously detect changes of the outputting terminal VOUT. The third FET M3 is formed in a common gate structure and thus has a relatively quick speed of response, so the third FET M3 sends information of the decreasing voltage of the outputting terminal VOUT into the second capacitor C2 in a very short time. A capacitor has a feature that a voltage of a second terminal increases or decreases identically to a voltage of a first terminal. The first terminal of the second capacitor C2 is connected to the gate electrode of the first FET M1, so a voltage of the gate electrode of the first FET M1 decreases, i.e., a gate-source voltage of the first FET M1 VGS (M1) rapidly increases, and a current running through the first FET M1 also rapidly increases, so as to rapidly catch up with the changes of the load LOAD. Similarly, the first capacitor C1 rapidly leads to a decreasing voltage of the source electrode of the sixth FET M6 and further an increasing gate-source voltage of the sixth FET M6 VGS(M6) so as to increase a current running therethrough, in such a manner that the gate-source voltage of the first FET M1 is rapidly dragged down by a current running through the sixth FET M6 and the current running through the first FET M1 increases, so as to rapidly catch up with the changes of the load LOAD.
When a current of the outputting terminal VOUT suddenly decreases, a voltage of the outputting terminal VOUT tends to increase and then the third FET M3 and the first capacitor C1 are able to simultaneously detect changes of the outputting terminal VOUT. The third FET M3 is made in a common gate structure and thus has a relatively quick speed of response, so the third FET M3 sends information of the increasing voltage of the outputting terminal VOUT into the second capacitor C2 in a very short time. A capacitor has a feature that a voltage of a second terminal increases or decreases identically to a voltage of a first terminal The first terminal of the capacitor C2 is connected to the gate electrode of the first FET M1, so a voltage of the gate electrode of the first FET M1 increase, i.e., a gate-source voltage of the first FET M1 VGS(M1) rapidly decreases, and a current running through the first FET M1 also rapidly decreases, so as to rapidly catch up with the changes of the load LOAD. Similarly, the first capacitor C1 is able to rapidly leads to an increasing voltage of the source electrode of the sixth FET M6 and further a decreasing gate-source voltage of the sixth FET M6 VGS(M6) so as to decrease a current running therethrough, in such a manner that a voltage of the gate electrode of the first FET M1 is rapidly dragged up by a current running through the sixth FET M6 and a current running through the first FET M1 decreases, so as to catch up with the changes of the load LOAD.
According to the preferred embodiment of the present invention, the first capacitor C1 is connected between the outputting terminal VOUT and a second connecting terminal V2; the second capacitor C2 is connected between a first connecting terminal V1 and a third connecting terminal V3. When the power source terminal VDD and the load LOAD are relatively stable, the first capacitor C1 and the second capacitor C2 consume no power; when the power source terminal VDD and the load LOAD are changing rapidly, the first capacitor C1 and the second capacitor C2 are able to respond quickly and save power consumption.
In other preferred embodiments, capacitors are optionally connected between the first connecting terminal V1 and the second connecting terminal V2, between the first connecting terminal V1 and the outputting terminal VOUT, between the first connecting terminal V1 and the third connecting terminal V3 and between the second connecting terminal V2 and the outputting terminal VOUT to form a fast channel.
Moreover, according to the preferred embodiment of the present invention, the fast channel circuit comprises the first channel and the second channel. In other preferred embodiments, the first channel can be omitted and only the second channel functions as a fast channel circuit.
The low-dropout linear voltage stabilizing circuit and its system of the present invention are able to quickly respond to the rapid changes of the power source terminal VDD or the load LOAD through the fast channel circuit to quickly turn the voltage outputted by the outputting terminal VOUT back to normal, and stabilize the voltage outputted by the outputting terminal VOUT through the slow channel circuit when the power source terminal VDD or the load LOAD are stable. The low-dropout linear voltage stabilizing circuit and its system of the present invention also have a simple structure, reduce the power consumption and maintain the outputting precision of the outputting terminal.
One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.
It will thus be seen that the objects of the present invention have been fully and effectively accomplished. Its embodiments have been shown and described for the purposes of illustrating the functional and structural principles of the present invention and is subject to change without departure from such principles. Therefore, this invention includes all modifications encompassed within the spirit and scope of the following claims.
Number | Date | Country | Kind |
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201110252483.0 | Aug 2011 | CN | national |