Patent Application
20230384813
This application claims priority to Taiwanese Application Serial Number 111119505, filed May 25, 2022, which is herein incorporated by reference.
The present disclosure relates to a low-dropout regulator circuit and a control method thereof. More particularly, the present disclosure relates to a low-dropout regulator circuit and a control method thereof capable of avoiding a large inrush current flowing through a power switch circuit when the low-dropout regulator circuit is initially powered on.
With development of technology, various integrated circuits (ICs) are developed. However, performance of many integrated circuits can be further improved.
For example, in some related approaches, when a low-dropout regulator circuit is initially powered on (an input voltage initially increases), a large inrush current flows through a power switch circuit in the low-dropout regulator circuit. This large inrush current may burn components or wires in the circuit.
Some aspects of the present disclosure are to provide a low-dropout regulator circuit. The low-dropout regulator circuit includes a reference circuit, an amplifying circuit, a power switch circuit, a feedback circuit, and a control circuit. The reference circuit is configured to generate a reference voltage. The amplifying circuit is configured to generate an amplifying voltage according to the reference voltage and a feedback voltage. The power switch circuit is configured to receive the amplifying voltage and generate an output voltage at an output terminal according to an input voltage. The feedback circuit is configured to generate the feedback voltage according to the output voltage. The control circuit is configured to control the power switch circuit according to the input voltage and a signal from the reference circuit.
Some aspects of the present disclosure are to provide a control method of a low-dropout regulator circuit. The control method includes following operations: generating, by a reference circuit, a reference voltage; generating, by an amplifying circuit, an amplifying voltage according to the reference voltage and a feedback voltage; receiving, by a power switch circuit, the amplifying voltage and generating, by the power switch circuit, an output voltage at an output terminal according to an input voltage; generating, by a feedback circuit, the feedback voltage according to the output voltage; and controlling, by a control circuit, the power switch circuit according to the input voltage and a signal from the reference circuit.
As described above, in the low-dropout regulator circuit of the present disclosure, the control circuit can control the power switch circuit according to the input voltage and the signal from the reference circuit. Thus, when the low-dropout regulator circuit is initially powered on, a smaller current flows through power switch circuit to avoid a large inrush current.
The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
In the present disclosure, “connected” or “coupled” may refer to “electrically connected” or “electrically coupled.” “Connected” or “coupled” may also refer to operations or actions between two or more elements.
Reference is made to
As illustrated in
The reference circuit 102 is coupled to the amplifying circuit 104. The amplifying circuit 104 is coupled to the power switch circuit 106 and the feedback circuit 108. The power switch circuit 106 is coupled to the feedback circuit 108 and the control circuit 110. A load L is coupled between an output terminal OUT and a ground terminal GND. An external capacitor CEX can be disposed on a printed circuit board. A first terminal of the capacitor CEX is coupled to a pin of the output terminal OUT through other component or a metal wire with a parasitic resistor RS, and a second terminal of the capacitor CEX is coupled to the ground terminal GND. The external capacitor CEX is used to make the output voltage VO more stable.
The reference circuit 102 operates according to an input voltage AVDD, and the reference circuit 102 is used to generate a reference voltage VBG. In the embodiment of
The amplifying circuit 104 operates according to the input voltage AVDD and includes a positive terminal and a negative terminal. The negative terminal of the amplifying circuit 104 receives the reference voltage VBG from the reference circuit 102, and the positive terminal of the amplifying circuit 104 receives a feedback voltage VFB from the feedback circuit 108. The amplifying circuit 104 is used to compare the reference voltage VBG with the feedback voltage VFB to generate an amplifying voltage VGATE. In some embodiments, the amplifying circuit 104 can be an analog amplifier.
The power switch circuit 106 is used to receive the amplifying voltage VGATE, and generates an output voltage VO at the output terminal OUT according to the input voltage AVDD. The power switch circuit 106 can include at least one power switch, the amplifying voltage VGATE can turn on the power switch, and a current flowing the turned-on power switch can charge the output terminal OUT to generate the output voltage VO.
The feedback circuit 108 is used to generate the feedback voltage VFB to the positive terminal of the amplifying circuit 104 according to the output voltage VO. As illustrated in
The control circuit 110 is used to control the power switch circuit 106 according to the input voltage AVDD and a signal SS from the reference circuit 102. The details about how the control circuit 110 controls the power switch circuit 106 according to the input voltage AVDD and the signal SS are described with reference to
Reference is made to
In the embodiment of
As illustrated in
The voltage-divider circuit 212 is used to generate a voltage-dividing voltage VX according to the input voltage AVDD. For example, the voltage-divider circuit 212 includes a resistor R3, a resistor R4, and a capacitor CX. A first terminal of the resistor R3 is used to receive the input voltage AVDD, a second terminal of the resistor R3 is coupled to a first terminal of the resistor R4, and a second terminal of the resistor R4 is coupled to the ground terminal GND. A first terminal of the capacitor CX is coupled between a connection node N2 between the resistor R3 and the resistor R4, a second terminal of the capacitor CX is coupled to the ground terminal GND, and the voltage-dividing voltage VX is generated at the connection node N2. With this configuration, there is a positive correlation between the voltage-dividing voltage VX and the input voltage AVDD. In other words, when the input voltage AVDD is higher, the voltage-dividing voltage VX will be higher.
The detector circuit 214 is used to generate a detection signal DS according to the reference voltage VBG and the voltage-dividing voltage VX. In some embodiments, the detector circuit 214 can be implemented by a comparator. For example, the comparator can compare the reference voltage VBG with the voltage-dividing voltage VX. When the voltage-dividing voltage VX is less than the reference voltage VBG, the comparator outputs the detection signal DS with a first logic value (e.g., a logic value 0). On the contrary, when the voltage-dividing voltage VX is equal to or greater than the reference voltage VBG, the comparator outputs the detection signal DS with a second logic value (e.g., a logic value 1). The detection signal DS with the second logic value (e.g., the logic value 1) can enable the counter circuit 216 to start counting.
The counter circuit 216 is used to generate a counting signal CN according to the detection signal DS. As described above, when the voltage-dividing voltage VX is equal to or greater than the reference voltage VBG, the detection signal DS with the second logic value (e.g., the logic value 1) can enable the counter circuit 216 to start counting to generate the counting signal CN so as to control the power switch circuit 206.
As illustrated in
When the low-dropout regulator circuit 200 is initially powered on, the amplifying voltage VGATE can first turn on the power switch MP1 such that the input voltage AVDD can slightly charge the output terminal OUT. Since the input voltage AVDD is not large enough and the reference circuit 102 is not stable (the voltage-dividing voltage VX is less than the reference voltage VBG), the detector circuit 214 does not output the detection signal DS with the second logic value and the counter circuit 216 is still disabled. Thus, the power switches MP2-MP4 are turned off.
After a period of time, the input voltage AVDD is large enough (the voltage-dividing voltage VX is equal to or larger than the reference voltage VBG). In other words, the output voltage VO is charged to a higher voltage level and is more stable. Since the voltage-dividing voltage VX is equal to or greater than the reference voltage VBG, the detector circuit 214 can output the detection signal DS with the second logic value to enable the counter circuit 216 to start counting. For example, a value of the counting signal CN can increase from 0. In some embodiments, a power switch control circuit (not shown) can be coupled to the counter circuit 216. When the value of the counting signal CN increases to a first value (a first delay time elapses equivalently), the power switch control circuit can output a control signal to turn on the power switch MP2. When the value of the counting signal CN increases to a second value (a second delay time elapses equivalently), the power switch control circuit can output a control signal to turn on the power switch MP3. When the value of the counting signal CN increases to a third value (a third delay time elapses equivalently), the power switch control circuit can output a control signal to turn on the power switch MP4. In other words, when the input voltage AVDD is large enough (the output voltage VO is charged to a higher voltage level and is more stable), more power switches are turned on. Thus, the current flowing through the power switch circuit 206 becomes larger and the low-dropout regulator circuit 200 is capable of providing a larger current to the load L for normal operation. In some other embodiments, the power switches MP2-MP4 can be turned on simultaneously.
In some embodiments, the power switches MP1-MP4 have the same gate length but different gate widths. For example, the ratio of the gate widths of the power switches MP1-MP4 can be 1:2:4:8, but the present disclosure is not limited thereto. In the example above, the size of the power switch MP1 is smallest, and the current flowing through power switch circuit 206 during the initial stage (the low-dropout regulator circuit 200 is initially powered on) is very small. In some other embodiments, the power switches MP1-MP4 can have the same gate width.
In addition, the quantity of the transistors in the power switch circuit 206 is for illustration, and the present disclosure is not limited thereto. Other applicable quantities are within the contemplated scopes of the present disclosure.
As illustrated in
In some related approaches, a low-dropout regulator circuit merely includes an over-current protection circuit. However, as described above, the over-current protection circuit starts to operate normally after an input voltage reaches to a threshold voltage. If the over-current protection circuit have multiple cascaded transistors, the threshold voltage will be higher. Due to the threshold voltage, the over-current protection circuit may not start to operate normally when a power switch circuit in the low-dropout regulator circuit is initially turned on. Accordingly, the over-current protection circuit cannot avoid a large inrush current flowing the power switch circuit when the low-dropout regulator circuit is initially powered on (the input voltage initially increases).
In some other related approaches, an additional low-pass filter circuit (e.g., a resistor-capacitor circuit) is coupled to an output terminal of a reference circuit in a low-dropout regulator circuit. This additional low-pass filter circuit makes a reference voltage outputted from the reference circuit increase more slowly. Thus, the power switch circuit can slowly charge an output terminal until the output voltage becomes stable. However, the additional low-pass filter circuit occupies a larger circuit area.
Compared to the aforementioned related approaches, in the present disclosure, when the low-dropout regulator circuit 200 is initially powered on, the control circuit 210 can control the current flowing through power switch circuit 206 to be smaller. Thus, it can avoid a large inrush current flowing through the power switch circuit 206 when the low-dropout regulator circuit 200 is initially powered on. In addition, the present disclosure does not need to dispose the additional low-pass filter circuit, so the circuit area does not increase too much.
Reference is made to
One of major differences between the low-dropout regulator circuit 300 in
One of major differences between the low-dropout regulator circuit 300 in
In some embodiments, the implementation of the control circuit 210 in
When the low-dropout regulator circuit 300 is initially powered on, the switch SW can be turned on to limit a gate-source voltage of the power switch MP5. Thus, the current flowing through the power switch circuit 306 is not too large.
Similar to
As illustrated in
Similarly, when the low-dropout regulator circuit 300 is initially powered on, the current flowing through power switch circuit 306 is smaller. Thus, it can avoid a large inrush current flowing through the power switch circuit 306 when the low-dropout regulator circuit 300 is initially powered on. In addition, the present disclosure does not need to dispose additional low-pass filter circuit, so the circuit area does not increase too much.
Reference is made to
The following paragraphs mainly describe the major differences between the low-dropout regulator circuit 400 and the aforementioned embodiments. Other details of the low-dropout regulator circuit 400 that are similar to the aforementioned embodiments are not described herein again.
As illustrated in
In the embodiment of
The power switch circuit 406 includes a power switch MP6. The power switch MP6 can be implemented by a P-type transistor. The power switch MP6 includes a first terminal, a second terminal, and a control terminal. The first terminal of the power switch MP6 is used to receive the input voltage AVDD, the second terminal of the power switch MP6 is coupled to the output terminal OUT, and the control terminal of the power switch MP6 is coupled to the output terminal of the amplifying circuit 104.
The control circuit 410 includes a transistor MR and a capacitor CR. The transistor MR includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MR is used to receive the input voltage AVDD. The second terminal of the transistor MR is coupled to the control terminal of the power switch MP6. The reference circuit 402, the control terminal of the transistor MR, and a first terminal of the capacitor CR are coupled to at a node N3. A second terminal of the capacitor CR is coupled to the ground terminal GND. A node voltage VR at the node N3 initially has a first logic value (e.g., a logic value 0), and the reference current IX from the reference circuit 402 can be used to charge at the node N3.
During the low-dropout regulator circuit 400 is initially powered on, the input voltage AVDD can increase from 0 volt to a threshold voltage of the transistor MR. Since the node voltage VR at the node N3 initially has the first logic value (e.g., the logic value 0), the transistor MR is turned on. The power switch MP6 is turned off. When the reference circuit 402 is stable, the reference circuit 402 generates the weak reference current IX to charge at the node N3 slowly. During the charging process, a gate-source voltage of the transistor MR gradually decreases. Accordingly, an equivalent resistance RR of the transistor MR gradually becomes larger. This makes the difference between the input voltage AVDD and the amplifying voltage VGATE larger, and then makes the turned-on degree of the power switch MP6 gradually increases. Accordingly, the input voltage AVDD charges the output terminal OUT. When the node voltage VR at the node N3 is charged to a high enough level (e.g., the difference between the input voltage AVDD and the node voltage VR is less than an absolute value of the threshold voltage of the transistor MR), the power switch MP6 can provide a larger current to the load L.
As illustrated in
Similarly, when the low-dropout regulator circuit 400 is initially powered on, the current flowing through power switch circuit 406 is smaller. Thus, it can avoid a large inrush current flowing through the power switch circuit 406 when the low-dropout regulator circuit 400 is initially powered on. In addition, the present disclosure does not need to dispose additional low-pass filter circuit, so the circuit area does not increase too much.
Reference is made to
In some embodiments, the control method 500 can be implemented to the low-dropout regulator circuit 100 in
In operation S510, the reference circuit 102 generates the reference voltage VBG. In some embodiments, the reference circuit 102 can be implemented by a reference circuit 402 in
In operation S520, the amplifying circuit 104 generates the amplifying voltage VGATE according to the reference voltage VBG and the feedback voltage VFB. In some embodiments, the negative terminal of the amplifying circuit 104 receives the reference voltage VBG, and the positive terminal of the amplifying circuit 104 receives the feedback voltage VFB.
In operation S530, the power switch circuit 106 receives the amplifying voltage VGATE and generates the output voltage VO at the output terminal OUT according to the input voltage AVDD. In some embodiments, when the power switch circuit 106 is turned on, the input voltage AVDD can charge the output terminal OUT through the power switch circuit 106.
In operation S540, the feedback circuit 108 generates the feedback voltage VFB according to the output voltage VO. In some embodiments, a relationship between the feedback voltage VFB and the output voltage VO is related to the resistance-value ratio of the resistor R1 and the resistor R2.
In operation S550, the control circuit 110 controls the power switch circuit 106 according to the input voltage AVDD and the signal SS from the reference circuit 102. In some embodiments (e.g.,
As described above, in the low-dropout regulator circuit of the present disclosure, the control circuit can control the power switch circuit according to the input voltage and the signal from the reference circuit. Thus, when the low-dropout regulator circuit is initially powered on, a smaller current flows through power switch circuit to avoid a large inrush current.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 111119505 | May 2022 | TW | national |
