FIELD
The disclosure relates to a regulator, and more particularly to a low dropout regulator with wide input voltage.
BACKGROUND
FIG. 1 illustrates a conventional regulator for converting a variable DC input voltage (VIN) ranging, for example, from 7V to 40V, into a DC output voltage (VOUT) of, for example, 5V. The conventional regulator includes a reference voltage generation module 1′ that is operable to generate a first reference voltage output (Vrf1) and a second reference voltage (Vrf2) based on the DC input voltage (VIN), and a conversion module 5′ that is coupled to the reference voltage generation module 1′ and that is operable to generate the DC output voltage (VOUT) based on the DC input voltage (VIN), on the first reference voltage output (Vrf1) and on the second reference voltage (Vrf2) from the reference voltage generation module 1′.
Referring further to FIG. 2A, the reference voltage generation module 1′ has an input terminal (P1) for receiving the DC input voltage (VIN), and includes first to sixth transistors 11-16 and a resistor 17. The first, fourth and fifth transistors 11, 14, 15 are PMOS transistors, and the second, third and sixth transistors 12, 13, 16 are NMOS transistors. The first to third transistors 11, 12, 13 are coupled sequentially in series between the input terminal (P1) and ground. The fourth to sixth transistors 14, 15, 16 and the resistor 17 are coupled sequentially in series between the input terminal (P1) and ground. Sources of the first and fourth transistors 11, 14 are coupled to the input terminal (P1). Gates of the first and fourth transistors 11, 14, drain of the fourth transistor 14 and source of the fifth transistor 15 are coupled to each other. Drains of the first and second transistors 11, 12 and gate of the second transistor 12 are coupled to each other. A source of the second transistor 12, a drain of the third transistor 13, and gates of the third and sixth transistors 13, 16 are coupled to each other. A gate and a drain of the fifth transistor 15, and a drain of the sixth transistor 16 are coupled to each other. Sources of the third and sixth transistors 13, 16 are coupled respectively to ground and one end of the resistor 17. The other end of the resistor 17 is coupled to ground. The potential at a common node (P2) among the gate of the first transistor 11, the gate and drain of the fourth transistor 14 and the source of the fifth transistor 15 serves as a first voltage (V1). The potential at a common node (P3) among the gate and drain of the fifth transistor 15 and the drain of the sixth transistor 16 serves as a second voltage (V2). The potential at a common node (P4) between the gate and drain of the second transistor 12 serves as a third voltage (V3). The potential at a common node (P5) among the gate and drain of the third transistor 13 and the gate of the sixth transistor 16 serves as the second reference voltage (Vrf2). The first, second and third voltages (V1, V2, V3) cooperatively constitute the first reference voltage output (Vrf1).
Referring to FIG. 2B, the conversion module 5′ includes an error amplifier circuit 51, and a voltage division circuit 52 coupled to the error amplifier circuit 51.
The error amplifier circuit 51 receives the first to third voltages (V1, V2, V3) (i.e., the first reference voltage output (Vrf1)) and the second reference voltage (Vrf2) from the reference voltage generation module 1′. The error amplifier circuit 51 is operable to generate an amplified signal (As) based on the first to third voltages (V1, V2, V3), on the second reference voltage (Vrf2) and on a divided voltage (Vd) associated with the DC output voltage (VOUT). The error amplifier circuit 51 includes a first transistor 511, a differential pair 50 of second and third transistors 512, 513, fourth and fifth transistors 514, 515, and first to eighth bias transistors 531-538. The transistors 511, 512, 513, 531, 532, 535, 536 are PMOS transistors, and the transistors 514, 515, 533, 534, 537, 538 are NMOS transistors. Each of the first to fifth transistors 511-515 and the first to eight bias transistors 531-538 has a source, drain and gate that serve respectively as a first terminal, a second terminal and a control terminal. The source and gate of the first transistor 511 receive respectively the DC input voltage (VIN) and the first voltage (V1) (from the common node (P2) of the reference voltage generation module 1′ (FIG. 2A)). The drain of the first transistor 511 and the sources of the second and third transistors 512, 513 are coupled to each other. The gates of the second and third transistors 512, 513 receive respectively the divided voltage (Vd) and the second reference voltage (Vrf2) (from the common node (P5) of the reference voltage generation module 1′ (FIG. 2A)). The drain of the second transistor 512, and the drain and gate of the fourth transistor 514 are coupled to each other. The drain of the third transistor 513, and the drain and gate of the fifth transistor 515 are coupled to each other. The sources of the fourth and fifth transistors 514, 515 are coupled to ground. The first to fourth bias transistors 531, 532, 533, 534 are coupled sequentially in series between the source of the first transistor 511 and ground. The fifth to eighth bias transistors 535, 536, 537, 538 are coupled sequentially in series between the source of the first transistor 511 and ground. The sources of the first and fifth bias transistors 531, 535 are coupled to the source of the first transistor 511, thereby receiving the DC input voltage (VIN). The drain of the first bias transistor 531 is coupled to the source of the second bias transistor 532. The gates of the first and fifth bias transistors 531, 535, and the drains of the second and third bias transistors 532, 533 are coupled to each other at a first common node (n1). The gates of the second and sixth bias transistors 532, 536 are coupled to each other for receiving the second voltage (V2) from the common node (P3) of the reference voltage generation module 1′ (FIG. 2A). The gates of the third and seventh bias transistors 533, 537 are coupled to each other for receiving the third voltage (V3) from the common node (P4) of the reference voltage generation module 1′ (FIG. 2A). The drain, source and gate of the fourth bias transistor 534 are coupled respectively to the source of the third bias transistor 533, ground and the drain of the third transistor 513. The drain of the fifth bias transistor 535 is coupled to the source of the sixth bias transistor 536. The drains of the sixth and seventh bias transistors 536, 537 are coupled to each other at a second common node (n2). The drain, source and gate of the eighth bias transistor 538 are coupled respectively to the source of the seventh bias transistor 537, ground and drain of the second transistor 512.
Thus, the first to third transistors 511, 512, 513 are operable to be conducting or non-conducting in response, respectively, to the first voltage (V1), the divided voltage (Vd) and the second reference voltage (Vrf2). The second and sixth bias transistors 532, 536 are operable to be conducting or non-conducting in response to the second voltage (V2). The third and seventh bias transistors 533, 537 are operable to be conducting or non-conducting in response to the third voltage (V3). The amplified signal (As) is outputted at the second common node (n2).
The voltage division circuit 52 receives the DC input voltage (VIN), and the amplified signal (As) from the second common node (n2) of the error amplifier circuit 51. The voltage division circuit 52 is operable to generate, based on the DC input voltage (VIN) and the amplified signal (As), the DC output voltage (VOUT) and the divided voltage (Vd). The voltage division circuit 52 includes a sixth transistor 521, and first to third resistors 522, 523, 524 coupled sequentially in series between the sixth transistor 521 and ground. The sixth transistor 521 is a PMOS transistor that has a source for receiving the DC input voltage (VIN), a gate coupled to the second common node (n2) for receiving the amplified signal (As) therefrom, and a drain coupled to one end of the first resistor 522. When the sixth transistor 521 conducts in response to the amplified signal (As), a voltage across the first to third resistors 522, 523, 524 is outputted to serve as the DC output voltage (VOUT), and a voltage across the third resistor 524 is outputted to serve as the divided voltage (Vd).
In such a configuration, as the DC input voltage (VIN) initially increases from zero, the second reference voltage (Vrf2) outputted at the common node (P5) of the reference voltage generation module 1′ increases until reaching a gate-to-source voltage of the third transistor 13. Thereafter, the second reference voltage (Vrf2) remains unchanged and is thus insensitive to the increase of the DC input voltage (VIN). As a result, the conventional regulator may not output the DC output voltage (VOUT) in a stable way after the second reference voltage (Vrf2) reaches the gate-to-source voltage of the third transistor 13.
SUMMARY
Therefore, an object of the disclosure is to provide a low dropout regulator with wide input voltage that can alleviate the drawback of the prior art.
According to the disclosure, there is provided a regulator for converting a DC input voltage into a DC output voltage. The regulator of this disclosure includes a reference voltage generation module, a control module, a switching module and a conversion module.
The reference voltage generation module is used to receive the DC input voltage, and is operable to generate a first reference voltage output and a second reference voltage based on the DC input voltage.
The control module is operable to generate a predetermined regulated voltage associated with the DC output voltage, and to further generate a control signal based on a feedback voltage associated with the DC output voltage.
The switching module is coupled to the reference voltage generation module and the control module for receiving the second reference voltage from the reference voltage generation module, and the predetermined regulated voltage and the control signal from the control module. The switching module is operable to output, in response to the control signal, one of the second reference voltage and the predetermined regulated voltage to serve as a switching voltage.
The conversion module is used to receive the DC input voltage, and is coupled to the reference voltage generation module, the control module and the switching module. The conversion module further receives the first reference voltage output from the reference voltage generation module, and the switching voltage from the switching module. The conversion module is operable to generate the DC output voltage and the feedback voltage based on the DC input voltage, the first reference voltage output and the switching voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiment with reference to the accompanying drawings, of which:
FIG. 1 is a schematic block diagram illustrating a conventional regulator;
FIG. 2A is a schematic electrical circuit diagram illustrating a reference voltage generation module of the conventional regulator;
FIG. 2B is a schematic electrical circuit diagram illustrating a conversion module of the conventional regulator;
FIG. 3 is a schematic block diagram illustrating the embodiment of a regulator according to the disclosure;
FIG. 4 is a schematic block diagram illustrating a control module of the embodiment;
FIG. 5 is a schematic block diagram illustrating a switching control circuit of the control module of the embodiment;
FIG. 6 is a schematic electrical circuit diagram illustrating the switching control circuit of the control module of the embodiment; and
FIG. 7 is a schematic electrical circuit diagram illustrating a conversion module of the embodiment.
DETAILED DESCRIPTION
Before this disclosure is described in detail, it should be noted herein that throughout this disclosure, like elements are denoted by the same reference numerals. In addition, when two elements are described as being “coupled in series,” “connected in series” or the like, it is merely intended to portray a serial connection between the two elements without necessarily implying that the currents flowing through the two elements are identical to each other and without limiting whether or not an additional element is coupled to a common node between the two elements. Essentially, “a series connection of elements,” “a series coupling of elements” or the like as used throughout this disclosure should be interpreted as being such when looking at those elements alone.
Referring to FIG. 3, the embodiment of a low dropout regulator with wide input voltage according to the disclosure is adapted for converting a variable DC input voltage (Vin) ranging, for example, from 7V to 40V, into a stable DC output voltage (Vout) of, for example, 5V. The regulator of this disclosure includes a reference voltage generation module 1, a control module 3, a switching module 4 and a conversion module 5. It is noted that the DC output voltage (Vout) is also used to serve as a bias voltage for operation of the control module 3.
The reference voltage generation module 1 is used to receive the DC input voltage (Vin), and is operable to generate a first reference voltage output (Vrf1) and a second reference voltage (Vrf2) based on the DC input voltage (Vin). In this embodiment, for example, the reference voltage generation module 1 may have the same configuration and operation as those of the reference voltage generation module 1′ of FIG. 2A. Thus, similarly, the first reference voltage output (Vrf1) is the same as that of FIG. 2A, which consists of the first to third voltages (V1-V3), and the second reference voltage (Vrf2) is the same as that of FIG. 2A.
The control module 3 is operable to generate a predetermined regulated voltage (Vre) associated with the DC output voltage (Vout), and to generate a control signal (Cs) based on a feedback voltage (VFB) associated with the DC output voltage (Vout). In this embodiment, referring further to FIG. 4, the control module 3 includes a voltage regulation circuit 31, a clock signal generation circuit 32 and a switching control circuit 33. The voltage regulation circuit 31 is used to generate the predetermined regulated voltage (Vre). The clock signal generation circuit 32 is coupled to the voltage regulation circuit 31 for receiving the predetermined regulated voltage (Vre) therefrom, and is operable to generate a clock signal (CLK) based on the predetermined regulated voltage (Vre). The switching control circuit 33 is coupled to the voltage regulation circuit 31, the clock signal generation circuit 32 and the conversion module 5. The switching control circuit 33 receives the predetermined regulated voltage (Vre) from the voltage regulation circuit 31, the clock signal (CLK) from the clock signal generation circuit 32, and the feedback voltage (VFB) from the conversion module 5. The switching control circuit 33 is operable to generate the control signal (Cs) based on the predetermined regulated voltage (Vre), the clock signal (CLK) and the feedback voltage (VFB), and to output the control signal (Cs) to the switching module 4.
In this embodiment, referring further to FIGS. 5 and 6, the switching control circuit 33 includes a comparison unit 34, a counting unit 35 and a logic unit 36.
The comparison unit 34 is coupled to the conversion module 5 and the voltage regulation circuit 31 for receiving the feedback voltage (VFB) and the predetermined regulated voltage (Vre) respectively therefrom. The comparison unit 34 is operable to generate, based on the feedback voltage (VFB) and the predetermined regulated voltage (Vre), a reset signal (Rs). The comparison unit 34 may include, but is not limited to, a comparator 341 and a NOT gate 342. The comparator 341 has a non-inverting input end for receiving the feedback voltage (VFB), an inverting input end that is coupled to the voltage regulation circuit 31 for receiving the predetermined regulated voltage (Vre) therefrom, and an output end. The comparator 341 compares the predetermined regulated voltage (Vre) and the feedback voltage (VFB) so as to generate an output signal (So) at the output end thereof. The NOT gate 342 has an input terminal that is coupled to the output end of the comparator 341 for receiving the output signal (So) therefrom, and an output terminal that outputs the reset signal (Rs) generated by the NOT gate 342 from the output signal (So).
The counting unit 35 is coupled to the clock signal generation circuit 32 and the comparison unit 34 for receiving the clock signal (CLK) and the reset signal (Rs) respectively therefrom. The counting unit 35 is operable to generate, based on an input signal (Si), the clock signal (CLK) and the reset signal (Rs), a counting result (Cr) associated with a predetermined period of time. The counting unit 35 may include, but is not limited to, an AND gate 351, and a number N of cascaded D-type flip-flops, where N is associated with the predetermined period of time. In this embodiment, for example, N=4. Therefore, four cascaded D-type flip-flops 352, 353, 354, 355 are shown in FIG. 6, respectively referred to as first, second, third and fourth D-type flip-flops 352, 353, 354, 355 hereinafter for the sake of simplicity of explanation. However, in other embodiments, when the predetermined period of time is longer, N may be greater than four. The AND gate 351 has a first input end for receiving the input signal (Si), a second input end that is coupled to the clock signal generation circuit 32 for receiving the clock signal (CLK) therefrom, and an output end. The AND gate 351 outputs a trigger signal (Ts) at its output end in response to the input signal (Si) and the clock signal (CLK). Each of the D-type flip-flops 352, 353, 354, 355 has a data input (D) and an inverting data output (QB) that are coupled to each other, a trigger signal input (T), a non-inverting data output (Q), and a reset signal input (CLR) that is coupled to the output end of the NOT gate 342 for receiving the reset signal (Rs) therefrom. The trigger signal input (T) of the first D-type flip-flop 352 is coupled to the output end of the AND gate 351 for receiving the trigger signal (Ts). The trigger signal input (T) of an ith one of the D-type flip-flops is coupled to the non-inverting data output (Q) of an (i−1)th one of the D-type flip-flops, where 2≦i≦4. Each of the D-type flip-flops 352, 353, 354, 355 outputs a respective bit signal and a respective inverted bit signal respectively at its non-inverting data output (Q) and its inverting data output (QB). The bit signal outputted at the non-inverting data output (Q) of the first D-type flip-flop 352, and the inverted bit signals outputted respectively at the inverting data outputs (QB) of the second to fourth D-type flip-flops 353, 354, 355 cooperatively constitute the counting result (Cr).
The logic unit 36 is coupled to the counting unit 35 for receiving the counting result (Cr) therefrom, and to the switching module 4. The logic unit 36 is operable to generate the input signal (Si) and the control signal (Cs) based on the counting result (Cr). The logic unit 36 may include, but is not limited to, a NAND gate 361 for generating the input signal (Si) and a NOT gate 362 for generating the control signal (Cs). In this embodiment, the NAND gate 361 has, for example, four input terminals that are coupled respectively to the non-inverting data output (Q) of the D-type flip-flop 352 and the inverting data outputs (QB) of the second to fourth D-type flip-flops 353, 354, 355 for receiving the bit signal and the inverted bit signals respectively therefrom, and an output terminal that is coupled to the first input end of the AND gate 351 of the counting unit 35 for outputting the input signal (Si) thereto. The NOT gate 362 has an input end that is coupled to the output terminal of the NAND gate 361 for receiving the input signal (Si) therefrom, and an output end for outputting the control signal (Cs).
Referring again to FIG. 3, the switching module 4 is coupled to the reference voltage generation module 1 and the control module 3 for receiving the second reference voltage (Vrf2) from the reference voltage generation module 1, and the predetermined regulated voltage (Vre) and the control signal (Cs) from the control module 3. The switching module 4 is operable to output, in response to the control signal (Cs), one of the second reference voltage (Vrf2) and the predetermined regulated voltage (Vre) to serve as a switching voltage (Vs). It is noted that, in this embodiment, when the feedback voltage (VFB) has been greater than the predetermined regulated voltage (Vre) for the predetermined period of time, the switching module 4 outputs the predetermined regulated voltage (Vre) as the switching voltage (Vs); otherwise, the second reference voltage (Vrf2) is outputted as the switching voltage (Vs).
The conversion module 5 is used to receive the DC input voltage (Vin), and is coupled to the reference voltage generation module 1, the control module 3 and the switching module 4. The conversion module 5 further receives the first reference voltage output (Vrf1) from the reference voltage generation module 1, and the switching voltage (Vs) from the switching module 4. The conversion module 5 is operable to generate, based on the DC input voltage (Vin), the first reference voltage output (Vrf1) and the switching voltage (Vs), the DC output voltage (Vout) and the feedback voltage (VFB).
In this embodiment, referring further to FIG. 7, the conversion module 5 may have, for example, its configuration and operation similar to those of the conversion module 5′ of FIG. 2B. The conversion module 5 of FIG. 7 differs from the conventional module 5′ of FIG. 2B in that the gate of the third transistor 513 receives the switching voltage (Vs) from the switching module 4 and that the voltage division circuit 52 further outputs the feedback voltage (VFB) that is a voltage across the second and third resistors 523, 524. It is noted that the DC output voltage (Vout) is greater than the feedback voltage (VFB), and the feedback voltage (VFB) is greater than the divided voltage (Vd). Thus, the amplified signal (As) is generated by the error amplifier circuit 51 based on the first to third voltages (V1-V3) (i.e., the first reference voltage output (Vrf1)), on the switching voltage (Vs) and on the divided voltage (Vd).
As an example, the ratio of the DC output voltage (Vout) to the feedback voltage (VFB) is 50/16. Initially, when the DC input voltage (Vin) increases in a way that the DC output voltage (Vout) gradually increases, for example, from 0V to about 3V, the voltage regulation circuit 31 of the control module 3 is able to generate the predetermined regulated voltage (Vre) of about 1.2V. In this case, since the feedback voltage (VFB) being 0.96V (=3×16/50V) is less than the predetermined regulated voltage (Vre), all the D-type flip-flops 352-355 (FIG. 6) are reset/cleared. Thereafter, when the DC output voltage (Vout) is greater than 3.75V (=1.2×50/16V), the counting unit 35 begins to count from 0000 to 1000. At the same time, the feedback voltage (VFB) has been greater than the predetermined regulated voltage (Vre) for the predetermined period of time. Thus, the switching module 4 outputs the predetermined regulated voltage (Vre) as the switching voltage (Vs) in response to the control signal (Cs) from the logic unit 36 (FIG. 5). As a result, the conversion module 5 is able to stably output the DC output voltage (Vout) of 5V based on the switching voltage (Vs) and the first reference voltage output (Vrf1) (FIG. 3).
To sum up, due to the presence of the control module 3 and the switching module 4, the regulator of this disclosure can convert the DC input voltage (Vin) into the DC output voltage (Vout) in a stable way regardless of variation in the DC input voltage (Vin).
While the disclosure has been described in connection with what is considered the exemplary embodiment, it is understood that this disclosure is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
Patent Application
20170031374
