Patent Application
20240036595
This application claims the priority benefit of Italian Application for Patent No. 102022000016128, filed on Jul. 29, 2022, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.
The description relates to linear voltage regulators, in particular to low-dropout (LDO) voltage regulators.
Low-dropout linear voltage regulator circuits are analog intellectual property (IP) blocks commonly used in modern electronic systems. Linear regulators are usually in the form of integrated circuits that step a voltage down from a higher voltage to a lower voltage without the need of an (external) inductor, contrarily to other step-down DC-DC converters such as switching buck converters.
In particular, LDO regulators may be used within complex electronic systems, such as Systems-on-Chip (SoC) for Internet-of-Things (IoT) applications, to provide a regulated supply voltage to one or more components of such systems.
By way of example,
In various applications as exemplified in
In various applications, the design of the LDO regulator represents an important task. In particular, the way in which the error amplifier 208 is designed has an impact on the performance of the whole regulator, insofar as the quiescent current consumption, the drop-out region, the transient response and the efficiency are concerned. Specifically, in portable systems, there is a need of reducing the current consumption in order to extend the battery life; in this scenario, LDO regulators play an important role since the quiescent current consumption is mainly set by these circuits. Moreover, requirements in terms of load regulation, line regulation and reduced overshoot and undershoot should also be met.
Maintaining a low power consumption results in reducing the energy provided by the battery (e.g., battery 12 in
Some solutions have been proposed to improve the settling time and to reduce overshoot and undershoot of LDO regulators, as discussed in the following documents (all of which are incorporated herein by reference):
[1] Y. Lee and K. Chen, “A 65 nm sub-1V multi-stage low-dropout (LDO) regulator design for SoC systems,” 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 2010, pp. 584-587, doi: 10.1109/MWSCAS.2010.5548893;
[2] A. Saberkari, E. Alarcon, and S. Shokouhi, “Fast transient current-steering CMOS LDO regulator based on current feedback amplifier,” Integration, the VLSI journal, vol. 46, no. 2, pp. 165-171, March 2013, doi: 10.1016/j.vlsi.2012.02.001; and
[3] M. Al-Shyoukh, H. Lee and R. Perez, “A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation,” in IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1732-1742, August 2007, doi: 10.1109/JS SC.2007.900281.
However, such known solutions show a quiescent current in the order of several microAmperes (1 μA=10−6 A) to maintain an acceptable transient response as well as overshoot/undershoot values.
Therefore, there is a need in the art to provide improved linear voltage regulators having a low current consumption, low overshoot and undershoot during output transients, and low settling time.
There is a need in the art to contribute in providing such improved linear voltage regulators.
One or more embodiments may relate to a voltage regulator circuit.
One or more embodiments may relate to a corresponding method of operating a voltage regulator circuit.
According to a first aspect of the present description, a voltage regulator circuit includes a first input terminal and a second input terminal configured to receive an input voltage therebetween. The voltage regulator circuit includes a first output terminal and a second output terminal configured to produce a regulated output voltage therebetween. The second input terminal and the second output terminal are coupled to a ground node. The voltage regulator circuit includes a feedback network configured to produce a feedback voltage indicative of the regulated output voltage. The voltage regulator circuit includes an error amplifier configured to produce a drive signal as a function of a difference between the feedback voltage and a reference voltage. The voltage regulator circuit includes a pass element arranged between the first input terminal and the first output terminal configured to receive the drive signal. The conductivity of the pass element is modulated as a function of the drive signal. The voltage regulator circuit includes an output transistor arranged between the first output node and the ground node. The voltage regulator circuit includes a mode selection circuit configured to receive a mode selection signal and to control the output transistor as a function thereof. In response to the mode selection signal being asserted, the mode selection circuit turns on the output transistor to sink a current with a controlled magnitude from the first output node. In response to the mode selection signal being de-asserted, the mode selection circuit sinks a current with a controlled magnitude from a control terminal of the output transistor to turn off the output transistor at a controlled rate.
One or more embodiments may thus facilitate providing a linear voltage regulator having a low current consumption, as well as low overshoot and undershoot during output transients.
In one or more embodiments, the mode selection circuit includes a first current conduction path including a first current source configured to source a first current, an enabling transistor, and a diode-connected transistor arranged in series between a power supply node and the ground node. The enabling transistor is configured to receive the mode selection signal at a respective control terminal. The enabling transistor is switched to a conductive state in response to the mode selection signal being asserted and to a non-conductive state in response to the mode selection signal being de-asserted. A control terminal of the diode-connected transistor is coupled to a control terminal of the output transistor.
In one or more embodiments, the mode selection circuit includes a set of coupling transistors having their current conduction paths arranged in series between the control terminal of the diode-connected transistor and the control terminal of the output transistor. The coupling transistors are configured to receive the mode selection signal at their respective control terminals. The coupling transistors are switched to a conductive state in response to the mode selection signal being asserted and to a non-conductive state in response to the mode selection signal being de-asserted.
In one or more embodiments, the mode selection circuit includes a capacitor coupled between a control terminal of the enabling transistor and the ground node.
In one or more embodiments, the mode selection circuit includes a gate-controlling transistor having its current conduction path arranged between the control terminal of the diode-connected transistor and the ground node. The gate-controlling transistor is configured to receive the complement of the mode selection signal at a respective control terminal. The gate-controlling transistor is switched to a conductive state in response to the mode selection signal being de-asserted and to a non-conductive state in response to the mode selection signal being asserted.
In one or more embodiments, the mode selection circuit includes a current mirror arrangement configured to selectively sink a second current from the control terminal of the output transistor in response to the mode selection signal being de-asserted.
In one or more embodiments, the mode selection circuit includes a further enabling transistor having its current conduction path arranged between the current mirror arrangement and the control terminal of the output transistor. The further enabling transistor is configured to receive the complement of the mode selection signal at a respective control terminal. The further enabling transistor is switched to a conductive state in response to the mode selection signal being de-asserted and to a non-conductive state in response to the mode selection signal being asserted.
In one or more embodiments, the mode selection circuit includes a further gate-controlling transistor having its current conduction path arranged between a control terminal of the current mirror arrangement and the ground node. The further gate-controlling transistor is configured to receive the mode selection signal at a respective control terminal. The further gate-controlling transistor is switched to a conductive state in response to the mode selection signal being asserted and to a non-conductive state in response to the mode selection signal being de-asserted.
In one or more embodiments, the voltage regulator circuit includes a capacitor coupled between a control terminal of the output transistor and a control terminal of the pass element.
In one or more embodiments, the voltage regulator circuit includes an output capacitor coupled between the first output node and the second output node.
According to another aspect of the present description, a method of operating a voltage regulator circuit includes: receiving an input voltage between the first input terminal and the second input terminal; producing a regulated output voltage between the first output terminal and the second output terminal; producing a feedback voltage indicative of the regulated output voltage at the feedback network; producing a drive signal as a function of a difference between the feedback voltage and a reference voltage at the error amplifier; receiving the drive signal at the pass element, modulating the conductivity of the pass element as a function of the drive signal; receiving, at the mode selection circuit, a mode selection signal and controlling the output transistor as a function thereof; in response to the mode selection signal being asserted, turning on the output transistor to sink a current with a controlled magnitude from the first output node; and in response to the mode selection signal being de-asserted, sinking a current with a controlled magnitude from a control terminal of the output transistor to turn off the output transistor at a controlled rate.
One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:
In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.
Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is included in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments.
The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.
Throughout the figures annexed herein, unless the context indicates otherwise, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for the sake of brevity.
As anticipated, an LDO voltage regulator according to one or more embodiments may aim at reducing current consumption, settling time, overshoot, and undershoot. In particular, one or more embodiments may satisfy one or more of the following specifications:
In one or more embodiments, an LDO voltage regulator is configured to operate in two different modes:
As exemplified in
As exemplified in
Therefore, in one or more embodiments a mode selection signal PULSE is received by the LDO regulator 30 in order to switch operation of the LDO regulator 30 from a low-power mode to a high-power mode (e.g., when the mode selection signal PULSE is asserted) and vice versa (e.g., when the mode selection signal PULSE is de-asserted). The mode selection circuit 300, using the input currents IPU (power-up) and IPD (power-down), controls (e.g., enables and disables) the power transistor 306 via the control signal CTR to modify the output stage of the LDO regulator 30, in order to provide smooth transitions from the low-current mode to the high-current mode (and vice versa), as well as low overshoot and/or low undershoot during the load current transients. When the LDO regulator 30 is switched to the high-current mode of operation, the load L can start drawing higher average current to perform the operation requested. At the end of the operation of the load L, the mode selection signal PULSE sets the LDO regulator 30 again in the low-current mode, so as to save power while waiting for a next request of operation by the load L. The high-power to low-power transition is dominated by the power-down current IPD that relaxes the mode selection circuit 300 turning off in order to prevent high overshoot, as further disclosed in the following.
A first portion of circuit 300 operates as a power-up circuit for power transistor 306 (also indicated as transistor M14 in
A second portion of circuit 300 operates as a power-down circuit for power transistor 306 (also indicated as transistor M14 in
The mode selection circuit 300 exemplified in
When implementing a low-power mode to high-power mode transition, the mode selection signal PULSE is asserted (e.g., set to a high logic value, ‘1’) by the load L (e.g., it turns on as directed, for example, by the digital circuit 54)). Transistor M13 is turned on by signal PULSE, as well as the series-connected transistors M16, M17, M18, M19 of the resistive chain between the gate terminals of transistors M15 and M14. Therefore, the current mirror composed by transistors M15 and M14 is enabled together with the resistive chain, so as to relax the turn-on phase of transistor M14 (e.g., gradually and/or slowly turning on transistor M14) and prevent large undershoot of the output voltage VOUT. Indeed, if transistor M14 were turned on quickly, the related current demand from the output node 204 would be sustained only by the output bypass capacitor CL possibly resulting in a large undershoot. To the contrary, in one or more embodiments as disclosed herein, the rising time of the mirrored current (i.e., the current flowing through transistor M14, which may be for instance in the vicinity of 10 μA) is rather long, thus allowing the error amplifier 208 to settle at its operating point, with the mirror current being provided by both the output capacitor CL and the pass element M24 (210). The undershoot of the output voltage VOUT is therefore controlled. Still during a low-power mode to high-power mode transition, transistor M23 is turned on and brings the gate terminals of transistors M25 and M22 to the ground voltage VGND, thereby turning off the mirror composed by transistors M25 and M22, whose operation is useful (only) during the high-power mode to low-power mode transitions to turn off the mode selection circuit 300. Still during a low-power mode to high-power mode transition, a p-channel MOS transistor arranged in parallel with the one that biases the input differential pair of the error amplifier 208 may additionally be turned on by the mode selection signal PULSE, in order to increase the bias current of the differential pair and therefore the bandwidth of the whole amplifier (e.g., operational transconductance amplifier, OTA). Increasing the current consumption of the first and second stage results in both the first and second pole being split at higher frequencies, therefore maintaining the phase margin higher than the critic threshold.
Therefore, in one or more embodiments during a low-power mode to high-power mode transition, and in particular during the current demands from the load L, the amplifier 208, which has become faster, tends to settle quickly so that the undershoot is controlled (e.g., the output voltage VOUT is maintained above 1 V). When the load L stops its current demand, the extra current provided by the pass element 210 (e.g., by transistor M24) is split in two parts, one flowing through transistor M14 and the other one (which is smaller) flowing through the output capacitor, instead of flowing entirely through capacitor CL. In this way, the overshoot is controlled (e.g., the output voltage VOUT is maintained below 1.32 V).
When implementing a high-power mode to low-power mode transition, the mode selection signal PULSE is de-asserted (e.g., set to a low logic value, ‘0’) by the load L (e.g., it turns off as directed, for example, by the digital circuit 54). Transistors M20 and M21 are turned on (e.g., activated) by signal PULSE. Transistor M20 operates as a switch that, when activated, ties the gate terminal of transistor M15 to the ground voltage VGND, and therefore turns off transistor M14 (e.g., the amplifier operates again as a class A amplifier). Transistor M21 enables a low-impedance path from the gate of transistor M14 to the ground node. Still during a high-power mode to low-power mode transition, the current mirror including transistors M25 and M22 turns on, insofar as transistor M23 is now turned off. The current flowing through transistor M22 is determined by the mirror factor and by the magnitude of the power-down current IPD provided by the current source 304, thus the parasitic (gate) capacitance of transistor M14 is discharged at a controlled rate determined by a constant and/or programmable current IPD. In this way, transistor M14 can be turned off slowly. In the absence of such a current control during the discharge phase of the gate capacitance of transistor M14, the turn-off phase of transistor M14 would result in an over-current and, consequently, an overshoot of the output voltage VOUT.
Therefore, one or more embodiments as disclosed herein may provide a fully integrated (e.g., fully on-chip) LDO regulator that is capable to prevent large overshoot and undershoot with small integrated capacitances (e.g., in the range of 0.5 nF to 1.5 nF, three orders of magnitude smaller than the capacitances of conventional solutions that rely on external capacitors). Additionally, operation of an LDO regulator as disclosed herein may be stable with a starting load current of 0 A.
One or more embodiments may thus provide the following performance: output capacitance (e.g., integrated) in the range of 0.5 nF to 1.5 nF, without the need of providing chip pads of connecting an external output capacitor; current consumption in the low-power operation mode of about 0.15 μA; current consumption in the high-power operation mode of about 25 μA; duration of the transient from the low-power operation mode to the high-power operation mode of about 250 μs, and overshoot and/or undershoot limited to about 100 mV.
Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.
The claims are an integral part of the technical teaching provided herein in respect of the embodiments.
The extent of protection is determined by the annexed claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102022000016128 | Jul 2022 | IT | national |
